CN100578466C - 用于基于集线器的存储器子系统中的双向数据总线的数据旁路的装置和方法 - Google Patents
用于基于集线器的存储器子系统中的双向数据总线的数据旁路的装置和方法 Download PDFInfo
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- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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Abstract
一种存储集线器,包括:第一和第二链路接口,其耦合到各自数据总线;数据路径,其耦合到所述第一和第二链路接口并且通过所述数据路径在所述第一和第二链路接口之间传送数据;还包括写旁路电路,其耦合到所述数据路径来耦合所述数据路径上的写数据并且临时存储所述写数据,以便在所述写数据被临时存储时允许在所述数据路径上传送读数据。提供一种用于向存储器系统中的存储器单元写入数据的方法,其包括访问存储器系统中的读数据,向存储器系统提供写数据,以及把写数据耦合到寄存器以便临时存储。在提供了读数据之后,写数据被再耦合到存储器总线并且被写入存储器单元。
Description
相关申请的交叉引用
本申请要求于2004年2月5日提交的、题目为“APPARATUSAND METHOD FOR DATA BYPASS FOR A BI-DIRECTIONALDATA BUS IN A HUB-BASED MEMORY SUB-SYSTEM”的美国专利申请No.10/773,583的申请日的权益,在此将其引入作为参考。
技术领域
本发明涉及存储器系统,并且尤其涉及具有数据旁路以防止双向数据总线上的数据冲突的存储器模块。
背景技术
计算机系统使用诸如动态随机访问存储器(“DRAM”)之类的存储器设备来存储被处理器访问的数据。这些存储器设备通常被用作计算机系统中的系统存储器。在一个典型的计算机系统中,处理器通过处理器总线和存储器控制器与系统存储器通信。系统存储器的存储器设备(一般被安置在具有多个存储器设备的存储器模块中)通过存储器总线耦合到存储器控制器。处理器发出存储器请求,该存储器请求包括比如读命令的存储器命令以及地址,该地址指定将从其读取数据或指令的存储器单元。存储器控制器使用命令和地址来生成合适的命令信号以及行地址和列地址,它们通过存储器总线被施加到系统存储器。响应于所述命令和地址,在系统存储器和处理器之间传送数据。存储器控制器通常是系统控制器的一部分,系统控制器还包括总线桥接电路,以用于将处理器总线耦合到诸如PCI总线之类的扩展总线。
在存储器系统中,高数据带宽是所希望的。通常,带宽限制不涉及存储器控制器,这是因为存储器控制器按存储器设备所允许的速度尽快排序数据往返于系统存储器。一个被采用来增加带宽的方案是增加将存储器控制器耦合到存储器设备的存储器数据总线的速度。从而,在更短的时间内可以通过存储器数据总线移送相同的信息量。然而,尽管增加了存储器数据总线的速度,却没有实现带宽的相应增加。数据总线速度和带宽之间的非线性关系的一个原因是存储器设备自身内的硬件限制。也就是说,存储器控制器必须调度到存储器设备的所有存储器命令,以便兑现(honor)硬件限制。尽管可以通过存储器设备的设计而一定程度地降低这些硬件限制,然而由于降低硬件限制通常增加存储器设备的成本、功率、和/或大小(这些都是不希望的选择)而必须做出折衷。因此,考虑到这些约束条件,尽管以曾经增加的速率移动“表现好的”业务(例如,到存储器设备的同一页面的结局业务(sequel traffic))对存储器设备而言是容易的,然而要解决“表现不好的”业务(比如在存储器设备的不同页面或存储体之间弹跳)对存储器设备而言却更加困难。结果是,存储器数据总线带宽的增加不会导致信息带宽的相应增加。
除了处理器和存储器设备之间的受限带宽之外,计算机系统的性能还受限于延时问题,所述延时问题增加了从系统存储器设备读取数据所需的时间。更具体地,当存储器设备读命令被耦合到诸如同步DRAM(“SDRAM”)设备之类的系统存储器设备时,所述读数据只能在几个时钟周期的延迟之后才被输出。因此,尽管SDRAM设备能够以高数据速率同步输出突发数据,然而初始提供数据时的延迟可以极大地降低使用这类SDRAM设备的计算机系统的操作速度。增加存储器数据总线速度可以被用来帮助缓解延时问题。然而,基本上由于之前所述的相同原因,存储器数据总线速度的增加在给出带宽的情况下没有导致延时的线性减少。
尽管增加存储器数据总线速度在某种程度上已经成功地增加了带宽并且减少了延时,然而这个方法却引发了其它的问题。例如,随着存储器数据总线速度的增加,存储器总线上的负荷需要被减少以便保持信号完整性,这是因为存储器控制器和插入存储器模块的存储器插槽之间在传统上只存在连线。若干方案已经被采用来提供存储器数据总线速度的增加。例如,减少存储器插槽的数量、增加存储器模块上的缓冲器电路以便向存储器模块上的存储器设备提供充足的控制信号输出,并且因为在单个存储器设备接口上的存储器模块连接器太少,所以在存储器模块上提供多个存储器设备接口。然而,这些传统方案的效果被限制。这些技术在过去被使用的原因在于那样做是成本节约的。然而,当在每个接口中只能插入一个存储器模块时,对于每个所需的存储器插槽都添加一个分离的存储器接口变得成本太高。换言之,它将系统控制器组从日用品范围中推出而进入精品范围,从而极大地增加了成本。
近来,一个用成本节约的方式来增加存储器数据总线速度的新方法是使用经由存储器集线器耦合到处理器的多个存储器设备。在存储器集线器架构或基于集线器的存储器子系统中,系统控制器或存储器控制器通过高速双向或单向存储器控制器/集线器接口耦合到若干个存储器模块。典型情况下,存储器模块以点到点或菊链架构的方式耦合以便存储器模块彼此逐个串联。从而,存储器控制器耦合到第一存储器模块,而第一存储器模块连接到第二存储器模块,第二存储器模块又耦合到第三存储器模块,以菊链方式依此类推。
每个存储器模块都包括一个存储器集线器,其被耦合到该模块上的存储器控制器/集线器接口和多个存储器设备,其中存储器集线器有效率地通过存储器控制器/集线器接口在控制器和存储器设备之间路由存储器请求和响应。采用这种架构的计算机系统可以使用一个高速存储器数据总线,这是因为在存储器数据总线上可以保持信号完整性。而且,这种架构还提供了对系统存储器的容易扩展,而不用考虑在添加更多存储器模块时的信号质量降级,比如在传统的存储器总线结构中发生的信号质量降低。
尽管使用存储器集线器的计算机系统可以提供较高性能,然而它们通常由于各种原因而无法以最佳效率操作。一个此种原因是管理经由存储器总线在存储器控制器往返流动的数据之间的数据冲突的问题。在常规的存储器控制器中,一个被采用来避免数据冲突的方案是延迟一个存储器命令的执行,直到另一个存储器命令完成为止。例如,利用常规的存储器控制器,在读命令后发出的写命令不被允许开始,直到所述读命令几乎完成为止,从而避免所述读(例如,输入)数据在存储器总线上与写(例如,输出)数据发生数据冲突。然而,强迫写命令等待有效地降低带宽,这与一般在存储器系统中所期望的不一致。
发明内容
根据本发明的第一方面,提供一种用于基于集线器的存储器模块的存储器集线器,包括:第一和第二链路接口,用于耦合到各自数据总线;双向数据路径,其耦合到所述第一和第二链路接口,并且通过所述双向数据路径在所述第一和第二链路接口之间传送数据;和写旁路电路,其耦合到所述双向数据路径以耦合所述双向数据路径上的要被向下游传送的写数据,并且在读命令之后且在所述读命令完成之前发出写命令时,所述写旁路电路被配置为临时存储所述写数据,以便在所述写数据被临时存储时允许通过所述双向数据路径向上游传送读数据。
根据本发明的第二方面,提供一种存储器模块,包括:多个存储器设备;和存储器集线器,其耦合到所述多个存储器设备,所述存储器集线器包括:第一和第二链路接口,用于耦合到各自数据总线;双向数据路径,其耦合到所述第一和第二链路接口,并且可以通过所述双向数据路径在所述第一和第二链路接口之间传送数据;和写旁路电路,其耦合到所述双向数据路径来耦合所述双向数据路径上的要被向下游传送的写数据,并且在读命令之后且在所述读命令完成之前发出写命令时,所述写旁路电路被配置为临时存储所述写数据,以便在所述写数据被临时存储时允许通过所述双向数据路径向上游传送读数据。
根据本发明的第三方面,提供一种基于处理器的系统,包括:处理器,具有处理器总线;系统控制器,其耦合到所述处理器总线,所述系统控制器具有系统存储器端口和外围设备端口;至少一个输入设备,其耦合到所述系统控制器的外围设备端口;至少一个输出设备,其耦合到所述系统控制器的外围设备端口;至少一个数据存储设备,其耦合到所述系统控制器的外围设备端口;和存储器模块,其耦合到所述系统控制器的系统存储器端口,所述存储器模块包括:多个存储器设备;和存储器集线器,其耦合到所述多个存储器设备,所述存储器集线器包括:第一和第二链路接口,用于耦合到各自数据总线;双向数据路径,其耦合到所述第一和第二链路接口并且通过所述双向数据路径在所述第一和第二链路接口之间传送数据;和写旁路电路,其耦合到所述双向数据路径来耦合所述双向数据路径上的要被向下游传送的写数据,并且在读命令之后且在所述读命令完成之前发布写命令时,所述写旁路电路被配置为临时存储所述写数据,以便在所述写数据被临时存储时允许通过所述双向数据路径向上游传送读数据。
根据本发明的第四方面,提供一种用于将数据写入存储器系统中的存储器单元的方法,所述存储器系统包括与双向存储器总线耦合的多个存储器模块,所述方法包括:向所述存储器系统发出读命令;在发出所述读命令之后并且在所述读命令完成之前,在所述双向存储器总线上向所述存储器系统提供写命令和相应的写数据;将所述写数据耦合到所述存储器系统中的寄存器以用于临时存储所述写数据,以便在所述写数据被提供到所述双向存储器总线之后并且在所述写数据被写入之前,允许读数据在所述双向存储器总线上返回;将所述读数据耦合到所述双向存储器总线并且提供所述读数据以用于读取;将所述寄存器中存储的所述写数据耦合到所述双向存储器总线;并且将所述写数据写入所述存储器单元。
根据本发明的第五方面,提供一种用于在存储器系统中执行存储器命令的方法,所述存储器系统包括耦合到双向存储器总线的多个存储器模块,所述方法包括:向所述存储器系统发出读命令;在所述读命令完成之前,向所述存储器系统中的存储器单元发出写命令并且向所述存储器系统的双向存储器总线提供写数据;访问所述存储器系统中的读数据;在所述存储器系统中,旁路电路从所述双向存储器总线临时捕获所述写数据;在所述双向存储器总线上从所述存储器系统接收所述读数据;将所述写数据释放到所述双向存储器总线;和恢复到所述存储器单元的所述写命令。
根据本发明的第六方面,提供一种用于在存储器系统中执行读命令和写命令的方法,所述存储器系统包括耦合到双向存储器总线的多个存储器模块,所述方法包括:发出读命令来访问所述存储器系统中的第一存储器单元;在所述读命令完成之前,调度写命令来向所述存储器系统中的第二存储器单元写入数据;从所述第一存储器单元取回读数据;向所述存储器系统的双向存储器总线提供与所述写命令相对应的写数据;在所述存储器系统中,旁路电路在所述双向存储器总线上临时捕获所述写数据;在所述双向存储器总线上从所述存储器系统接收所述读数据;并且向所述双向存储器总线释放所述写数据。
附图说明
图1是具有其中可以实施本发明的实施例的存储器集线器结构中的存储器模块的计算机系统的方框图;
图2是与图1的存储器模块一起使用的根据本发明实施例的存储器集线器的局部方框图;
图3是用于根据本发明实施例的图2的存储器集线器的数据旁路电路的方框图;
图4是说明具有图1的存储器集线器结构和图2的存储器集线器的计算机系统的图3的数据旁路电路的操作的方框图。
具体实施方式
本发明的实施例旨在具有旁路电路的存储器集线器,该旁路电路在基于集线器的存储器子系统中提供用于双向数据总线的数据旁路。某些细节在下面阐述,以提供对本发明的各种实施例的充分理解。然而,对于本领域的一个技术人员而言很清楚的是,本发明可以在不需要这些具体的细节的情况下实践。在其它情况下,公知的电路、控制信号、以及定时协议没有被详细示出以避免不必要地模糊本发明。
图1例示了根据本发明的一个实施例的计算机系统100。计算机系统100包括用于执行各种计算功能的处理器104,比如运行特定的软件来执行特定的计算或任务。处理器104包括处理器总线106,该处理器总线106通常包括地址总线、控制总线、和数据总线。处理器总线106通常被耦合到高速缓存存储器108。通常,高速缓存存储器108由静态随机访问存储器(“SRAM”)提供。处理器总线106还耦合到系统控制器110,其有时被称为总线桥。
对于各种其它组件,系统控制器110起到到处理器104的通信路径的作用。例如,如图1所示,系统控制器110包括通常被耦合到图形控制器112的图形端口。图形控制器通常被耦合到诸如视频显示器之类的视频终端114。系统控制器110还被耦合到一个或多个诸如键盘或鼠标之类的输入设备118,以便允许操作员与计算机系统100交互。通常,计算机系统100还包括一个或多个诸如打印机之类的输出设备120,它们通过系统控制器110被耦合到处理器104。一个或多个数据存储设备124还经由系统控制器110被耦合到处理器104,从而允许处理器将数据存储到内部或外部存储介质(未示出)或者从内部或外部存储介质取回数据。典型的存储设备124的例子包括硬盘和软盘、盒式磁带、以及紧凑磁盘只读存储器(“CD-ROM”)。
系统存储器110包括存储器集线器控制器128,其被耦合到若干个存储器模块130a、130b、130c、…130n的存储器集线器140。所述存储器模块130起计算机系统100的系统存储器的作用,并且被优选地通过高速双向存储器控制器/集线器接口134耦合到存储器集线器控制器128。存储器模块130被示出以点对点布置的方式耦合到存储器集线器控制器128,其中,存储器控制器/集线器接口134通过存储器模块130的存储器集线器140而耦合。即,存储器控制器/集线器接口134是用于串联耦合存储器集线器140的双向总线。因此,存储器控制器/集线器接口134上的信息必须传播通过“上游”存储器模块130的存储器集线器从而到达“下游”目的地。例如,通过具体参考图1,从存储器集线器控制器128发送到存储器模块130c的存储器集线器140的信息将穿过存储器模块130a和130b的存储器集线器140。
然而,应当明白的是,也可以使用除了图1的点到点布置之外的其它拓扑结构。例如,可以使用耦合布置,其中,分离的高速链路(未示出)被用来将每个存储器模块130都耦合到存储器集线器控制器128。还可以使用交换拓扑,其中,存储器集线器控制器128通过交换机(未示出)被选择性地耦合到每一个存储器模块130。其它可以使用的拓扑对于本领域的技术人员来说是显而易见的。另外,将存储器模块耦合到存储器集线器控制器的存储器控制器/集线器接口134可以是电或光通信路径。然而,其它类型的通信路径也可以被用于存储器控制器/集线器接口134。如果存储器控制器/集线器接口134被实现为光通信路径,则该光通信路径的形式可以是一条或多条光纤。在这类情况下,如在本领域中所熟知的,存储器集线器控制器128和存储器模块将包括光输入/输出端口,或者被耦合到所述光通信路径的分离的输入和输出端口。
存储器集线器140控制对各个存储器模块130的存储器设备148的访问。在图1中,存储器设备被例示为同步动态随机访问存储器(“SDRAM”)设备。然而,可以使用除了SDRAM设备之外的存储器设备。还如图1中所示,存储器集线器通过各个存储器总线150耦合到四个存储器设备组148。对于每个存储器模块130的总共20个存储器设备148,每组存储器设备都包括四个存储器设备148。如在本领域中所公知的,存储器总线150通常包括控制总线、地址总线、和数据总线。然而,本领域的那些普通技术人员应该明白,诸如使用共享的命令/地址总线的总线系统之类的其它总线系统也可以在不脱离本发明范围的情况下被使用。而且还应当明白,存储器设备148的布置和存储器设备148的数量可以在不脱离本发明范围的情况下被修改。
图2例示了根据本发明实施例的存储器集线器140的一部分。存储器集线器140包括耦合到存储器控制器/集线器接口134(图1)的本地集线器电路214。本地集线器电路214还通过存储器总线150耦合到存储器设备148。本地集线器电路214包括控制逻辑,用于处理从存储器控制器128发出的存储器命令并且用于通过存储器总线150来访问存储器设备148,以便在存储器命令被导引到各个存储器模块130时提供相应的数据。这类控制逻辑的设计和操作对于本领域中的那些技术人员来说是公知的,并且因此,为了简洁起见,可以在此省略更多的详细说明。存储器集线器140还包括耦合到本地集线器电路214的数据旁路电路286。如在下文中将被更详细解释的,数据旁路电路286被用来临时捕获向远距离存储器集线器传递的数据,从而允许从另一远距离存储器集线器返回的数据可以在所捕获的数据继续在该远距离存储器集线器上之前穿过存储器集线器140。因此,数据旁路电路286提供了一个数据旁路机制,其可以被用来避免在与存储器集线器140耦合的双向存储器控制器/集线器接口134上的数据冲突。
如上所述,常规的存储器子系统用来避免数据冲突的一个方法是延迟一个存储器命令的执行,直到另一个存储器命令完成为止。例如,在典型的存储器系统中,在读命令之后发出的写命令将不会被允许在该读命令几乎完成之前开始,以便避免读(即,输入)数据在存储器控制器/集线器接口134上与写(即,输出)数据发生冲突。与之相反,通过采用具有数据旁路电路286的存储器集线器140,与常规的存储系统相比较,在读命令之后发出的写命令可以被排序得较早,并且因此,在较早调度的写命令之后调度的存储器命令可以被尽早地执行。
图3说明了根据本发明实施例的数据旁路电路300。数据旁路电路300可以用来替代数据旁路电路286(图2),并且可以使用本领域技术人员所熟知的常规设计和电路来实现。数据旁路电路300包括输入缓存器302,其接收输入写数据WR_DATA_IN并且向旁路寄存器/FIFO 304和复用器306的第一输入端提供相同的数据。旁路寄存器/FIFO 304的输出端被耦合到复用器306的第二输入端。旁路选择逻辑308产生的使能信号EN选择两个输入端中的哪一个来耦合到复用器306的输出端。EN信号还被提供给输入/输出缓存器310,作为用于激活或去激活输入/输出缓存器310的输出使能信号。旁路选择逻辑308响应于由存储器集线器控制器128(图1)提供的激活信号BYPASS_EN而产生适当的EN信号。或者,BYPASS_EN信号可以从作为同一存储器系统的一部分的其它存储器集线器(未示出)提供。数据旁路电路的电路是常规的,并且应当明白,数据旁路电路300的电路可以用本领域中熟知的常规设计和电路来实现。
在操作中,数据旁路电路300所接收的WR_DATA_IN通过输入缓存器302被驱动并且被提供给复用器306的第一输入端。WR_DATA_IN还被保存在旁路寄存器/FIFO 304中。响应于无效的BYPASS_EN信号,旁路选择逻辑308产生有效的EN信号。有效的EN信号使得输入/输出缓存器310能够输出并且能够通过复用器306将输入缓存器302的输出端耦合到输入/输出缓存器310的输入端。因此,WR_DATA_IN被直接提供给输入/输出缓存器310的输入端,并且WR_DATA_IN通过数据旁路电路300被提供而无须任何旁路。然而,响应于有效的BYPASS_EN信号,旁路选择逻辑308产生无效的EN信号,从而禁止输入/输出缓存器310的输出功能并且将其输出端置于高阻状态。另外,无效的EN信号将输入/输出缓存器310的输入端耦合到旁路寄存器/FIFO 304的输出端。按照这种方式,WR_DATA_IN被数据旁路电路300接收,由旁路寄存器/FIFO 306存储,并且被施加到输入/输出缓存器310的输入端。然而,由于EN信号的无效状态,WR_DATA_IN没有作为输出数据WR_DATA_OUT由输入/输出缓存器310提供。结果是,WR_DATA_IN被保持在旁路状态中,直到BYPASS_EN信号变成无效为止,在那时,EN信号又变成有效,从而使得输入/输出缓存器310能够将WR_DATA_IN作为WR_DATA_OUT提供。复用器306还被切换回将输入缓存器302的输出端直接耦合到输入/输出缓存器310的输入端,从而允许WR_DATA_IN能够没有受阻碍地穿过数据旁路电路。
数据旁路电路286的操作将参考图4来描述。图4类似于图1,不同之处在于图4被简化了。特别地,图1的许多功能块已经被省略,而只示出了存储器模块130a-130c,并且由存储器集线器140a-140c来表示。只有一个存储器设备148a-148c被示出通过一个相应的存储器总线150a-150c耦合到一个相应的存储器集线器140a-140c。如同在图1中,存储集线器140a-140c被高速双向存储器控制器/集线器接口134耦合到存储器集线器控制器128。
在图4中,假定存储器集线器控制器128刚发出读命令和写命令,其中,读命令在写命令之前被排序。读命令被导引到存储器模块130b并且写命令被导引到存储器模块130c。即,将写入数据的存储器模块是将从中读取数据的存储器模块的下游。响应于读命令,存储器集线器140b开始从存储器设备148b取回读数据(RD),如图4中由“(1)”所指示。读命令发出之后,写命令然后被启动,并且写数据(WD)被提供到存储器控制器/集线器接口134上。然而,因为存储器集线器控制器128正期待RD从存储器模块130b返回,所以存储器集线器140a被导引来捕获其数据旁路电路286a中的WD。结果是,如图4中“(2)”所指示,存储器集线器286a捕获WD以清除存储器控制器/集线器接口134,以用于RD返回到存储器集线器控制器128。当存储器集线器140b从存储器设备148b取回RD时,随后通过存储器控制器/集线器接口134将RD提供给存储器集线器控制器128以便完成读请求,如图4中”(3)”所指示。当穿过存储器集线器140a的RD在其到存储器集线器控制器128的途中时,存储器集线器140a从数据旁路电路286a释放WD来继续向存储器集线器140c前进。通过高速链路将WD提供给存储器集线器140c,该高速链路现在在存储器集线器140a和140c之间被清空。如图4中的”(4)”所指示,当到达存储器集线器140c时,WD被写入存储器设备148c。在本发明的实施例中,存储器控制器/集线器接口上并且通过数据旁路电路286的RD和WD数据流的协调受存储器集线器控制器128的控制。例如,在先前的例子中,存储器集线器控制器确保,当从存储器模块130b取回RD时,与RD反向的任何WD流都不挡道(out of the way)。然而应当明白,在替换实施例中,经过存储器控制器/集线器接口134和数据旁路电路286的数据流可以被不同地管理,比如存储器集线器控制器128与存储器集线器140共享数据流的协调。
在先前的例子中,如常规的存储器系统中那样,RD被返回给存储器集线器控制器128。即,存储器设备148发送的RD被没有任何重大延迟地提供给存储器控制器。然而,通过采用先前描述的数据旁路机制,与常规的存储系统相比,写数据可以被调度得更早。在典型的存储器系统中,在读命令之后发出的写命令将不被允许开始,直到读命令几乎完成为止。与之相反,本发明的实施例允许随后发出的写命令被调度得较早,从而减小了读命令和写命令之间的时间间隔。结果是,在较早调度的写命令之后调度的命令具有总体降低的延迟。
从上述应当明白,虽然为了说明目的而在此已经对本发明的具体实施例进行了描述,但是在不脱离本发明的精神和范围的情况下可以做出各种修改。因此,本发明只由附加的权利要求来限定。
Claims (24)
1、一种用于基于集线器的存储器模块的存储器集线器,包括:
第一和第二链路接口,用于耦合到各自数据总线;
双向数据路径,其耦合到所述第一和第二链路接口,并且通过所述双向数据路径在所述第一和第二链路接口之间传送数据;和
写旁路电路,其耦合到所述双向数据路径以耦合所述双向数据路径上的要被向下游传送的写数据,并且在读命令之后且在所述读命令完成之前发出写命令时,所述写旁路电路被配置为临时存储所述写数据,以便在所述写数据被临时存储时允许通过所述双向数据路径向上游传送读数据。
2、如权利要求1所述的存储器集线器,其中,所述写旁路电路包括:
复用器,其具有耦合到所述数据路径的第一输入端并且还具有第二输入端、输出端和选择端子,所述复用器根据被施加到所述选择端子的选择信号将所述输出端耦合到所述第一或第二输入端;
先入先出(FIFO)寄存器,其具有耦合到所述数据路径的输入端并且还具有耦合到所述复用器的第二输入端的输出端;
输出缓存器,其具有耦合到所述复用器的输出端的缓存器输入端并且还具有缓存器输出端和激活端子,所述输出缓存器根据被施加到所述激活端子的激活信号将所述缓存器输入端耦合到所述缓存器输出端;以及
选择电路,在被激活时,其耦合到所述复用器来产生所述选择信号和激活信号,以将所述复用器的第二输入端耦合到所述复用器的输出端。
3、如权利要求2所述的存储器集线器,其中,所述写旁路电路还包括输入缓存器,其具有耦合到所述数据路径的输入端和耦合到所述复用器和所述FIFO寄存器的输入端的输出端。
4、如权利要求1所述的存储器集线器,还包括耦合到所述数据路径的存储器设备接口,所述存储器设备接口用于将数据耦合到至少一个与所述存储器设备接口耦合的存储器设备。
5、一种存储器模块,包括:
多个存储器设备;和
存储器集线器,其耦合到所述多个存储器设备,所述存储器集线器包括:
第一和第二链路接口,用于耦合到各自数据总线;
双向数据路径,其耦合到所述第一和第二链路接口,并且可以通过所述双向数据路径在所述第一和第二链路接口之间传送数据;和
写旁路电路,其耦合到所述双向数据路径来耦合所述双向数据路径上的要被向下游传送的写数据,并且在读命令之后且在所述读命令完成之前发出写命令时,所述写旁路电路被配置为临时存储所述写数据,以便在所述写数据被临时存储时允许通过所述双向数据路径向上游传送读数据。
6、如权利要求5所述的存储器模块,其中,所述存储器集线器的写旁路电路包括:
复用器,其具有耦合到所述数据路径的第一输入端并且还具有第二输入端、输出端和选择端子,所述复用器根据被施加到所述选择端子的选择信号将所述输出端耦合到所述第一或第二输入端;
先入先出(FIFO)寄存器,其具有耦合到所述数据路径的输入端并且还具有耦合到所述复用器的第二输入端的输出端;
输出缓存器,其具有耦合到所述复用器的输出端的缓存器输入端并且还具有缓存器输出端和激活端子,所述输出缓存器根据被施加到所述激活端子的激活信号将所述缓存器输入端耦合到所述缓存器输出端;和
选择电路,在被激活时,其耦合到所述复用器来产生所述选择信号和激活信号,以便将所述复用器的第二输入端耦合到所述复用器的输出端。
7、如权利要求6所述的存储器模块,其中,所述存储器集线器的写旁路电路还包括输入缓存器,所述输入缓存器具有耦合到所述数据路径的输入端和耦合到所述复用器和所述FIFO寄存器的输入端的输出端。
8、如权利要求5所述的存储器模块,其中,所述存储器集线器还包括存储器设备接口,其耦合到所述数据路径并且耦合到所述多个存储器设备中的至少一个,所述存储器设备接口用于将数据耦合到所述存储器设备。
9、如权利要求8的存储器模块,其中,所述存储器集线器的存储器设备接口包括:
存储器控制器,其通过存储器控制器总线耦合到所述数据路径,并且还通过存储器设备总线耦合到所述多个存储器设备中的至少一个;
写缓存器,其耦合到所述存储器控制器,以用于存储导引到与所述存储器控制器耦合的存储器设备的存储器请求;和
高速缓存存储器,其耦合到所述存储器控制器,以用于存储被提供给所述存储器设备或者从所述存储器设备取回的数据。
10、一种基于处理器的系统,包括:
处理器,具有处理器总线;
系统控制器,其耦合到所述处理器总线,所述系统控制器具有系统存储器端口和外围设备端口;
至少一个输入设备,其耦合到所述系统控制器的外围设备端口;
至少一个输出设备,其耦合到所述系统控制器的外围设备端口;
至少一个数据存储设备,其耦合到所述系统控制器的外围设备端口;和
存储器模块,其耦合到所述系统控制器的系统存储器端口,所述存储器模块包括:
多个存储器设备;和
存储器集线器,其耦合到所述多个存储器设备,所述存储器集线器包括:
第一和第二链路接口,用于耦合到各自数据总线;
双向数据路径,其耦合到所述第一和第二链路接口并且通过所述双向数据路径在所述第一和第二链路接口之间传送数据;和
写旁路电路,其耦合到所述双向数据路径来耦合所述双向数据路径上的要被向下游传送的写数据,并且在读命令之后且在所述读命令完成之前发出写命令时,所述写旁路电路被配置为临时存储所述写数据,以便在所述写数据被临时存储时允许通过所述双向数据路径向上游传送读数据。
11、如权利要求10所述的基于处理器的系统,其中,所述存储器集线器的写旁路电路包括:
复用器,其具有耦合到所述数据路径的第一输入端并且还具有第二输入端、输出端和选择端子,所述复用器根据被施加到所述选择端子的选择信号将所述输出端耦合到所述第一或第二输入端;
先入先出(FIFO)寄存器,其具有耦合到所述数据路径的输入端并且还具有耦合到所述复用器的第二输入端的输出端;
输出缓存器,其具有耦合到所述复用器的输出端的缓存器输入端并且还具有缓存器输出端和激活端子,所述输出缓存器根据被施加到所述激活端子的激活信号将所述缓存器输入端耦合到所述缓存器输出端;以及
选择电路,在被激活时,其耦合到所述复用器来产生所述选择信号和激活信号,以便将所述复用器的第二输入端耦合到所述复用器的输出端。
12、如权利要求11所述的基于处理器的系统,其中,所述存储器集线器的写旁路电路还包括输入缓存器,所述输入缓存器具有耦合到所述数据路径的输入端和耦合到所述复用器和所述FIFO寄存器的输入端的输出端。
13、如权利要求10所述的基于处理器的系统,其中,所述存储器集线器还包括存储器设备接口,所述存储器设备接口耦合到所述数据路径并且耦合到所述多个存储器设备中的至少一个,所述存储器设备接口用于将数据耦合到所述存储器设备。
14、如权利要求13所述的基于处理器的系统,其中,所述存储器集线器的存储器设备接口包括:
存储器控制器,其通过存储器控制器总线耦合到所述数据路径,并且还通过存储器设备总线耦合到所述多个存储器设备中的至少一个;
写缓存器,其耦合到所述存储器控制器,以用于存储被导引到与所述存储器控制器耦合的所述存储器设备的存储器请求;和
高速缓存存储器,其耦合到所述存储器控制器,以用于存储被提供给所述存储器设备或者从所述存储器设备取回的数据。
15、一种用于将数据写入存储器系统中的存储器单元的方法,所述存储器系统包括与双向存储器总线耦合的多个存储器模块,所述方法包括:
向所述存储器系统发出读命令;
在发出所述读命令之后并且在所述读命令完成之前,在所述双向存储器总线上向所述存储器系统提供写命令和相应的写数据;
将所述写数据耦合到所述存储器系统中的寄存器以用于临时存储所述写数据,以便在所述写数据被提供到所述双向存储器总线之后并且在所述写数据被写入之前,允许读数据在所述双向存储器总线上返回;
将所述读数据耦合到所述双向存储器总线并且提供所述读数据以用于读取;
将所述寄存器中存储的所述写数据耦合到所述双向存储器总线;并且
将所述写数据写入所述存储器单元。
16、如权利要求15所述的方法,其中,向所述存储器系统提供所述写数据包括在将所述写数据耦合到所述寄存器之前通过所述存储器系统的至少一个存储器模块来提供所述写数据。
17、如权利要求15所述的方法,其中,所述多个存储器模块在所述双向存储器总线中被串行耦合,并且其中向所述存储器单元写入所述写数据的步骤包括向位于第一存储器模块中的存储器单元写入所述写数据,其中该第一存储器模块位于从中访问所述读数据的第二存储器模块的下游。
18、一种用于在存储器系统中执行存储器命令的方法,所述存储器系统包括耦合到双向存储器总线的多个存储器模块,所述方法包括:
向所述存储器系统发出读命令;
在所述读命令完成之前,向所述存储器系统中的存储器单元发出写命令并且向所述存储器系统的双向存储器总线提供写数据;
访问所述存储器系统中的读数据;
在所述存储器系统中,旁路电路从所述双向存储器总线临时捕获所述写数据;
在所述双向存储器总线上从所述存储器系统接收所述读数据;
将所述写数据释放到所述双向存储器总线;和
恢复到所述存储器单元的所述写命令。
19、如权利要求18所述的方法,还包括在接收所述读数据的过程中将所述写数据临时存储在旁路缓存器中。
20、如权利要求18所述的方法,其中,向所述存储器总线提供所述写数据包括:在将所述写数据从所述存储器总线临时捕获之前,通过所述存储器系统的至少一个存储器模块来提供所述写数据。
21、一种用于在存储器系统中执行读命令和写命令的方法,所述存储器系统包括耦合到双向存储器总线的多个存储器模块,所述方法包括:
发出读命令来访问所述存储器系统中的第一存储器单元;
在所述读命令完成之前,调度写命令来向所述存储器系统中的第二存储器单元写入数据;
从所述第一存储器单元取回读数据;
向所述存储器系统的双向存储器总线提供与所述写命令相对应的写数据;
在所述存储器系统中,旁路电路在所述双向存储器总线上临时捕获所述写数据;
在所述双向存储器总线上从所述存储器系统接收所述读数据;并且
向所述双向存储器总线释放所述写数据。
22、如权利要求21所述的方法,其中,在所述双向存储器总线上临时捕获所述写数据包括:在一段时间内将所述写数据从所述存储器总线临时捕获,以避免在所述双向存储器总线上发生数据冲突。
23、如权利要求22所述的方法,还包括在接收所述读数据的过程中将所述写数据临时存储在旁路缓存器中。
24、如权利要求22所述的方法,其中,向所述存储器总线提供所述写数据包括:在从所述存储器总线临时捕获所述写数据之前,通过所述存储器系统的至少一个存储器模块来提供所述写数据。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108631130A (zh) * | 2017-03-17 | 2018-10-09 | 新唐科技股份有限公司 | 集线器 |
CN108631130B (zh) * | 2017-03-17 | 2019-11-01 | 新唐科技股份有限公司 | 集线器 |
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US20050177695A1 (en) | 2005-08-11 |
EP2565794B1 (en) | 2014-07-16 |
KR100855193B1 (ko) | 2008-09-01 |
KR20060132925A (ko) | 2006-12-22 |
JP4568290B2 (ja) | 2010-10-27 |
EP1725936B1 (en) | 2014-12-31 |
CN101084489A (zh) | 2007-12-05 |
TW200606636A (en) | 2006-02-16 |
US8694735B2 (en) | 2014-04-08 |
EP2565794A3 (en) | 2013-03-13 |
JP2007520826A (ja) | 2007-07-26 |
EP1725936A4 (en) | 2009-12-02 |
WO2005076816A3 (en) | 2007-03-15 |
US20100287323A1 (en) | 2010-11-11 |
US9164937B2 (en) | 2015-10-20 |
EP1725936A2 (en) | 2006-11-29 |
US20140207993A1 (en) | 2014-07-24 |
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