CN100590733C - Delay locked loop circuit - Google Patents

Delay locked loop circuit Download PDF

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Publication number
CN100590733C
CN100590733C CN200610128064A CN200610128064A CN100590733C CN 100590733 C CN100590733 C CN 100590733C CN 200610128064 A CN200610128064 A CN 200610128064A CN 200610128064 A CN200610128064 A CN 200610128064A CN 100590733 C CN100590733 C CN 100590733C
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clock
delay
phase
output
locked loop
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CN1941171A (en
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金敬勋
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Abstract

A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.

Description

Delay locked loop circuit
Technical field
The present invention relates to a kind of delay locked loop circuit; More particularly, the present invention relates to a kind of storage arrangement that is used for according to the output of the delay locked loop circuit of controlling Synchronous Dynamic Random Access Memory (SDRAM) such as the operating conditions of pressure or temperature.
Background technology
Usually, delay-locked loop (DLL) is to be used for by using outside input clock signal to control from such as the semiconductor memory system of dynamic RAM (DRAM) circuit to the sequential of the output data of external device (ED).Do not have any mistake in order to transfer data to chipset or CPU from semiconductor memory system, the output of this semiconductor memory system is with synchronous from the clock signal that this chipset or this CPU produced.
When the clock signal transferred to the internal control piece transmission of internal control piece in the semiconductor memory system/from semiconductor memory system, this clock signal was owing to clock input buffer device, line load, data output buffer and other piece wherein postpones.Therefore, there is phase differential between the internal clock signal that external timing signal and this semiconductor memory system inside are produced.For synchronous this internal clock signal and this external timing signal, DLL is used to compensate this phase differential.
The clocking error (clock skew) that this DLL compensation is caused by the delay of the internal clocking of home block in the semiconductor memory system, thereby synchronously from the data output timing and the external timing signal of semiconductor memory system.As a result, synchronous via the data output timing and the external timing signal of data output buffer by the nucleus institute sensing of semiconductor memory system according to internal clock signal.
Known DLL circuit can be categorized as analog D LL and digital dll circuit.Digital dll circuit can be various construction, comprises register controlled DLL, mixes DLL, synchronous mirror DLL, estimates control DLL and analog thereof.
Fig. 1 is the calcspar that conventional delay-locked loop is shown.
This routine delay-locked loop comprises clock input buffer device 10 to 20, phase comparator 30, lag line 40, illusory (dummy) lag line 50, delay controller 60, reconstructed model circuit 70, clock cable 80 and output buffer 90.
The clock input buffer device buffering external clock clk and the clkb that comprise rising edge clock buffer 10 and negative edge clock buffer 11 are to produce inner rising clock rclk and inner decline clock fclk.This rising edge clock buffer 10 produces the synchronous inside rising clock rclk of rising edge with the clock clk that is imported, and negative edge clock buffer 11 produces the synchronous inside decline clock fclk of negative edge with the clock clkb that is imported.
This phase comparator 30 relatively should inside rising clock rclk phase place and from the phase place of the feedback clock fbclk of reconstructed model circuit 70 outputs to detect the phase differential between inner rising clock rclk and the feedback clock fbclk.In order to reduce power consumption, phase comparator 30 can replace more inner rising clock rclk and feedback clock fbclk, and relatively produces, has low-frequency through frequency-dividing clock and feedback clock fbclk by the Clock dividers (not shown).According to comparative result, phase comparator 30 produces the output signal that is used for control lag controller 60.This output signal presents one of three kinds of states, that is, and and hysteretic state, leading state and lock-out state.
This delay controller 60 comprises a plurality of shift registers and comes pilot delay line 40 and illusory lag line 50 based on the output signal that is received from phase comparator 30.This lag line 40 postpones this inside rising clock rclk and this inside decline clock fclk under the control of delay controller 60.Similarly, illusory lag line 50 postpones the output clock of this clock input buffer device 20, thereby should be sent in the reconstructed model circuit 70 to produce feedback clock fbclk by delayed clock.The inner structure of illusory lag line 50 is similar to the inner structure of lag line 40, but when importing through frequency-dividing clock, illusory lag line 50 can reduce power consumption.
This reconstructed model circuit 70 is with the output delay scheduled volume of illusory lag line 50, described scheduled volume is estimated by the retardation of modelling clock transmission, externally clock is after the external device (ED) input, and the internal clocking of being changed by external clock is output to external device (ED) in this clock transmission.This clock transmission comprises a plurality of delay units, such as illusory clock buffer, output buffer, Clock dividers etc.These delay units determine that error amount is as the DLL feature.Can be by shrinking, simplify or duplicating a plurality of delay units and come modelling reconstructed model circuit 70.
Clock cable 80 is used to produce drive signal to control this output buffer 90 based on the output signal POUT from lag line 40 outputs as clock driver.Output buffer 90 will synchronously export lead-out terminal to via data and the drive signal that data bus is imported by the nucleus of semiconductor memory system.
Fig. 2 is a schematic circuit of describing lag line 40.
This lag line 40 comprises a plurality of unit delay unit elements (unit delay unit cell) UDC1 to UDC5 and a plurality of NAND (with non-) door ND11 to ND15.Each of these a plurality of unit delay unit elements UDC1 to UDC5 is corresponding to each of a plurality of register signal Reg_n to Reg_0 that export from delay controller 60 and each of a plurality of NAND door ND11 to ND15.
Each of a plurality of NAND door ND11 to ND15 carried out each of a plurality of register signal Reg_n to Reg_0 and the logic NAND computing of one of inner rising clock rclk and inner decline clock fclk.Because this logic NAND computing, reference clock signal, be one of inner rising clock rclk and inner decline clock fclk, input in the unit delay unit elements that receives corresponding register signal that described register signal is one of Reg_n to Reg_0 and has logic high potential.Therefore, postpone to transmit the inside that is formed at lag line 40.
For example each unit delay unit elements of UDC1 includes a NAND door ND1 and the 2nd NAND door ND2.It is the logic NAND computing of the output of ND11 with corresponding NAND door that the one NAND door ND1 carries out supply voltage VDD; And the 2nd NAND door ND2 carries out the logic NAND computing of the output of a supply voltage VDD and a NAND door ND1.Because other unit delay unit elements has same structure, therefore omit its detailed description.
Lag line 40 can comprise two delay line with structure described above at rise clock rclk and inner decline clock fclk of inside.In the case, lag line 40 can be carried out the delay compensation operation to inside rising clock rclk and inner decline clock fclk simultaneously.As a result, maximizing suppresses the duty ratio distortion.
Conventional DLL produces the DLL output clock that only has a phase place, and this DLL output clock is used to control the sequential from the data of semiconductor memory system output, and is used for driving wherein a plurality of control circuits.Yet, if the operation window of DLL output clock reduces under high frequencies of operation or the variation such as the operating conditions of pressure, temperature or input voltage current potential, then when a DLL output clock with a phase place was used to control a plurality of control circuit, the operational reliability of semiconductor memory system descended.
Summary of the invention
An object of the present invention is to provide a kind of semiconductor memory system, its output clock that has a phase place that is different from DLL output clock by use increases the operation window of delay-locked loop.
Another object of the present invention is for providing a kind of semiconductor memory system, and this semiconductor memory system is used to control the output with high-frequency or delay-locked loop (DLL) circuit operated under the situation that the operating conditions such as pressure, temperature or input voltage current potential changes.
According to an aspect of the present invention, provide a kind of delay-locked loop, this delay-locked loop comprises the clock delay compensation block, is used to receive from the clock signal of outside input, thereby produces first clock and second clock for a long time for a long time.The phase control piece is first clock and this second clock for a long time for a long time relatively, to produce the phase control signal of controlling shifting function.Multi-phase delay controll block is carried out shifting function with control clock delay compensation block based on phase control signal, and wherein this clock delay compensation block comprises: clock buffer is used to cushion this clock signal to produce rising clock and decline clock; Phase comparator, being used for relatively should the rising clock, this decline clock and feedback internal clocking, with the output comparative result; Delay controller is used for carrying out shifting function based on this comparative result, to produce the register signal of control phase retardation; The multi-phase delay line, be used for postponing this rising clock and this decline clock to produce this second clock for a long time based on this comparative result, and be used for producing this first clock for a long time in response to delayed control signal from the output of this multi-phase delay controll block, wherein this first for a long time the phase place of clock be different from this second phase place of clock for a long time; Illusory lag line is used to one of output signal that postpones this clock buffer; Reconstructed model is used for output delay with this illusory lag line based on delay unit and modeled scheduled volume, to produce this feedback internal clocking; And output buffer, be used for second clock is synchronous for a long time with this via the data of data bus input, with generation through synchrodata.
Description of drawings
With reference to the description subsequently of the specific embodiment that provides in conjunction with the accompanying drawings, this will be best understood for above-mentioned and other target of the present invention and feature, wherein:
Fig. 1 is the calcspar of conventional delay-locked loop;
Fig. 2 is the schematic circuit of lag line;
Fig. 3 is the calcspar of the delay-locked loop that uses for semiconductor memory system according to an embodiment of the invention;
Fig. 4 is the schematic circuit of the embodiment of the clock buffer shown in Fig. 3;
Fig. 5 is the schematic circuit of the embodiment of the phase comparator shown in Fig. 3;
Fig. 6 is the schematic circuit of the delay controller shown in the depiction 3;
Fig. 7 is the schematic circuit of the multi-phase delay line 140 shown in Fig. 3;
Fig. 8 is the schematic circuit of the multi-phase delay controller 130 shown in Fig. 3;
Fig. 9 is the schematic circuit of the phase controller shown in Fig. 3; And
Figure 10 is the schematic circuit of the delay element shown in Fig. 9.
Embodiment
Hereinafter, will describe according to a particular embodiment of the invention storage arrangement in detail referring to accompanying drawing.
Delay-locked loop (DLL) function of enhancing specifically is provided according to semiconductor memory system of the present invention.
Fig. 3 is the calcspar that the delay-locked loop that uses for semiconductor memory system is shown according to an embodiment of the invention.
This delay-locked loop comprises: clock delay compensation block, phase controller 180 and multi-phase delay controller 130.This clock delay compensation block comprises: clock buffer 100,101 and 110, phase comparator 120, delay controller 160, multi-phase delay line 140, illusory lag line 150, reconstructed model 170 and output buffer 200.
The clock delay compensation block receives from the clock signal clk and the clkb of outside input, to produce first clock MPCLK and the second clock MPOUT for a long time for a long time.By receiving this first clock MPCLK and this second clock MPOUT for a long time for a long time, this phase controller 180 is first clock MPCLK and this second clock MPOUT for a long time for a long time relatively; And the result produces phase control signal sre, src, slo and sle based on the comparison.This phase control signal sre, src, slo and sle are used to control shifting function.Multi-phase delay controller 130 is carried out shifting function based on this phase control signal sre, src, slo and sle, thus control clock delay compensation block.
Clock buffer 100 and 101 receives this clock signal clk and clkb, and cushions this clock signal clk and clkb, to produce rising clock rclk and decline clock fclk.This clock buffer comprises rising edge clock buffer 100 and negative edge clock buffer 101.By receiving this clock signal clk and clkb, rising edge clock buffer 101 produces the synchronous rising clock rclk of rising edge with clock signal clk.Similarly, by receive clock signal clk and have the clock signal clkb opposite with the phase place of clock signal clk, negative edge clock buffer 101 produces the synchronous decline clock fclk of negative edge with clock signal clk.
Phase comparator 120 relatively rise clock rclk, decline clock fclk or both and feedback internal clocking fbclk are to export comparative result in the delay controller 160 to.In another embodiment, phase comparator 120 receive from the output of Clock dividers (not shown) through frequency-dividing clock, and relatively should be through frequency-dividing clock and this feedback internal clocking fbclk, with the minimizing power consumption.Owing to be lower than the frequency of rising clock rclk or decline clock fclk from the frequency through frequency-dividing clock of Clock dividers output, so phase comparator 120 can reduce the power consumption in the compare operation.Represent one of three kinds of states according to comparative result from the output signal that phase comparator 120 exports delay controller 60 to: leading, lag behind or locking.
Based on the comparative result of phase comparator 120, delay controller 160 is carried out shifting function, register signal Reg_n to Reg_0 is exported to multi-phase delay line 140 and illusory lag line 150, with the control phase retardation.Wherein, n is a positive integer.Delay controller 160 comprises a plurality of shift registers, and these a plurality of shift registers can be determined the initial maximum or the minimum phase retardation of multi-phase delay line 140 and illusory lag line 150.
The multi-phase delay controller 130 that comprises a plurality of bidirectional shift registers is according to phase control signal sre, sro, slo and sle from phase controller 180 outputs, with delayed control signal oc＜1:n〉export multi-phase delay line 140 to.Phase control signal comprises even number dextroposition signal sre and odd number dextroposition signal sro, even number signal sle and the odd number signal slo that shifts left that shifts left.
According to delayed control signal oc＜1:n〉and register signal Reg_n to Reg_0, multi-phase delay line 140 postpones the phase place of rising clock rclk and decline clock fclk, to produce first clock MPCLK and the second clock MPOUT for a long time for a long time.First for a long time the phase place of clock MPCLK be different from second phase place of clock MPOUT for a long time.Multi-phase delay line 140 is result's postpone to rise clock and decline clock based on the comparison, producing the second clock MPOUT for a long time, and in response to the delayed control signal oc＜1:n from 130 outputs of multi-phase delay controller〉produce the first clock MPCLK for a long time.
The output signal of clock buffer 110 that is postponed receive clock signal clk by the illusory lag line 150 of delay controller 160 control is to export delayed signal to reconstructed model 170.Reconstructed model 170 with the output delay of illusory lag line 150 based on delay unit and modeled scheduled volume, to produce feedback internal signal fbclk.
Externally in the clock path between clock input and the internal clocking output, except the part of delay-locked loop inside is a multi-phase delay line 140, delay unit also comprises a plurality of unit, with will be synchronous with external timing signal with the second clock MPOUT data in synchronization output for a long time.As a result, the accurate modelization of delay unit determines to be considered the error of the critical nature factor of semiconductor memory system.For accurate modelization, reconstructed model 170 can have contraction, simplifies or duplicate the structure such as the delay unit of clock buffer, Clock dividers, output buffer and analog thereof.
As described above, phase controller 180 according to second for a long time clock MPOUT and first for a long time clock MPCLK produce phase control signal sre, src, slo and the sle of the shifting function be used to control multi-phase delay controller 130.This phase controller 180 can be based on first phase place of adjusting such as the PVT condition of manufacturing process, voltage potential or temperature from multi-phase delay line 140 output of clock MPCLK for a long time.
Clock cable 190 will from multi-phase delay line 140 second for a long time clock MPOUT be sent to output buffer 200.This output buffer 200 receives via data bus institute's data signals transmitted and with this data-signal and this second synchronously outwards output of clock MPOUT for a long time.
Fig. 4 is the schematic circuit of the embodiment of the clock buffer 100 shown in description Fig. 3 or 101.
This clock buffer 100 comprises the differential amplifier with PMOS transistor P1 and P2, nmos pass transistor N1, N2 and N3 and phase inverter IV1.This clock signal clk and clkb input to the input terminal of differential amplifier, i.e. the grid of nmos pass transistor N1 and N2.Enable signal EN inputs to the grid of nmos pass transistor N3 to enable differential amplifier.PMOS transistor P1 and P2 are between nmos pass transistor N1 and N2 and the supply voltage VDD.Anti-phase and be produced as rising clock rclk in the output signal of the differential amplifier of drain electrode place of nmos pass transistor N2 output by phase inverter IV1.
Clock buffer 101 and 110 has similar structures.Compare with clock buffer 100, in clock buffer 101, clock signal clk and clkb input to the input terminal of differential amplifier with reversed sequence, to produce decline clock fclk.
Fig. 5 is the schematic circuit of the embodiment of the phase comparator 120 shown in Fig. 3.
Phase comparator 120 comprises phase comparison unit 121 and shift register controller 125.This phase comparison unit 121 comprises a plurality of delay element DC1 to DC3, a plurality of logic NAND door ND16 to ND44, a plurality of phase inverter IV2 to IV7, logic OR (or) door OR1, logic NOR (or non-) door NOR1 and logic AND (with) door AND1.For example the delay element of DC1 is with rising clock rclk and decline clock fclk delay scheduled time.
Phase comparison unit 121 relatively feeds back internal signal fbclk, rising clock rclk or decline clock fclk, and the second clock MPOUT for a long time, and based on the comparison the result export indication leading, lag behind, the information of locking.Determine dextroposition operation and by comparison signal PC2 and the PC4 operation of determining to shift left by comparison signal PC1 and PC3.Carry out the dextroposition operation and the retardation of operation of shifting left with control multi-phase delay line 140 and illusory lag line 150.
In phase comparison unit 121, delay element DC1 to DC3 will feed back internal signal and the rising clock or the decline clock delay schedule time.The logical block that is configured to a plurality of logic NAND doors and a plurality of phase inverters relatively feeds back internal signal fbclk, rising clock rclk or decline clock fclk and from delayed feedback internal signal and the delayed rising clock or the decline clock of delay element DC1 to DC3 output, with the output comparative result.In order to shorten the lock operation time, when having big phase differential between rising clock rclk or decline clock fclk and the feedback internal signal fbclk, postpone the aero mode control module and receive the second clock MPOUT and relatively from the comparative result AC and second of logical block output clock MPOUT for a long time, to enable to postpone aero mode for a long time.
This phase comparison unit 121 determines whether to carry out shifting function based on second comparative result of clock MPOUT or rising clock rclk or decline clock fclk and feedback internal signal fbclk for a long time.For example, if use frequency divider, then by using eight unit delay parts to come phase place between two clocks of comparison with 1/8 ratio.According to being used for the right side or the comparative result of the operation of shifting left uses through frequency-dividing clock or without frequency-dividing clock.
In response to three kinds of states from phase comparison unit 121 outputs, shift register controller 125 produces the various combination of comparison of signal phase SR1, SR2, SL1 and SL2.If the information representation lock-out state does not then start phase control signal.
Fig. 6 is the schematic circuit of the delay controller 160 shown in Fig. 3.
The delay controller 160 that is disposed in a plurality of levels comprises a plurality of logic NOR door NOR2 to NOR7, a plurality of logic NAND door ND57 to ND62, a plurality of logic nmos pass transistor N4 to N27, reaches a plurality of phase inverter IV11 to IV16.
For example each level of the level of output register signal Reg_1 includes anti-phase latch, switch unit and logical block.This switch unit comprises four NMOS transistors, and for example N8 to N11 shifts left or the dextroposition operation to control in response to a plurality of comparison of signal phase SR1, SR2, SL1 and SL2.Anti-phase latch comprises the logic NAND door of ND58 for example and the phase inverter of IV12 for example, to latch the output of switch unit.For example the logical block of NOR3 receives the output and the actuating logic computing of first prime and next stage, and then produces for example register signal of Reg_1.
A plurality of grades logical block is carried out shifting function and is produced register signal Reg_n-1 to Reg_0 in response to a plurality of comparison of signal phase SR1, SR2, SL1 and SL2.According to starting condition, delay controller 160 can be determined the minimum or the maximum-delay amount of multi-phase delay line 140 and illusory lag line 150.Moreover, in order to carry out appropriate shifting function, for example avoid displacement failure (shifting collapse), delay controller 160 prevents the crossover of a plurality of comparison of signal phase SR1, SR2, SL1 and SL2.
Fig. 7 is the schematic circuit of the multi-phase delay line 140 shown in Fig. 3.
This multi-phase delay line 140 comprises the first logical combination unit 141, a plurality of delay cell element UDC6 to UDC10 and o controller 142.
The first logical combination unit 141 comprises a plurality of NAND doors to carry out the logical operation of rising clock rclk or decline clock fclk and register signal Reg_n-1 to Reg_0, the result is exported in each delay cell element.Therefore, form delay path by the delay cell element that receives register signal among a plurality of delay cell element UDC6 to UDC10 with logic high potential.Each of a plurality of delay cell element UDC6 to UDc10 is corresponding to each of register signal Reg_n-1 to Reg_0.
The a plurality of delay cell element UDC6 to UDC10 that comprise a plurality of logic NAND door ND63 to ND72 control second retardation of clock MPOUT for a long time based on the output of the first logical combination unit 141.For example, delay cell element UDC6 comprises two logic NAND door ND63 and ND64.This logic NAND door ND63 receives the output of supply voltage VDD and logic NAND door 73, and produces to the output of the logic NAND computing of logic NAND door ND64; And similarly, logic NAND door ND65 carries out the logic NAND computing of the output of supply voltage VDD and logic NAND door 63, and exports the result to o controller 142 and next delay cell element UDC7.The most last delay cell element UDC10 with second for a long time clock MPOUT export clock cable 190 to.Delay cell element UDC 7 to 10 has similar structures, and therefore, no longer describes in further detail.
O controller 142 comprises a plurality of transmission gate T1 to Tn and a plurality of phase inverter IV17 to IV20.In response to delayed control signal oc＜n:1〉and each of a plurality of transmission gates of selectivity conducting, with a plurality of signals that will produce from a plurality of delay cell element UDc6 to UDc10 as the first clock MPCLK output for a long time.Wherein, n is a positive integer.
Fig. 8 is the schematic circuit of the multi-phase delay controller 130 shown in Fig. 3.
This multi-phase delay controller 130 with a plurality of grades comprises a plurality of logic NOR door NOR8 to NOR12, a plurality of logic NAND door ND78 to ND83, a plurality of nmos pass transistor N28 to N51 and a plurality of phase inverter IV21 to IV26.Each level of multi-phase delay controller 130 includes anti-phase latch L, switch unit S and the second logical block C.
At output delay control signal oc[n-1] the level in, anti-phase latch L has logic NAND door 79 and phase inverter IV22.For initialization, reset signal is inputed to this logic NAND door 79.This switch unit S is in response to the phase control signal sre, the sro that export from phase controller 180, slo, sle and control the logical value that is latched the anti-phase latch L.The second logical block C of each grade receives the output and the actuating logic computing of each second logical block in first prime and the next stage, and then produces delayed control signal oc[n-1].
In switch unit S, nmos pass transistor N32 is by even number dextroposition signal sre control, and the nmos pass transistor N33 that is controlled by the anti-phase latch of first prime is used for by nmos pass transistor N32 ground voltage being conducted to anti-phase latch L.Similarly, the nmos pass transistor controlled of the nmos pass transistor N34 of odd number dextroposition signal sro control and anti-phase latch that next is previous is used for ground voltage is conducted to this anti-phase latch L.
Referring to Fig. 8, the switch unit S of each grade is by the various combination of phase control signal sre, sro, slo, sle: for example sre and sle, sre and slo, sro and sle etc., control.Wherein, according to starting condition, multi-phase delay controller 130 can be determined the minimum or the maximum-delay amount of multi-phase delay line 140 and illusory lag line 150.Moreover, in order to carry out appropriate shifting function, for example, avoid the displacement failure, delay controller 160 prevents that two logic high state signal crossovers from appearring in phase control signal sre, sro, slo, sle.
Fig. 9 is the schematic circuit of the phase controller 180 shown in Fig. 3.
This phase controller 180 comprises phase place comparison block 181, trigger-blocks 183 and the 3rd logical block 184.
The phase place comparison block 181 that comprises delay element 182, a plurality of logic NAND door ND84 to ND90 and a plurality of phase inverter IV27 and IV28 is first clock MPCLK and the second clock MPOUT for a long time for a long time relatively.Phase place comparison block 181 exports this comparative result to the 3rd logical block 184.
The trigger-blocks 183 that comprises a plurality of logic NAND doors and a plurality of phase inverter IV29 to IV31 receives the first clock MPCLK and export the clock for a long time through triggering to the 3rd logical block 184 for a long time.
Reception is from the comparative result of phase place comparison block 181 outputs and the clock for a long time through triggering of slave flipflop piece 183 outputs, and the 3rd logical block 184 is carried out the Different Logic combination to produce phase control signal sre, sro, slo, sle.
Figure 10 is the schematic circuit of the delay element 182 shown in Fig. 9.
Delay element 182 comprises the RC delay element with a plurality of phase inverter IV32 and IV33, register R and capacitor C.This delay element 182 based on register R and capacitor C with the second clock MPOUT delay scheduled time for a long time.
Operation is described below.Phase controller 180 is first phase place and second phase place of clock MPOUT for a long time of clock MPCLK for a long time relatively, produces the various combination of phase control signal sre, sro, slo and sle with result based on the comparison.Phase controller 180 has the predetermined amount of delay that is set by mode register set (MRS) or safety cut out.
As described previously, even number dextroposition signal sre and odd number dextroposition signal sro are used for the dextroposition operation,, increase the retardation of multi-phase delay line 140 and illusory lag line 150 that is.Even number signal sle and the odd number signal slo operation that is used to shift left of shifting left of shifting left promptly, reduces the retardation of multi-phase delay line 140 and illusory lag line 150.These signals are that each of phase control signal sre, sro, slo and sle alternately produces with pulse shape.
Phase controller 180 detects first clock MPCLK and second phase differential between the clock MPOUT for a long time for a long time, and export phase control signal sre, sro, slo and sle to multi-phase delay controller 130, to control first clock MPCLK and second retardation of clock MPOUT for a long time for a long time.
In response to phase control signal sre, sro, slo and sle, multi-phase delay controller 130 control shifting functions and with this delayed control signal oc＜1:n export multi-phase delay line 140 to.
According to delayed control signal oc＜1:n 〉, one of a plurality of transmission gate T1 to Tn in the multi-phase delay line 140 are switched on.Therefore, multi-phase delay line 140 produces the first clock MPCLK for a long time, and it has than second phase place that more shifts to an earlier date of clock MPOUT for a long time from delay cell element UDC10 output.At this moment,, delayed control signal oc＜1 when input during initial operation during reset signal〉become logic high potential, and in response to phase control signal sle and slo, first for a long time the phase place of clock MPCLK be ahead of second phase place of clock MPOUT for a long time.
Multi-phase delay line 140 can be controlled according to the condition that comprises pressure, voltage potential, temperature and similar terms according to an embodiment of the invention.The a plurality of delayed control signals of multi-phase delay line options according to another embodiment of the present invention are oc＜1:n for example〉one and via backfeed loop it is exported such as phase controller, that is, be used to reflect that the backfeed loop of the comparative result of exporting MPCLK and MPOUT is eliminated.Can select one of a plurality of delayed control signals by mode register set MRS and fuse.In addition, by using mode register set MRS and fuse, the retardation of the backfeed loop that is embodied in the adjustable delay locked loop.
Though according to the embodiments of the invention shown in Fig. 3, only from phase information of multi-phase delay line 140 extra outputs, but according to another embodiment of the present invention,, can produce at least one phase information by using a plurality of outputs of the transmission gate T1 to T5 in the multi-phase delay line.
As described above, has heterogeneous clock signal by use, can be according to semiconductor memory system of the present invention according to high-frequency operation or such as the variation of the operating conditions of pressure, temperature or institute's input voltage current potential, come the output of control lag locked loop (DLL) circuit, and the operation window of the delay-locked loop in the improvement semiconductor memory system.
The application contains and korean patent application KR 2005-0090951 and KR 2005-0117134 number relevant theme of submitting in Korean Patent office on September 29th, 2005 and on Dec 2nd, 2005 respectively, and its full content is contained in this as quoting.
Though described the present invention with reference to certain specific embodiments, it will be apparent to one skilled in the art that and to make various variations and modification not departing under the spirit of the present invention and category situation that limits as claim.

Claims (18)

1. delay-locked loop comprises:
The clock delay compensation block is used to receive from the clock signal of outside input, to produce first clock and second clock for a long time for a long time;
The phase control piece is used for relatively this first clock and this second clock for a long time for a long time, to produce the phase control signal of control shifting function; And
Multi-phase delay controll block is used for carrying out this shifting function based on this phase control signal, controlling this clock delay compensation block,
Wherein this clock delay compensation block comprises:
Clock buffer is used to cushion this clock signal to produce rising clock and decline clock;
Phase comparator, being used for relatively should the rising clock, this decline clock and feedback internal clocking, with the output comparative result;
Delay controller is used for carrying out shifting function based on this comparative result, to produce the register signal of control phase retardation;
The multi-phase delay line, be used for postponing this rising clock and this decline clock to produce this second clock for a long time based on this comparative result, and be used for producing this first clock for a long time in response to delayed control signal from the output of this multi-phase delay controll block, wherein this first for a long time the phase place of clock be different from this second phase place of clock for a long time;
Illusory lag line is used to one of output signal that postpones this clock buffer;
Reconstructed model is used for output delay with this illusory lag line based on delay unit and modeled scheduled volume, to produce this feedback internal clocking; And
Output buffer is used for second clock is synchronous for a long time with this via the data of data bus input, with generation through synchrodata.
2. delay-locked loop as claimed in claim 1, wherein this multi-phase delay line comprises:
The first logical combination unit, being used to produce this rising clock maybe should the decline clock and the logical operation of this register signal;
A plurality of delay cell elements are used for the output based on this first logical combination unit, control this second retardation of clock for a long time; And
O controller, the conducting in response to this delayed control signal, with a plurality of signals that a plurality of delay cell elements place is provided as this first clock output for a long time.
3. delay-locked loop as claimed in claim 2, wherein this first logical combination unit comprises a plurality of logic NAND doors that are used for actuating logic NAND computing.
4. delay-locked loop as claimed in claim 2, wherein when this register signal is in logic high potential, these a plurality of delay cell elements form the delay path of the reference clock signal that inputs to the predetermined delay unit elements based on this output of this first logical combination unit.
5. delay-locked loop as claimed in claim 2, wherein this o controller comprises a plurality of transmission gates, each of these a plurality of transmission gates is coupled between each delay cell element and each lead-out terminal and based on this delayed control signal and conducting.
6. delay-locked loop as claimed in claim 5, wherein, in scheduled operating time, one of these a plurality of transmission gates be cut off and these a plurality of transmission gates in other transmission gate be switched on.
7. delay-locked loop as claimed in claim 6, wherein the number of this transmission gate is determined by mode register set (MRS).
8. delay-locked loop as claimed in claim 6, wherein the number of conducting transmission gate is determined by safety cut out.
9. delay-locked loop as claimed in claim 1, wherein this multi-phase delay controll block also comprises at least one bidirectional shift register.
10. delay-locked loop as claimed in claim 9, wherein this multi-phase delay controll block comprises:
Switch unit is used for controlling in response to this phase control signal and shifts left or the dextroposition operation;
Latch units is used to latch the output of this switch unit; And
The second logical combination unit is used to carry out the logical operation of the output of this switch unit, to produce this delayed control signal.
11. delay-locked loop as claimed in claim 1, wherein this phase control piece comprises:
Phase comparison unit is used for relatively this first clock and this second clock for a long time for a long time;
First flip-flop element is used to carry out this first trigger action of clock for a long time; And
The 3rd logical combination unit is used to carry out the logical operation of the output of the output of this phase comparison unit and this first flip-flop element, to produce this phase control signal.
12. as the delay-locked loop of claim 11, wherein this phase comparison unit comprises:
Delay element, being used for maybe should the decline clock delay schedule time with this feedback internal clocking and this rising clock;
Logical block, being used for relatively this feedback internal clocking, this rising clock maybe should the decline clock, with delayed feedback internal clocking and delayed rising clock or delayed decline clock from this delay element output, with the output comparative result; And
Postpone the aero mode control module, be used for based on this comparative result and this second for a long time clock enable to postpone aero mode.
13. as the delay-locked loop of claim 12, wherein the retardation of this delay element is determined by mode register set (MRS).
14. as the delay-locked loop of claim 12, wherein the retardation of this delay element is determined by safety cut out.
15. as the delay-locked loop of claim 12, wherein this delay element comprises the RC delay unit.
16. as the delay-locked loop of claim 11, wherein this first flip-flop element comprises the T trigger.
17. as the delay-locked loop of claim 11, wherein the 3rd logical combination unit comprises a plurality of logic NAND doors, these a plurality of logic NAND doors are used to carry out the logic NAND computing of the output of the output of this phase comparison unit and this first flip-flop element.
18. as the delay-locked loop of claim 11, wherein this phase control signal comprises even number dextroposition signal, odd number dextroposition signal, even number signal and the odd number signal that shifts left that shifts left.
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