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Numéro de publicationCN100592521 C
Type de publicationOctroi
Numéro de demandeCN 200510103417
Date de publication24 févr. 2010
Date de dépôt15 sept. 2005
Date de priorité15 sept. 2005
Autre référence de publicationCN1933159A
Numéro de publication200510103417.1, CN 100592521 C, CN 100592521C, CN 200510103417, CN-C-100592521, CN100592521 C, CN100592521C, CN200510103417, CN200510103417.1
Inventeurs何家骅, 赖二琨
Déposant旺宏电子股份有限公司
Exporter la citationBiBTeX, EndNote, RefMan
Liens externes:  SIPO, Espacenet
Fast flash memory element and producing method thereof
CN 100592521 C
Résumé
This invention relates to a quick flash memory body including a first source/drain region and a second source/drain region in the base, a first floating grating at the base between the two regions andadjacent to the first region, a second floating grating on the base between the two regions and adjacent to the second region, a light doped area in the base between the two floating gratings and a control grating covering the two gratings, in which, the first floating grating is separated from the second. This memory body can increase the memory density and reduce cost.
Revendications(17)  Langue du texte original : Chinois
1、一种快闪存储元件,包含多个单位存储单元,适用于一基底,每一该单位存储单元包括: 一第一源极/漏极区及一第二源极/漏极区,位于该基底中; 一第一浮置栅极,位于该第一源极/漏极区以及该第二源极/漏极区间的该基底上,且该第一浮置栅极邻接在该第一源极/漏极区; 一第二浮置栅极,位于该第一源极/漏极区以及该第二源极/漏极区间的该基底上,且该第二浮置栅极邻接在该第二源极/漏极区; 一淡掺杂区,位于该第一浮置栅极及该第二浮置栅极的二相对侧壁间的该基底中;以及一控制栅极,覆盖在该第一浮置栅极及该第二浮置栅极上。 A flash memory device comprising a plurality of unit memory cell, is suitable for a substrate, each of the unit memory cell comprising: a first source / drain region and a second source / drain region is located The substrate; on a first floating gate, located at the first source / drain region and the second source / drain interval of the substrate, and the first floating gate adjacent to the first source / drain regions; a second floating gate, located at the first source / drain regions and on the second source / drain interval of the substrate, and the second floating gate adjacent to the The second source / drain region; a light doped region, the second substrate located opposite the first side wall and the second floating gate between the floating gate; and a control gate, cover In the first floating gate and the second floating gate.
2、 根据权利要求1所述的快闪存储元件,其中该第一源极/漏极区及该第二源极/漏极区具有与该淡掺杂区相同的导电类型。 2. The flash memory device according to claim 1, wherein the first source / drain region and the second source / drain region, and the light doped region having the same conductivity type.
3、 根据权利要求1所述的快闪存储元件,其中该淡掺杂区的掺杂离子浓度小于该第一源极/漏极区与该第二源极/漏极区的掺杂离子浓度。 3, the flash memory device according to claim 1 or claim 2, wherein the light-doped region is less than the doping concentration of the dopant ion concentration first source / drain region and the second source / drain regions .
4、 根据权利要求1所述的快闪存储元件,其中该第一浮置栅极与该第二浮置栅极以一介电层隔离。 4, the flash memory device according to one of the preceding claims, wherein the first and the second floating gate to floating gate dielectric layer isolated.
5 、根据权利要求1所述的快闪存储元件,更包括多个口袋型注入掺杂区,位于该第一源极/漏极区及该第二源极/漏极区间的该基底中,而且分别邻接在该第一源极/漏极区及该第二源极/漏极区。 5. The flash memory device according to claim 1, further comprising a plurality of pocket implantation doped regions, located within the first source / drain region and the second source / drain section of the substrate, and respectively adjacent to the first source / drain region and the second source / drain region.
6、 根据权利要求1所述的快闪存储元件,其中该第一浮置栅极及该第二浮置栅极以一隧穿介电层与该基底隔离。 6. The flash memory device according to claim 1, wherein the first floating gate and the second floating gate with a tunneling dielectric layer is isolated from the substrate.
7、 根据权利要求1所述的快闪存储元件,其中该第一浮置栅极以及该第二浮置栅极以具有大于4的介电常数的一介电层与该控制栅极隔离。 7. The flash memory device according to claim 1, wherein the first and the second floating gate to floating gate 4 having a dielectric constant greater than the dielectric layer and the control gate isolation.
8、 一种快闪存储元件的制造方法,包括: 在基底上形成导体层,在该导体层中形成多个第一开口; 在每一个该第一开口下的该基底中形成一源极/漏极区; 形成多个介电插塞,以分别填满该第一开口,该些介电插塞高于该导体层;在该导体层以及各该介电插塞的侧壁上形成一多层间隙壁,其中该多层间隙壁暴露部分的该导体层;在该导体层中形成一第二开口,使该导体层分开而形成一第一浮置栅极以及一第二浮置栅极;在该第二开口下的该基底中形成一自行对准淡掺杂区;形成一第一介电层以填满该第二开口;暴露该第一浮置栅极以及该第二浮置栅极;以及在该基底上形成一控制栅极,该控制栅极覆盖该基底。 8. A method of manufacturing a flash memory element, comprising: forming a conductive layer on a substrate, forming a plurality of openings in the first conductive layer; in each of the first opening in the substrate to form a source / a drain region; forming a plurality of dielectric plug to fill the first opening, respectively, which is higher than those of the dielectric plug conductive layer; forming a conductive layer on the sidewalls of the dielectric and in each of the plug Multilayer spacer, wherein the spacer of the multi-conductor layer exposed portion; a second opening formed in the conductor layer, so that the conductor layer is formed separately from a first floating gate and a second floating gate pole; in the second opening in the substrate to form a self-aligned light doped region; forming a first dielectric layer to fill the second opening; expose the first floating gate and the second floating gate; and a control gate is formed on the substrate, the control gate overlying the substrate.
9、 根据权利要求8所述的快闪存储元件制造方法,其中该淡掺杂区的掺杂离子浓度小于该些源极/漏极区的掺杂离子浓度。 9. The flash memory device manufacturing method according to claim 8, wherein the light doping concentration of the doped region is less than the dopant ion concentration of source / drain regions.
10、 根据权利要求8所述的快闪存储元件的制造方法,其中形成该多层间隙壁的步骤包括:在该基底上形成一共形的介电层,该共形的介电层覆盖该基底; 在该共形的介电层上形成一第二介电层;以及进行一蚀刻工艺,以移除部分该第二介电层以及部分该共形的介电层, 直到暴露该导体层的一部分。 Step 10, according to the manufacturing method of a flash memory device according to claim 8, wherein the spacer is formed of the multilayer comprising: forming a conformal dielectric layer on the substrate, the conformal dielectric layer overlying the substrate ; formed on the conformal dielectric layer a second dielectric layer; and performing an etching process to remove portions of the dielectric layer and the second portion of the conformal dielectric layer until exposing the conductive layer part.
11、 根据权利要求10所述的快闪存储元件的制造方法,其中更包括: 以该第一浮置栅极以及该第二浮置栅极的顶表面的部分该共形的介电层为终止层,进行一平坦化工艺;以及移除其他的该共形的介电层,直到暴露该第一浮置栅极以及该第二浮置栅极的顶表面。 11. The method of manufacturing a flash memory device as claimed in claim 10 wherein, wherein further comprising: a first floating gate and the dielectric layer on the top surface of the second floating gate portion of the conformal stop layer, conducted a planarization process; and removing the other conformal dielectric layer until exposing the first floating gate and the top surface of the second floating gate.
12、 根据权利要求11所述的快闪存储元件的制造方法,其中移除其他的该共形的介电层的步骤是以进行一化学机械研磨工艺、 一湿式蚀刻工艺或一干式蚀刻工艺来达成。 12. The method of manufacturing a flash memory device according to claim 11, wherein the step of removing the other conformal dielectric layer is carried out a chemical mechanical polishing process, a wet etching process or a dry etching process to achieve.
13、 根据权利要求10所述的快闪存储元件的制造方法,其中该共形的介电层对该第二介电层的研磨选择比是500。 13. The method of manufacturing a flash memory device as claimed in claim 10 wherein, wherein grinding the conformal dielectric layer of the second dielectric layer 500 selectivity.
14、 根据权利要求10所述的快闪存储元件的制造方法,其中该共形的介电层是由氮化硅制成。 14. The method of manufacturing a flash memory device according to claim 10, wherein the conformal dielectric layer is made of silicon nitride.
15、 根据权利要求10所述的快闪存储元件的制造方法,其中该第二介电层是由氮氧化硅制成。 15. The method of manufacturing a flash memory device as claimed in claim 10 wherein, wherein the second dielectric layer is made of silicon oxynitride.
16、 根据权利要求10所述的快闪存储元件的制造方法,其中该第二介电层是由与构成该介电插塞以及该第一介电层相同的材料制成。 16. The method of manufacturing a flash memory device according to claim 10, wherein the second dielectric layer is made of a dielectric constituting the plug and the first dielectric layer of the same material.
17、 根据权利要求8所述的快闪存储元件的制造方法,其中形成该自行对准淡掺杂区的步骤可以利用约每立方厘米10"个离子的浓度以及约10keV 的注入能量的注入离子来达成。 17. The method of manufacturing a flash memory device according to claim 8, wherein the step of self-aligned light doped regions can be formed about 10 "as well as the concentration of ions per cubic centimeter to about 10keV implantation energy of ion implantation to achieve.
Description  Langue du texte original : Chinois

快闪存储元件与其制造方法 Flash memory device and its manufacturing method

技术领域 Technical Field

本发明是有关于一种半导体元件与其制造方法,且特别是有关于一种快闪存储元件与其制造方法。 The present invention relates to a semiconductor device and its manufacturing method, and in particular relates to a flash memory device and its manufacturing method.

背景技术 Background

存储元件,顾名思义,是一种用来储存资料或资讯的半导体元件。 Storage element, by definition, is a semiconductor device used to store data or information. 当电脑的微处理器变得功能更强大,软件的程序与计算变得更复杂,存储元件的容量需求也随之增加。 When the microprocessor computers become more powerful, procedures and calculation software becomes more complex, demand for storage capacity element is also increased. 为了满足此需求增加的趋势,制造高容量的便宜存储元件的技术与工艺成为制造高积集度元件的趋动力。 In order to meet this increased demand trends, technology and manufacturing technology of high-capacity storage device becomes inexpensive manufacture of highly integrated set of elements driving forces.

在各种存储元件产品中,非挥发性存储元件具有重复储存、读取、或抹除资料,并且在电源中断时不会丧失资料的能力,因此成为在个人电脑或电子设备中广为应用的半导体元件。 In various storage components products, the non-volatile memory storage element has a repeat, read, or erase data, and data will not lose the ability to power interruptions, it became widely used in personal computers or electronic equipment a semiconductor element. 其中,快闪存储元件是拥有快速读写的能力与高存^f诸容量等优点一种非挥发性存储元件。 Among them, the flash memory element is to have fast read and write capabilities and high memory capacity, etc. ^ f such a non-volatile storage element.

快闪存储元件被应用于包括通讯产业、消费电子工业、资料处理产业以及运输产业的多种产业。 Flash memory element is applied to a variety of industries including the communications industry, consumer electronics industry, data processing industry and transport industry. 在愈来愈小的电子设备的高度需求下,如何缩小快闪存储元件的尺寸,并增加存储元件的储存密度,而且降低制造成本成为近来制造技术的主要研究课题。 In high demand increasingly smaller electronic devices, how to reduce the size of the flash memory element, and to increase the storage density of the memory elements, and to reduce the manufacturing cost manufacturing technology has recently become a major research topic.

发明内容 DISCLOSURE

因此,本发明至少有一目的是提供一种快闪存储元件结构,其可以在一 Accordingly, an object of the present invention is to at least provide a flash memory device structure, which may be a

单位快闪存储元件储存至少两个载子(Carrier)。 Unit flash memory element storing at least two carriers (Carrier).

本发明至少有另一目的是提供一种快闪存储元件的制造方法,使用此制造方法,浮置4册极(Floating Gate)可以具有一致的形状,而且可以降低成本。 Another object of the present invention is to at least provide a flash memory device manufacturing method using this manufacturing method, the floating electrode 4 (Floating Gate) may have a uniform shape, and can reduce costs.

现并广泛描述的内容,^i明对一基底提供一种快闪存储元件。 Content now and broadly described herein, ^ i next to a substrate to provide a flash memory device. 此快闪: This flash:

储元件包括第一源极/漏极区、第二源极/漏极区、第一浮置栅极、第二浮置栅极、淡掺杂区以及控制栅极。 Storage element comprises a first source / drain region, the second source / drain region, the first floating gate, a second floating gate, a control gate and a doped region of light. 第一源极/漏极区及第二源极/漏极区位于基底中。 A first source / drain region and a second source / drain region is located in the substrate. 另外,第一浮置栅极位于第一源极/漏极区与第二源极/漏极区间的基底上,并与第一源极/漏极区相邻。 Further, the first floating gate located at the first source / drain region and the second source / drain intervals on the substrate, and adjacent to the first source / drain region. 第二浮置栅极位于第一源极/漏极区与第二源极/漏极区间的基底上,并与第二源极/漏极区相邻。 Located in the second floating gate / drain region and the second source / drain of the first section of the source substrate, and the source / drain region adjacent to the second source. 淡掺杂区位于第一浮置4册极与第二浮置栅极的二相对侧壁间的基底中。 Light doped region is located opposite the second sidewall of the first substrate floating electrode 4 and the second floating gate between the. 此外,控制栅极覆盖于第一浮置栅极及第二浮置栅极上。 In addition, a first control gate overlying the floating gate and the second floating gate.

4在本发明中,源极/漏极区及淡掺杂区具有相同的导电类型。 4 In the present invention, the source / drain region and a light doped regions have the same conductivity type. 淡掺杂区的掺杂离子浓度小于第一源极/漏极区与第二源极/漏极区的掺杂离子浓度。 Light doping concentration than the first doped region of the source / drain region and the second source / drain region doping concentration. 此外,第一浮置栅极与第二浮置栅极以介电层隔离。 In addition, the first and the second floating gate to floating gate dielectric isolation layer. 本发明的快闪存储元件更包括数个口袋型注入掺杂区。 Flash memory device of the present invention further includes a plurality of pocket implantation doping area. 口袋型注入掺杂区位于第一源极/漏极区与第二源极/漏极区间的基底中,并分別与第一源极/漏极区与第二源极/漏极区相邻。 Pocket implanted doped region located between the first source / drain region and the second source / drain section of the substrate, and with the first source / drain region and the second source / drain region adjacent . 另外,第一浮置栅极与第二浮置栅极以隧穿介电层与基底隔离。 Further, the first and the second floating gate to floating gate tunneling dielectric isolation layer and the substrate. 第一浮置栅极及第二浮置栅极以一层介电层与控制栅极隔离,此介电层的介电常数大于4。 The first and the second floating gate to floating gate dielectric layer and a control gate isolated from the dielectric constant of the dielectric layer is greater than 4.

在本发明中,由于每个单位存储单元均配置有第一浮置栅极以及第二浮置栅极,每个第一浮置栅极以及第二浮置栅极可以储存至少一个载子。 In the present invention, since each unit memory cell are configured with a first floating gate and a second floating gate, the floating gate of each of the first and the second floating gate can store at least one carrier. 因此,对于一个单位存储单元而言,存储密度较高。 Thus, for a unit memory cell, the high storage density.

本发明更提出一种快闪存储元件的制造方法。 The present invention further proposes a method for manufacturing a flash memory device. 此方法包括的步骤有在基底上形成导体层,在该导体层中形成多个第一开口。 This method comprises the step of forming a conductive layer on a substrate, forming a plurality of first openings in the conductor layer. 然后,在每一个第一开口下的基底中形成一源极/漏极区。 Then, forming a source / drain region in each of the substrate under the first opening. 另外,形成数个介电插塞以填满第一开口。 In addition, the formation of a number of dielectric plug to fill the first opening. 介电插塞高于导体层继之,形成多层间隙壁于导体层上以及介电插塞的侧壁,此多层间隙壁暴露部分的导体层。 The dielectric plug is higher than the conductive layer followed by forming a multilayer spacers on sidewalls of the conductive layer and a dielectric plug, this multilayer conductor exposed portion of the spacer layer. 于导体层中形成第二开口, 以导体层分隔成第一浮置栅极以及第二浮置栅极。 A second opening formed in the conductive layer to the conductive layer is divided into a first and a second floating gate floating gate. 形成自行对准淡掺杂区于第二开口下的基底中,然后形成第一介电层以填满第二开口。 Lighter doped region is formed self-aligned to the substrate under the second opening, and then forming a first dielectric layer to fill the second opening. 暴露出第一 Exposing first

浮置栅极与第二浮置栅极的顶表面。 The top surface of the floating gate and the second floating gate. 接着,形成控制栅极于基底上。 Then, the control gate is formed on the substrate.

在本发明中,淡掺杂区的掺杂离子浓度小于源极/漏极区的掺杂离子浓度。 In the present invention, the doping concentration of the doped region is less than the light doping concentration of the source / drain regions. 此外,形成多层间隙壁的步骤包括在基底上形成一层共形的介电层。 In addition, the step of forming the multilayer spacer layer comprises a conformal dielectric layer formed on the substrate. 接着,在共形的介电层上形成一层第二介电层。 Next, on the conformal dielectric layer of a second dielectric layer. 然后,进行蚀刻工艺以移除部分的第二介电层以及部分的共形介电层直到暴露出部分导体层。 Then, an etching process is performed to remove the portion of the second dielectric layer and the conformal dielectric layer to expose a portion until a portion of the conductor layer. 在上述情 In the above situation

形中,更可以进行平坦化工艺,此平坦化工艺是以在第一浮置栅极以及第二浮置栅极顶表面的共形介电层的一部分为终止层。 Shaped, the planarization process may be more, in the planarization process it is part of the first floating gate and a second floating gate top surface of the conformal dielectric layer is terminated. 之后,移除其他的共形介电层直到暴露第一浮置栅极以及第二浮置栅极的顶表面。 After removing the other conformal dielectric layer until exposing the top surface of the first floating gate and a second floating gate. 此外,上述移除 Further, the removal

其他的共形介电层的步骤可利用化学机械研磨(CMP)工艺、湿蚀刻工艺或干蚀刻工艺来完成。 Other steps conformal dielectric layer can be used for chemical mechanical polishing (CMP) process, a wet etching process or a dry etching process to complete. 此外,共形介电层与第二介电层的研磨选择比(Polishing Selective Ratio)大约是500。 In addition, the polishing conformal dielectric layer and second dielectric layer selectivity (Polishing Selective Ratio) is about 500. 共形介电层是以氮化硅制成,第二介电层是以氮氧化硅制成。 Conformal dielectric layer is made of silicon nitride, the second dielectric layer is made of silicon oxynitride. 特别的是,第二介电层的材质与介电插塞以及第一介电层的材质相同。 In particular, the dielectric material and the second dielectric layer of the same material as the electrical plug and the first dielectric layer. 此外,形成自行对准淡掺杂区的步骤可利用离子浓度每立方厘米IO"个离子的注入以及约10keV的注入能量来达成。 In addition, the step of forming self-aligned light-doped region can take advantage of ion concentration per cubic centimeter IO "an ion implantation and implantation energy of about 10keV to reach.

在本发明中,由于导体层被第一介电层分离成第一浮置^fr极以及第二浮置栅极,每个第一浮置栅极以及第二浮置栅极可以储存至少一个载子。 In the present invention, since the conductor layer is separated into a first layer of a first dielectric ^ fr floating electrode and the second floating gate, the floating gate of each of the first and the second floating gate may be storing at least one carrier. 因此,对于一个单位存储单元而言,存储密度增加了。 Thus, for a unit storage unit, the storage density increases. 此外,淡掺杂区是以介电插塞以及多层间隙壁当作罩幕自行对准地形成于基底中,而未另行使用微影工艺。 In addition, light doped region is plug and multilayer dielectric spacer as a mask to form self-aligned in the substrate, without using a separate lithography processes. 因此,成本得以降低。 Therefore, costs can be reduced.

以上的一般叙述以及接下来的细节说明是示范性的,而且是用来提供所主张的本发明内容进一步的说明。 The above general description and the following detailed description are exemplary, and are claimed to provide further explanation of the contents of the present invention.

为让本发明的上述和其他目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合所附图式,作详细说明如下。 To make the above and other objects, features and advantages of the present invention can be more clearly comprehensible, preferred embodiments below, and with the accompanying drawings, described in detail below.

附图说明 Brief Description

为了提供对本发明进一步的了解,附图并入而构成本说明书的一部分。 In order to provide further understanding of the present invention, the drawings are incorporated and constitute part of this specification. 此些附图绘示本发明的实施例,配合说明的内容,以解说本发明的原理。 This drawing painted some embodiments of the present invention is shown, with the contents described to explain the principles of the invention.

图1A至图1H绘示本发明一较佳实施例的快闪存储元件的制造方法剖面图。 1A to 1H illustrates a sectional view of a method of manufacturing a flash memory device of a preferred embodiment of the present invention.

图2绘示本发明另一较佳实施例的快闪存储元件的剖面图。 Figure 2 illustrates the present invention, a flash memory element to another preferred embodiment of a sectional view.

100、 200:基底102、 202:隧穿介电层 100, 200: substrate 102, 202: tunneling dielectric layer

104:导体层104a、 204a:第一浮置栅极 104: conductive layer 104a, 204a: first floating gate

104b、 204b:第二浮置栅极108:硬式罩幕层 104b, 204b: second floating gate 108: hard mask layer

110:第一开口112、 212:源极/漏极区 110: First opening 112, 212: source / drain region

114a、 116a、 116c、 216c:介电插塞 114a, 116a, 116c, 216c: dielectric plug

114b、 116b、 128、 128a、 130、 230:介电层 114b, 116b, 128, 128a, 130, 230: dielectric layer

118: L型间隙壁120:间隙壁 118: L-type spacers 120: spacer

122:多层间隙壁124:第二开口 122: multi-layer spacer 124: a second opening

126、 226:淡掺杂区132、 232:控制栅极 126, 226: light doped regions 132, 232: control gate

240: 口袋型注入^^杂区 240: Pocket injection ^^ miscellaneous area

具体实施方式 DETAILED DESCRIPTION

图1A至图1H绘示本发明一较佳实施例的快闪存储元件的制造方法剖面图。 1A to 1H illustrates a sectional view of a method of manufacturing a flash memory device of a preferred embodiment of the present invention.

请参阅1A所示,提供具有隧穿介电层102的基底100、 一层导体层(图中未示)以及一层硬式罩幕层(图中未示)。 See FIG. 1A, providing a tunneling dielectric layer 102 a substrate 100, a layer of conductive layer (not shown) and a layer of hard mask layer (not shown). 导体层位于隧穿介电层102上,硬式罩幕层位于导体层上。 Conductor layer is located on the tunneling dielectric layer 102, hard mask layer is located on the conductor layer. 隧穿介电层1M例如是以氧化硅、氧化铝、氧化铪、氮化硅或氮氧化硅所制成,但不限上述材料。 1M tunneling dielectric layer is made of e.g. silicon oxide, aluminum oxide, hafnium oxide, silicon nitride or silicon oxynitride, but not limited to the above materials. 隧穿介电层102的形成方法例如是低压化学气相沈积(LPCVD)工艺,但不限于此方法。 Tunneling dielectric layer 102, for example, a method of forming a low pressure chemical vapor deposition (LPCVD) process, but is not limited to this method. 另外,隧穿介电层102的厚度约为5至15纳米。 Further, the thickness of the tunneling dielectric layer 102 is about 5 to 15 nm. 此外,导体层例如是以多晶硅、掺杂多晶硅、 金属硅化物或金属所制成,但不限上述材料。 In addition, the conductive layer is a polysilicon e.g., doped polysilicon, metal silicide, or made of metal, but not limited to the above materials. 导体层的厚度大约是40至100 纳米。 Thickness of the conductor layer is about 40 to 100 nm. 再者,硬式罩幕层例如是以氧化硅或氮化硅制成,硬式罩幕的厚度大 Furthermore, the hard mask layer such as the curtain is made of silicon oxide or silicon nitride, hard mask thickness

6约是5D至200纳米,但硬式罩幕的材质与厚度并不加以限定。 6 5D to about 200 nm, but the material and the thickness of hard mask is not to be limited.

然后,图案化硬式罩幕层以及导体层以形成导体层104与硬式罩幕层108,以及导体层104与硬式罩幕层108之中的第一开口110。 Then, the patterned hard mask layer and the conductive layer to form a conductor layer 104 and the hard mask layer 108, and a conductor layer 104 and the hard mask layer 108 into the first opening 110. 在本实施例中,第一开口110只穿过硬式罩幕层108以及导体层104,并暴露部分的隧穿介电层102。 In the present embodiment, the first opening 110 through the hard mask layer 108 and conductive layer 104, and the exposed portion of the tunnel through the dielectric layer 102. 然而,本实施例所说明的第一开口110结构并不限定本发明的范围。 However, the structure of the first opening 110 of the present embodiment is not limited to the scope described in the present invention. 也就是说,随着制造需求的不同,第一开口110也可以穿过隧穿介电层102以暴露部分的基底100。 That is, with the different manufacturing needs, and to be passed through the first opening 110 tunneling dielectric layer 102 to expose portions of the substrate 100.

请参阅1B所示,在第一开口110下的基底100中分别形成数个源极/ 漏极区112。 See Fig. 1B, the first opening 110 in the substrate 100 are formed a plurality of source / drain regions 112. 源极/漏极区112的形成方法包括进行离子注入以注入浓度每立方厘米1019至102°个离子至基底100中。 The method for forming source / drain regions comprises ion implantation 112 to 1019 per cubic centimeter of implant concentration 至 102 ° ions to the substrate 100. 此外,注入于基底100中的离子例如是砷离子、氮离子或磷离子。 In addition, it injected into the substrate 100 ions such as arsenic ions, nitrogen ions or phosphorus ions.

另外,形成数个介电插塞114a并分别填满第一开口110。 In addition, the formation of a number of dielectric plugs fill the first opening 114a and 110, respectively. 介电插塞114a 的形成方法包括以一层介电材料覆盖基底100,以于硬式罩幕层108上形成介电层114b,并分别于第一开口110中形成介电插塞114a。 The dielectric plug 114a is formed comprising a layer of dielectric material to cover the substrate 100, to form a dielectric layer 114b on the hard mask layer 108, and forming a dielectric plug 114a in the first opening 110. 介电材料例如是氮化硅、氧化硅或具有与硬式罩幕层108不同湿蚀刻行为的介电材料,但不加以限定。 The dielectric material such as silicon nitride, silicon oxide or a dielectric material having 108 different wet etching behavior and hard mask layer, but not be limited. 此外,以介电层114b与介电插塞114a所构成的介电层的厚度约为80至300纳米。 In addition, the dielectric layer 114b and the dielectric thickness of the dielectric layer interposed plug 114a composed of about 80-300 nm.

请参阅1C所示,进行湿式浸泡工艺以移除部分介电层114b以及介电插塞114a,而将介电层114b与介电插塞114a转换成介电层116b与介电插塞116a。 See FIG 1C, were soaking wet process to remove portions of the dielectric layer 114b and a dielectric plug 114a, 114b and the dielectric layer and the dielectric plug 114a is converted into a dielectric layer 116b and the dielectric plug 116a. 因此,介电层116b与介电插塞116a会暴露硬式罩幕层108的顶表面的一部分。 Therefore, the dielectric layer 116b and 116a of the dielectric plug will expose a portion of the top surface of the hard mask layer 108. 当由介电层114b与介电插塞114a所构成的介电层是由氧化硅制成时,湿式浸泡工艺可以利用稀释的氬氟酸或緩冲的氬氟酸来达成,或者,当由介电层114b与介电插塞114a所构成的介电层是由氮^^圭制成时,湿式浸泡工艺可以利用热磷酸来达成。 When plugged by a dielectric layer 114b and the dielectric of the dielectric layer 114a composed of plug it is made of silicon oxide, soaking wet process may use argon diluted hydrofluoric acid or buffered hydrofluoric acid to achieve argon, or when the The dielectric layer 114b and a dielectric layer interposed dielectric plug 114a constituted by nitrogen ^^ Kyu made when soaking wet process phosphoric acid can be used to achieve the heat.

之后,请参阅1D所示,进行剥离工艺以移除硬式罩幕层108以及硬式罩幕层108的上的介电层116b。 After, see FIG 1D, a peeling process to remove the dielectric layer 116b 108 on the hard mask layer 108 and the hard mask layer. 当硬式罩幕层108是由氧化硅制成时,湿式 When the hard mask layer 108 is made of silicon oxide, wet

浸泡工艺可以利用稀释的氢氟酸与緩冲的氢氟酸来达成。 Soaking process may be buffered hydrofluoric acid and hydrofluoric acid diluted to achieve. 或者,当硬式罩幕层108是由氮化硅制成时,湿式浸泡工艺可以利用热磷酸来达成。 Alternatively, when the hard mask layer 108 is made of silicon nitride, soaking wet process phosphoric acid can be used to achieve heat.

另外,在导体层104上以及介电插塞116a的侧壁上形成多层间隙壁122。 In addition, the conductive layer 104, and a multi-layer dielectric insert the plug on the sidewall spacers 122 (116a). 其中多层间隙壁122暴露部分导体层104。 Wherein the multilayer spacer layer 122 exposed portion of the conductor 104. 多层间隙壁122的形成方法包括于基底100上形成一层共形的介电层(图中未示),然后于此共形的介电层上形成一层介电层(图中未示),之后进行蚀刻工艺以移除部分的介电层以及部分的共形介电层,直到暴露部分的导体层104。 Multilayer spacer 122 forming method comprising forming a layer of conformal dielectric layer (not shown) on the substrate 100, a dielectric layer is formed on this layer and then a conformal dielectric layer (not shown in ), followed by an etching process to remove portions of the conformal dielectric layer and the dielectric layer portion, until the exposed portion of the conductive layer 104. 接着,此共形介电层以及此介电层分别被转化为L型间隙壁118以及间隙壁120,而且L型间隙壁118以及间隙壁120共同构成多层间隙壁122。 Subsequently, the conformal dielectric layer and the dielectric layer are respectively converted spacer 118 and the L-shaped spacer 120, and the L-shaped spacer 118 and spacer 120 constitute a multi-layer spacer 122. 另外,共形介电层(即L型间隙壁118)对介电层(即间隙壁120)的研磨选"t奪比大约是500。此外,共形介电层(即L型间隙壁118)例如是由利用化学气相沈积(CVD)工艺与电浆增强化学气相沈积工艺所形成的氮化硅所制成,但是共形介电层的材质与形成方法并不限定。介电层(即间隙壁120)例如是与形成介电插塞116a相同的材质所制成。请参阅1E所示,利用多层间隙壁122以及介电插塞116a为罩幕,进行蚀刻工艺以于导体层104中形成第二开口124而将导体层104分离成为第一浮置栅极104a以及第二浮置对册极104b。在本实施例中,第二开口124仅穿过导体层104 (如图1D所示)并暴露隧穿介电层102的一部分。然而,呈现于本实施例的第二开口124的结构并不限定本发明的范围。也就是说,对于不同的制造需求,第二开口124也可以穿过隧穿介电层102以暴露部分的基底100。另外,在第二开口124下的基底IOO中形成自行对准淡掺杂区126。自行对准淡掺杂区126的形成步骤可以利用离子浓度每立方厘米1018个,注入能量约10keV的注入离子来达成。此外,掺质例如是砷离子、氮离子以及磷离子,但是并不限定。请参阅1F所示,形成一层介电层128以填满第二开口124。介电层128 例如是利用与形成介电插塞116a以及间隙壁120相同的介电材料所制成, 而且介电层128例如是以LPCVD工艺来形成。请参阅1G与图1H所示,进行平坦化工艺直到暴露第一浮置栅极104a以及第二浮置栅极104b。进行此平坦化工艺的方法包括利用第一浮置栅极l(Ma 以及第二浮置栅极104b的顶表面的部分L型间隙壁118 (如图1F所示)为终止层,进行平坦化工艺以移除部分的介电层128以及多层间隙壁122,然后移除其他的L型间隙壁118,直到完全暴露第一浮置栅极104a以及第二浮置栅极104b的顶表面。此外,移除其他的L型间隙壁118的步骤例如是进行化学机如^f磨(CMP)工艺、湿式蚀刻工艺或干式蚀刻工艺来达成,但并不限定。在此平坦化工艺中,在CMP工艺的开始阶段,由于介电层128、间隙壁1M以及介电插塞116a是由相同的材质制成,而且L型间隙壁118的研磨量非常小,研磨率可以维持稳定。然而,当大部分之间隙壁118被移除了,而且L型间隙壁118的研磨量剧烈地减少,由于L型间隙壁118对介电层(即间隙壁以及介电插塞116a)的研磨选择比,CMP工艺会停止。 In addition, the conformal dielectric layer (ie, the L-shaped spacer 118) of the dielectric layer (ie, the spacer 120) abrasive election "t wins than about 500. In addition, the conformal dielectric layer (ie, the L-shaped spacer 118 ), for example (CVD) process and plasma enhanced chemical vapor deposition of silicon nitride is formed by the process is made by chemical vapor deposition, but the material and method of forming a conformal dielectric layer is not limited. The dielectric layer (ie the spacer 120), for example, and forming a dielectric plug 116a made of the same material. See 1E, multilayer dielectric spacer 122 and the plug 116a as a mask, etching process is performed with the conductor The second opening 124 is formed in layer 104 and the conductive layer 104 is separated into a first floating gate 104a and the second floating electrode pair register 104b. In the present embodiment, only the second opening 124 through the conductive layer 104 (e.g. Fig. 1D) and tunneling dielectric layer exposed portion 102. However, presenting at the second opening of the structure 124 of the present embodiment is not to limit the scope of the present invention. That is, for the different manufacturing needs, a second It may also pass through opening 124 tunneling dielectric layer 102 to expose the base portion 100. Further, the second opening is formed in the substrate 124 IOO self-aligned under the light doped regions doped region 126. The self-aligned light 126 forming step may utilize ion concentration, the implantation energy of about 10keV to inject ions reach 1018 per cubic centimeter. Furthermore, a dopant such as arsenic ions, nitrogen ions and phosphorus ions, but is not limited. See 1F, to form a dielectric layer 128 to fill the second opening 124. The dielectric layer 128, for example, the use of plug and forming a dielectric spacer 116a and the same dielectric material 120 made of, for example, and the dielectric layer 128 is LPCVD process to form. See Fig. 1G and 1H, the flattening process until exposing the first floating gate 104a and the second floating gate 104b. make this flattening process method comprises a first floating gate l (L-type spacer portion Ma and the top surface of the second floating gate 104b, 118 (shown in FIG. 1F) the stop layer, planarizing process is performed to remove portions of the dielectric layer 128 and the multilayer spacers 122 , then remove the other L-shaped spacer 118, until it is completely exposed top surface of the first floating gate electrode 104a and the second floating gate 104b. Further, other removal step 118 of the L-shaped spacer is carried out e.g. Chemical milling machine such as a ^ f (CMP) process, a wet etching process or a dry etching process to achieve, but it is not limited in this planarization process, the beginning of the CMP process, since the dielectric layer 128, spacer 1M and a dielectric plug 116a is made of the same material, and the L-shaped spacer 118 very small amount of polishing, polishing rate can be maintained stable. However, when most of the spacer 118 is removed, and the L-shaped gap drastically reducing the amount of polishing wall 118, since the grinding gap wall 118 L-type dielectric layer (ie dielectric spacer and plug 116a) selectivity, CMP process stops. 在平坦化工艺之后,残留的介电插塞被标示为116c,而在第二开口中残留的介电层被标示为128a。 After the planarization process, the residual dielectric plug labeled as 116c, while remaining in the second opening in the dielectric layer is labeled as 128a. 请参阅1H所示,在基底IOO上形成介电层130。 See FIG 1H, a dielectric layer 130 is formed on the substrate IOO. 介电层130例如是介电常数大于4的介电层。 E.g., dielectric layer 130 is a dielectric constant greater than the dielectric layer 4. 较佳的是,介电层l:30例如是氧化硅/氮化硅/氧化硅层或氧化硅/高介电材料(High k Material)/氧化硅层,但并不限定。 Preferably, the dielectric layer l: 30, for example, a silicon oxide / silicon nitride / silicon oxide layer or a silicon oxide / high dielectric material (High k Material) / silicon oxide layer, but is not limited. 此高介电材料可以是具有大于4的介电常数的介电材料。 This high dielectric material having a dielectric constant greater than 4 may be a dielectric material. 而且,此高介电材料8之后,在基底100上形成控制栅极132。 Moreover, this high dielectric material after 8 on a substrate 100 forming the control gate 132. 控制栅极132的材质例如是以多晶硅、掺杂多晶硅,金属硅化物或金属所制成,而且控制栅极132具有约40至200纳米的厚度,控制栅极132的材质与厚度并不限定。 Control gate material 132, for example based on polysilicon, doped polysilicon, made of metal or metal silicide, and control gate 132 has a thickness of about 40-200 nm, control the material and thickness of the gate 132 is not limited. 请继续参照图1H,本发明更提供一快闪存储元件结构。 Please continue Referring to FIG. 1H, the present invention also provides a flash memory element structure. 本发明的快闪存储元件结构包括位于基底100中的数个源极/漏极区112,位于源极/漏极区112之间基底100上的第一浮置栅极104a以及第二浮置栅极104b,其中第一浮置栅极104a以及第二浮置栅极104b以介电层128a彼此隔离,且分别与源极/漏极区112相邻。 A flash memory device structure of the present invention comprises a substrate 100 in a plurality of source / drain regions 112, a source electrode located on the first floating gate 104a between / drain region 112 on the substrate 100 and the second floating gate 104b, wherein the first floating gate 104a and the second floating gate 104b to the dielectric layer 128a isolated from each other, and 112, respectively, adjacent to the source / drain regions. 此快闪存储元件更包括位于第一浮置栅极104a 以及第二浮置栅极104b之间的基底100中的淡掺杂区126。 This flash memory element further comprises a first substrate and a second floating gate 104a between the floating gate 104b doped region 100. Light 126. 再者,控制栅极132位于基底100上,而且藉由介电常数大于4的介电层130与第一浮置栅极104a以及第二浮置栅极104b隔离。 Furthermore, the control gate 132 is positioned on the substrate 100, and by the dielectric constant of the dielectric layer 4 is greater than 130 and the first floating gate 104a and the second floating gate 104b isolation. 此外,源极/漏极区112以及淡掺杂区126具有相同的导电类型。 In addition, the source / drain region 112 and doped region 126 light has the same conductivity type. 另外,第一浮置栅极104a以及第二浮置栅极104b以隧穿介电层102与基底100隔离。 Further, the first floating gate 104a and the second floating gate 104b to the tunneling dielectric layer 102 and the substrate 100 isolated. 图2绘示本发明另一较佳实施例的快闪存储元件的剖面图。 Figure 2 illustrates the present invention, a flash memory element to another preferred embodiment of a sectional view. 本发明另一较佳实施例的快闪存储元件更包括位于源极/漏极区212之间基底200中的数个口袋型注入掺杂区240, 口袋型注入掺杂区240分别邻接源极/漏极区212。 The present invention further preferred embodiment of a flash memory device further comprises a base 200 between several pocket implantation on the source / drain region 212 doped region 240, the pocket implantation doping region 240 are adjacent to the source / drain regions 212. 口袋型注入摻杂区240例如是利用与源极/漏极区212不同导电类型的注入基底200的离子来形成。 Pocket implantation is carried out with doped region 240 and the source / drain regions 212 of different conductivity type implanted ions to the substrate 200 is formed. 注入基底200以形成口袋型注入掺杂区240的离子浓度约为每立方厘米1016至1018个离子,而且这些离子例如是硼离子或氟化硼。 Injecting substrate 200 to form a pocket ion implantation doping concentration area of about 240 per cubic centimeter 1016-1018 ions, and these ions such as boron ions or boron trifluoride. 在本发明中,由于导体层104被介电层128a分离成第一浮置栅极104a 以及第二浮置栅极104b,每个第一浮置栅极l(Ma以及第二浮置栅极l(Mb 可以储存至少一个载子。因此,对于一个单位存储单元而言,存储密度增加了。此外,以介电插塞116a以及多层间隙壁122当作罩幕,淡掺杂区126 是自行对准而形成于基底100中,而未另行使用微影工艺。因此,成本得以降低。另外,以位于第一浮置栅极104a以及第二浮置栅极顶表面上的L 型间隙壁118当作研磨终止层,为移除介电层128、间隙壁以及介电插塞116a所进行的CMP工艺可以得到良好的控制。因此,第一浮置栅极104a 以及第二浮置栅极104b在平坦化工艺后的形状可以较为一致。显而易见,对于熟知此技艺者,本发明可做各种调整与变化而不脱离本发明的范围与精神。在以上的描述中,若这些调整与变化属于权利要求以及等效叙述的范围,则本发明包括对其本身的各种调整以及变化。虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何熟习此技艺者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视权利要求界定为准。9 In the present invention, since the conductive layer 104 is a dielectric layer 128a is separated into a first floating gate electrode 104a and the second floating gate 104b, each of the first floating gate l (Ma and the second floating gate l (Mb can be stored at least one carrier. Thus, for a unit storage unit, the storage density increases. In addition, the plug 116a and the dielectric multilayer spacer 122 as a mask, the doped region 126 is light The formed self-aligned to the substrate 100, without using a separate lithographic process. Accordingly, the cost can be reduced. Further, in the first floating gate 104a and the L-shaped spacers on the top surface of the second floating gate 118 as a polishing stop layer, a dielectric layer 128 is removed, and a dielectric spacer 116a plug CMP process can be carried out to obtain good control. Thus, the first floating gate electrode 104a and the second floating gate 104b in shape after the planarization process can be more consistent. Obviously, for those familiar with this art, the present invention can do all kinds of adjustments and changes without departing from the scope and spirit of the invention. In the above description, if these adjustments and changes belong claims and the scope of the narrative equivalent of the present invention includes a variety of their own adjustments and changes. Although the present invention has been revealed as the preferred embodiment, however it is not intended to limit the present invention, any person skilled in this art, without departing from the spirit and scope of the present invention, it is intended that modifications and variations, and the scope of the invention as defined in claim depending on whichever .9

Citations de brevets
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Classifications
Classification internationaleH01L27/105
Événements juridiques
DateCodeÉvénementDescription
21 mars 2007C06Publication
16 mai 2007C10Request of examination as to substance
24 févr. 2010C14Granted