CN100594729C - MPEG-2 packet synchronously checking byte generating apparatus - Google Patents
MPEG-2 packet synchronously checking byte generating apparatus Download PDFInfo
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- CN100594729C CN100594729C CN 200810119513 CN200810119513A CN100594729C CN 100594729 C CN100594729 C CN 100594729C CN 200810119513 CN200810119513 CN 200810119513 CN 200810119513 A CN200810119513 A CN 200810119513A CN 100594729 C CN100594729 C CN 100594729C
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Abstract
The present invention discloses a method for synchronously checking and generating an MPEG-2 packet. A checking byte generator which is realized by the method consists of a polynomial operation module1 (100), a polynomial operation module 2 (101), a 1497 bit retarder (110), a logical operation module (111) and a 7-time shift register (000), wherein the 8bit data consisting of the 7-bit output ofthe 7-time shift register (000) and the output of the logical operation module (111) is used as the output for the checking byte generator, as illustrated in the figure. After inputting 188-byte data,the checking byte generator obtains an output of octet data for determining whether the position of a synchronous checking byte, i.e. a sync bit, is found. Afterward, an output of octet data can be obtained by each bit of the inputted data, and the output is used for determining whether the position of the synchronous checking byte is found. The method is high in operational efficiency, comparedwith the polynomial multiplication method, and saves resources, compared with the matrix multiplication method.
Description
Technical field
The invention belongs to the Channel Transmission part in the cable digital TV transmission system.
Background technology
The cable digital TV transmission system is to utilize the system of cable TV (CATV) Network Transmission multi-path digital TV programme, in this system, current have a plurality of standards that can be suitable for, ANSI/SCTE 07 2000 standards, be the Channel Transmission standard of the cabled digital video transmission of American National Standard Committee issue, include the appendix B in the standard J.83 in International Telecommunications Union.
ANSI/SCTE 07 2000 standards are mainly carried out the processing of channel strip, and at transmitting terminal, it is input as the MPEG-2 packet, according to the standard of MPEGII, contain 188 bytes in each MPEG-2 packet, and wherein, first byte is a sync byte.ANSI/SCTE 07 2000 standard codes to the input the MPEGII packet do following processing: with 187 bytes except that sync byte in each MPEG-2 packet by the computing of appointment, the result of computing is a byte, claim that this byte is the synchronization check byte, and replace sync byte in the next MPEG-2 packet with this byte, as shown in Figure 1.Both can be used for synchronous identification through the MPEG-2 packet sync byte of handling like this, can judge again whether the MPEG-2 packet is correct.
At receiving terminal, can do opposite processing to the MPEG-2 packet that has the synchronization check byte of input.In the MPEG-2 packet of input,, when finding the synchronization check byte, it is replaced with the sync byte of MPEGII standard code, promptly 47 by calculate seeking the position of synchronization check byte
HEX
Seek synchronization check byte position, the method of promptly seeking sync bit is that the MPEG-2 packet that will have check byte is input in the check byte generator, the check byte generator can produce one eight data, whether equals 47 by the value of judging these data of eight again
HEX, judge whether to find sync bit.Usually the method that realizes the check byte generator has two kinds.
First method is and polynomial multiplication.
The principle of this method is check byte generator initialization after everybody is set to 0,188 byte MPEG-2 data of sequential serial input, and the mode by XOR and displacement realizes that each all multiplies each other with polynomial f (X), wherein,
f(X)＝(1+X
1497b(X))/g(X)
b(X)＝1+X+X
3+X
7
g(X)＝1+X+X
5+X
6+X
8
The circuit of this method as shown in Figure 2, each input is all carried out XOR with of the right side of linear feedback shift register in the circuit, the result of computing had both fed back in the displacement feedback register, entered Z again
-1497In, i.e. No. 1497 shift registers, carry out 1497 displacements after, carry out computing with rightmost one of another linear feedback shift register again, at last again with Z
-1497Input export after doing XOR.The input and output of circuit all are 1, and the data input validation byte generator of 188 bytes produces 188 bytes through after the computing, i.e. 1504 output, and last eight are used to judge whether to equal 47
HEX, equal 47
HEX, find sync bit, be not equal to 47
HEX, then do not find sync bit.After every input 188 byte datas of this method are calculated once, carry out computing next time before, all need device is carried out initialization, import 188 bytes again, obtain effective eight outputs.The output of this circuit need connect one 7 bit shift register, and 8 bit data of the output of 7 registers of the output of this circuit and 7 bit shift register composition are the dateout of this check byte generator like this.
This check byte generator need be with the XOR gate of 1519 registers and 8 two input, and 1497 registers wherein can be realized with RAM.
If the circuit scale of this method is 1 area equivalent, the required time that produces a check byte is designated as 1 time equivalent.Under the constant situation of circuit work frequency, from a continuous input traffic, find the synchronization check byte on average to spend 752 time equivalents with the circuit of 1 area equivalent; If will on average find the synchronization check byte, then need 1504 area equivalent circuit with 1 time equivalent.
Second method is and matrix multiple.
The implementation method of the check byte generator of this method is as follows:
Known 1497 dimensional vector C, vectorial C is made of 374 hexadecimal numbers and a binary number, as shown in Figure 3.Form each row of a matrix by eight vectorial C, wherein each row is all to line down, and fill by 0 vacant position, obtains 1504 * 8 matrix P, as shown in Figure 4.188 bytes of input, promptly 1504 data are regarded 1504 dimensional vector R as, obtain one eight vectorial S by R * P, as shown in Figure 5.
This check byte generator is imported the output that draws an eight bit data after 188 byte datas, and later every input one digit number is used to judge whether to find sync bit, as shown in Figure 6 according to the output that all can draw an eight bit data.
If this method produces the required time of a check byte and is designated as 1 time equivalent.Under the constant situation of circuit work frequency, from a continuous input traffic, find the synchronization check byte on average to spend 1 time equivalent.Than having saved the time, improved operating efficiency, but the XOR gate of 1504 registers and 751 two inputs has been used in the realization of this method, need take ample resources with the polynomial multiplication method.
Summary of the invention
The check byte generator that the present invention realized can realize importing the output that draws an eight bit data after 188 byte datas, and later every input one digit number is used to judge whether to find sync bit according to the output that all can draw an eight bit data.Under the steady job frequency, 1054 computings are designated as the computing of 1 equivalent.If this check byte generator produces the required time of a check byte and is designated as 1 time equivalent, under the constant situation of circuit work frequency, from a continuous input traffic, find the synchronization check byte on average to spend 1 time equivalent.The check byte generator that the present invention realized need be with the XOR gate of 1520 registers and 12 two input, and 1497 registers wherein can be realized with RAM.Compare with method in the literary composition one, under the constant situation suitable of circuit work frequency, on average spend 1 time equivalent and can find the synchronization check byte, improved operating efficiency with circuit scale; Compare with method two in the literary composition, the present invention realizes storage with RAM, and has used the XOR gate of a large amount of two inputs less, and the power consumption of reduction has been saved resource.
The check byte generator that the present invention realized is made up of multinomial operation module 1 (100), 2 (101), 1497 delayers of multinomial operation module (110), logical operation module (111) and No. 7 shift registers (000), as shown in Figure 7, need carry out initialization when this check byte generator is started working, the output state of each register is set to 0.
Serial input data enters 1 (100) and 1497 delayer of multinomial operation module (110) respectively; The output of multinomial operation module 1 (100) flows to logical operation module (111); The output of 1497 delayers (110) flows to multinomial operation module 2 (101) and logical operation module (111); The output of multinomial operation module 2 (101) flows to logical operation module (111); The output of logical operation module (111) flows to No. 7 shift registers (000); 8 bit data that the output of the output of last No. 7 shift registers and logical operation module (111) constitutes are as the output of check byte generator.
Description of drawings
Fig. 1 is the transmitting terminal data handling procedure;
Fig. 2 be with the polynomial multiplication method in the circuit diagram of check byte generator;
Fig. 3 is the pie graph of vectorial C;
Fig. 4 is the pie graph of matrix P;
Fig. 5 is the generating principle figure of vectorial S;
Fig. 6 be with the matrix multiple method in the schematic diagram of the check byte generator course of work;
Fig. 7 is the circuit diagram of check byte generator among the present invention;
Fig. 8 realizes Z among the present invention with RAM
-1497Structure chart.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described by concrete implementation process.
The check byte generator circuit that the present invention realized as shown in Figure 7.This circuit is made up of multinomial operation module 1 (100), 2 (101), 1497 delayers of multinomial operation module (110), logical operation module (111) and No. 7 shift registers (000), need carry out initialization when this check byte generator is started working, the output state of each register is set to 0.
The multinomial operation module 1 (100) of present embodiment, form by linear feedback shift register, comprise 8 registers and 4 XOR gate, the output signal that is input as the 4th XOR gate of the 1st register, the output of the 1st register flows to the 2nd register, the output of the 2nd register flows to the 1st XOR gate, another of the 1st XOR gate is input as the output signal of the 4th XOR gate, the output of the 1st XOR gate flows to the 3rd register, the output of the 3rd register flows to the 2nd XOR gate, another of the 2nd XOR gate is input as the output signal of the 4th XOR gate, the output of the 2nd XOR gate flows to the 4th register, the output of the 4th register flows to the 5th register, the output of the 5th register flows to the 6th register, the output of the 6th register flows to the 7th register, the output of the 7th register flows to the 3rd XOR gate, another of the 3rd XOR gate is input as the output signal of the 4th XOR gate, the output of the 3rd XOR gate flows to the 8th register, the output of the 8th register flows to the 4th XOR gate, another of the 4th XOR gate is input as the input signal of the check byte generator of the present invention's realization, and the output of the 4th XOR gate flows to logical operation module (111) as the output signal of multinomial operation module 1 (100).
1497 delayers (110) of present embodiment are the functions that RAM realizes No. 1497 shift registers, and the structure chart of realization as shown in Figure 8.The data of serial input write among the RAM the every N of data position through deserializer successively, and sense data converts serial output by parallel-to-serial converter to by the input of N parallel-by-bit from RAM, and wherein, address generator is used for controlling and producing the read/write address of RAM.Read again after writing the input data of this check byte generator among the RAM in 1497 delayers (110), dependence is read and write different addresses, realize bits per inch according to 1497 outputs again of time-delay, and flowed to multinomial operation module 2 (101) and logical operation module (111).
The multinomial operation module 2 (101) of present embodiment, its inner structure is identical with the structure of multinomial operation module 1 (100), comprise 8 registers and 4 XOR gate, the output signal that is input as the 4th XOR gate of the 1st register, the output of the 1st register flows to the 2nd register, the output of the 2nd register flows to the 1st XOR gate, another of the 1st XOR gate is input as the output signal of the 4th XOR gate, the output of the 1st XOR gate flows to the 3rd register, the output of the 3rd register flows to the 2nd XOR gate, another of the 2nd XOR gate is input as the output signal of the 4th XOR gate, the output of the 2nd XOR gate flows to the 4th register, the output of the 4th register flows to the 5th register, the output of the 5th register flows to the 6th register, the output of the 6th register flows to the 7th register, the output of the 7th register flows to the 3rd XOR gate, another of the 3rd XOR gate is input as the output signal of the 4th XOR gate, the output of the 3rd XOR gate flows to the 8th register, the output of the 8th register flows to the 4th XOR gate, another of the 4th XOR gate is input as the output signal of 1497 delayers (110), the output of multinomial operation module 2 (101) has 4, by the 3rd, the 4th, the output signal of the 6th and the 7th register is formed, and flows to logical operation module (111).
The logical operation module of present embodiment (111), comprise 5 XOR gate, the the 3rd and the 4th register is output as the input of the 1st XOR gate in the multinomial operation module 2 (101), the 6th register is output as the input of the 2nd XOR gate in the output of the 1st XOR gate and the multinomial operation module 2 (101), the 7th register is output as the input of the 3rd XOR gate in the output of the 2nd XOR gate and the multinomial operation module 2 (101), the output of the 3rd XOR gate and 1497 delayers (110) are output as the input of the 4th XOR gate, the output of the 4th XOR gate and multinomial operation module 1 (100) are output as the input of the 5th XOR gate, the output of the 5th XOR gate flows to No. 7 shift registers (000) as the output of logical operation module (111).
No. 7 shift registers (000) of present embodiment comprise 7 registers, to carry out 7 displacements from the input data of logical operation module (111).8 bit data that the output of the output of these 7 registers and logical operation module (111) constitutes are as the output of check byte generator.
A kind of new MPEG-2 bag synchronization check that the present invention proposes and the check byte generator in the generation method, both than with polynomial multiplication method high efficiency, used a large amount of XOR gate than lacking again with the method for matrix multiple, saved resource.
Claims (2)
1, a kind of MPEG-2 bag synchronization check byte generator, it is characterized in that described check byte generator comprises: multinomial operation module 1 (100), 2 (101), 1497 delayers of multinomial operation module (110), logical operation module (111) and No. 7 shift registers (000), need carry out initialization when described check byte generator is started working, the output state of each register is set to 0;
Wherein, described multinomial operation module 1 (100), comprise 8 registers and 4 XOR gate, the output signal that is input as the 4th XOR gate of the 1st register, the output of the 1st register flows to the 2nd register, the output of the 2nd register flows to the 1st XOR gate, another input of the 1st XOR gate also is the output signal of the 4th XOR gate, the output of the 1st XOR gate flows to the 3rd register, the output of the 3rd register flows to the 2nd XOR gate, another of the 2nd XOR gate is input as the output signal of the 4th XOR gate, the output of the 2nd XOR gate flows to the 4th register, the output of the 4th register flows to the 5th register, the output of the 5th register flows to the 6th register, the output of the 6th register flows to the 7th register, the output of the 7th register flows to the 3rd XOR gate, another of the 3rd XOR gate is input as the output signal of the 4th XOR gate, the output of the 3rd XOR gate flows to the 8th register, the output of the 8th register flows to the 4th XOR gate, another of the 4th XOR gate is input as the input signal of described check byte generator, and the output of the 4th XOR gate flows to logical operation module (111) as the output signal of multinomial operation module 1 (100);
Described 1497 delayers (110), read again after will importing among the RAM that data write 1497 delayers (110) successively, dependence is read and write different addresses, realize bits per inch according to 1497 outputs again of time-delay, and flowed to multinomial operation module 2 (101) and logical operation module (111);
Described multinomial operation module 2 (101), its inner structure is identical with the structure of multinomial operation module 1 (100), comprise 8 registers and 4 XOR gate, the output signal that is input as the 4th XOR gate of the 1st register, the output of the 1st register flows to the 2nd register, the output of the 2nd register flows to the 1st XOR gate, another of the 1st XOR gate is input as the output signal of the 4th XOR gate, the output of the 1st XOR gate flows to the 3rd register, the output of the 3rd register flows to the 2nd XOR gate, another of the 2nd XOR gate is input as the output signal of the 4th XOR gate, the output of the 2nd XOR gate flows to the 4th register, the output of the 4th register flows to the 5th register, the output of the 5th register flows to the 6th register, the output of the 6th register flows to the 7th register, the output of the 7th register flows to the 3rd XOR gate, another of the 3rd XOR gate is input as the output signal of the 4th XOR gate, the output of the 3rd XOR gate flows to the 8th register, the output of the 8th register flows to the 4th XOR gate, another of the 4th XOR gate is input as the output signal of 1497 delayers (110), the output of multinomial operation module 2 (101) has 4, by the 3rd, the 4th, the output signal of the 6th and the 7th register is formed, and flows to logical operation module (111);
Described logical operation module (111), comprise 5 XOR gate, the the 3rd and the 4th register is output as the input of the 1st XOR gate in the multinomial operation module 2 (101), the 6th register is output as the input of the 2nd XOR gate in the output of the 1st XOR gate and the multinomial operation module 2 (101), the 7th register is output as the input of the 3rd XOR gate in the output of the 2nd XOR gate and the multinomial operation module 2 (101), the output of the 3rd XOR gate and 1497 delayers (110) are output as the input of the 4th XOR gate, the output of the 4th XOR gate and multinomial operation module 1 (100) are output as the input of the 5th XOR gate, and the output of the 5th XOR gate flows to No. 7 shift registers (000) as the output of logical operation module (111).
2, a kind of MPEG-2 bag synchronization check byte generator described in claim 1, it is characterized in that described No. 7 shift registers (000) comprise 7 registers, to carry out 7 displacements from the input data of logical operation module (111), 8 bit data that the output of the output of described 7 registers and described logical operation module (111) constitutes are as the output of check byte generator.
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