CN101004899B - Peripheral driver circuit of liquid crystal electro-optical device - Google Patents

Peripheral driver circuit of liquid crystal electro-optical device Download PDF

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Publication number
CN101004899B
CN101004899B CN2007100840894A CN200710084089A CN101004899B CN 101004899 B CN101004899 B CN 101004899B CN 2007100840894 A CN2007100840894 A CN 2007100840894A CN 200710084089 A CN200710084089 A CN 200710084089A CN 101004899 B CN101004899 B CN 101004899B
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register
circuit
liquid crystal
shift
power
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CN101004899A (en
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小山润
尾形靖
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Abstract

In a peripheral driver circuit of a liquid crystal electro-optical device is comprised of a shift register circuit arranged by a plurality of registers, and a circuit for supplying power to each register. When an input signal is entered into an nth register, a supply of power to at least a portion of registers other than the nth register is stopped. The shift register circuit is constructed of a P-channel type TFT and a resistor. The circuit for supplying the power controls the supply of power to the shift register by using the output of the shift register circuit. This circuit for supplying the power is arranged by a P-channel type TFT and a resistor. The consumption power of the circuit for supplying the power is equal to and lower than that of the shift register circuit.

Description

The peripheral driver circuit of liquid crystal electro-optical
The present patent application is to be that August 16 nineteen ninety-five, application number are that of 95115111.8 patented claim of the same name divides an application the applying date.
Technical field
The present invention relates to the peripheral driver circuit of liquid crystal electro-optical, specifically, relate to the peripheral driver circuit of the liquid crystal electro-optical of under low-power consumption, working.
Background technology
In the art, the liquid crystal electro-optical of Figure 29 is known, and is to be made of PEL matrix part 2901, signal line drive circuit 2902 and scan line driver circuit 2903.
In PEL matrix part 2901, sweep trace 2904 and signal wire 2905 are configured to matrix form.Specifically, in active matrix, pixel thin film transistor (TFT) (TFT) 2906 is set on high crunode, the grid of pixel TFT 2906 is linked on the sweep trace 2904, and its source electrode is linked on the signal wire 2905, and drain electrode is linked on the pixel capacitors.Generally speaking, because formed liquid crystal capacitor 2907 can not obtain big electric capacity between pixel capacitors and counter electrode, then a preservation electric capacity 2908 that is used to preserve electric charge is set on the pixel capacitors side.
When being added on the sweep trace above pixel TFT threshold voltage according, make pixel TFT conducting, be the short circuit attitude between its source-drain electrode.Like this, the voltage on the signal wire is added on the pixel capacitors thereupon, so, to liquid crystal capacitance and the charging of preservation electric capacity.When TFT disconnected, drain electrode was off-state, before the basic conducting of TFT, existed the electric charge in liquid crystal capacitance and the preservation electric capacity keeping always.
Signal line drive circuit 2902 is made of shift register 2909, buffer circuits 2910 and sample circuit 2911.In shift-register circuit 2909, the input signal synchronous with vision signal is added on the terminal 2912, and thereupon according to the time pulse and order displacement.The output of shift-register circuit 2909 is added on the sample circuit 2911 through paraphase type buffer circuit 2910.
Sample circuit 2911 is to be made of analog switch 2913 and preservation capacitor 2914.Analog switch 2913 is ON/OFF by buffer circuits 2910 actuatings.In conducting state, video signal cable 2915 and 2914 short circuits of preservation capacitor are so electric charge is deposited and preserved in the capacitor 2914.Signal wire 2905 is linked to be preserved on the capacitor 2914, and the vision signal after the sampling is added on each pixel.
Scan line driver circuit 2903 forms by shift register 2916 with 2917 configurations of noninverting type impact damper, and comes the driven sweep line by the synchronous input signal of input on its input end and vertical synchronizing signal with the horizontal-drive signal clock signal synchronous subsequently.
As shift-register circuit, might adopt the clock chamber phase inverter 3001 of Figure 30 A and sending out of Figure 30 B to close the door 3002.
In Figure 31, show the shift register that the clock phase inverter of Figure 30 A that is realized by cmos circuit constitutes.
As the peripheral driver circuit of liquid crystal electro-optical, when on forming the transparent substrates of PEL matrix, constituting shift register, following shortcoming is arranged with the CM0S circuit.That is: owing to will make P channel TFT and N channel TFT, then the sum of manufacturing step increases.The characteristic of P channel TFT is difficult for consistent with the characteristic of N channel TFT.N channel TFT rapid wear.On the contrary, do not comprise the problems referred to above that shift register produced with the shift-register circuit of P channel-type TFT and register shown in Figure 32 with cmos circuit.
Shown in figure 32, in the shift-register circuit that adopts P channel-type TFT and register, when 3201 conductings of P channel TFT, power supply 3202 like this, will have electric current to flow through through resistor 3,204 3203 short circuits over the ground, and power consumption increases.When the resistance increase of resistor 3204 can not be flow through electric current, then can not more easily carry out discharge operation, will be delayed from the charging of supply voltage voltage-to-ground.That is to say,, just be difficult to increase resistance because frequency characteristic degenerates.Really the serious problem of this high power consumption be used to when liquid crystal electro-optical on the time such as the various electronic installations of pocket massaging device.
Figure 33 is that traditional liquid crystal electro-optical comprises PEL matrix part 3301, signal line drive circuit 3302 and scan line driver circuit 3303.In PEL matrix part 3301, sweep trace 3304 and signal wire 3305 are configured to rectangular.Particularly in active matrix, pixel TFT 3306 is configured on the cross section, and the canopy utmost point of pixel TFT 3306 is linked on the sweep trace 3304, and its source electrode is linked to signal wire 3305, and its drain electrode is linked on the pixel capacitors.
When the voltage of the threshold value that surpasses pixel TFT is added on the sweep trace, pixel TFT conducting.Under this state, the drain electrode of pixel TFT and source electrode are the short circuit attitude, and are added on the pixel capacitors at the voltage on the signal wire, and like this, electric charge is stored on the liquid crystal capacitor.When pixel TFT disconnected, drain electrode was the attitude that opens circuit, and before the basic conducting of pixel TFT, exists the electric charge in the liquid crystal capacitance to be held.
Liquid crystal capacitor 3307 between pixel capacitors sum counter electrode can not have high capacity.As a result, between following one-period, electric charge can not be maintained by liquid crystal capacitor 3307 before pixel TFT conducting, and like this, the voltage that is added on the liquid crystal is changed, thereby changed briliancy.Thereby, at the preservation capacitor 3308 that is provided for keeping electric charge near pixel capacitors.Therefore, after pixel TFT conducting, the two all is recharged liquid crystal capacitor and preservation capacitor.
As shown in figure 34, the signal line drive circuit is made of shift-register circuit 3401, buffer circuit 3402 and sample circuit 3403.In shift-register circuit, import and the synchronous input signal of vision signal, and be shifted in proper order according to time clock.The output of shift-register circuit is input on the sample circuit through anti-phase buffer circuit.
Sample circuit comprises analog switch 3404 and preserves capacitor 3405.Analog switch by buffer circuit control ON/OFF with to video signal sampling.Sampled signal is held as the electric charge of preserving in the electric capacity.Signal wire is linked to be preserved on the electric capacity, and the sample video signal sends on each pixel through this signal wire.
As the signal line drive circuit, available decoder replaces shift-register circuit to use.After each pixel and address combined correspondingly, then vision signal was written in the pixel, and corresponding address is input in the signal line drive circuit, and selected one of these signal wires by decoder circuit.On selected signal wire, the decoded signal sampling of vision signal maintains subsequently as the electric charge of preserving in the electric capacity.
In addition, as the signal line drive circuit, also can adopt decoder circuit sum counter circuit, to clock pulse count, and the output of counter circuit is used as address signal by counter circuit.According to address signal, select a signal wire by decoder circuit, the vision signal of sampling is write in the pixel.
Figure 35 is illustrated in the situation of using decoding circuit in the signal line drive circuit.By Sheffer stroke gate 3502 selecting address signals input 3501, the output of Sheffer stroke gate 3502 is used as the input of analog switch 3503.By analog switch to video signal sampling, and the sampling after signal stored the electric charge that is used as preserving in the circuit 3504.Figure 36 illustrates the situation that adopts demoder sum counter circuit in the signal line drive circuit.By 3602 pairs of time clock input 3601 countings of counter circuit.As address signal, and the output of Sheffer stroke gate 3603 is imported on the analog switch 3604 by the output of Sheffer stroke gate 3603 gated counter circuit.To video signal sampling, and the vision signal after the sampling is held as input and preserves electric charge in the electric capacity 3605 by analog switch.
In Figure 37, scan line driver circuit is made of shift register 3701 and the anti-phase type impact damper 3702 of NAND circuit.All be input in the scan line driver circuit with the synchronous input signal of vertical synchronizing signal with the synchronous clock of horizontal-drive signal, with driven sweep line sequentially.In addition, in this scan line driver circuit, decoding circuit, or the alternative shift register of the combination of decoding circuit and counter circuit.
As the peripheral driver circuit of liquid crystal electro-optical, when on forming the transparent substrates of PEL matrix when using cmos circuit to constitute shift register, have following shortcoming.That is to say that owing to will make P channel-type TFT and N channel-type TFT, total manufacturing step number increases.The characteristic of P channel-type TFT is not easy to do consistently with the characteristic of N channel-type TFT.On the contrary, the external circuit of the TFT of a kind of conduction mode of N raceway groove of the TFT of a kind of conduction mode of employing P raceway groove or band register can not comprise the problem of the external circuit that passes through the use cmos circuit as previously explained.
The another kind of circuit that adopts P channel TFT and register also is shown.In Figure 38 A to 38C, NAND circuit, NOR circuit and negative circuit are arranged, as a kind of basic circuit, it can constitute the J-K flip flop of Figure 39 and the 4 digit counter circuit of Figure 40.Counter circuit produces the output signal of pulsation carry 4005, in response to counter bit output and anti-phase output, zero clearing 4002, the clock 4003 of power supply 4001 each input signal and allow 4004.
Under the situation of the peripheral driver circuit of making P channel TFT and resistance on the transparent substrates that constitutes PEL matrix, when P channel-type TFT conducting, power supply will have electric current to flow through through the resistance shorted to earth like this in the circuit that uses Figure 38, so power consumption increases.After the resistance of resistor increases, when electric current is flow through, discharge can not be carried out easily, and delayed time to the transformation of ground voltage from supply voltage.That is to say,, be difficult to increase resistance value because frequency characteristic degenerates.This high power consumption can cause serious problems on liquid crystal electro-optical being used in such as the various electronic installations of pocket massaging device the time.
Summary of the invention
The object of the present invention is to provide a kind of peripheral driver circuit of liquid crystal electro-optical, when whole device is driven, even when adopting shown in Figure 32 high power consumption shift-register circuit, can reduce power consumption.
Another object of the present invention is to provide a kind of even when the peripheral driver circuit that adopts Figure 38, during the peripheral driver that promptly forms by thin film transistor (TFT) (TFT) and resistor configuration, can reduce the circuit arrangement of the whole liquid crystal electro-optical power demand of driving.
For addressing the above problem, according to an aspect of the present invention, the peripheral driver circuit of liquid crystal electro-optical comprises: the shift-register circuit that is formed by a plurality of register configuration and be used for power supply is added to circuit on each register or each part.When input signal enters into n register, stop at least a portion power supply of the register outside n register.Shift-register circuit of the present invention is made of P channel TFT and resistor.Provide power supply by the circuit control that power supply is provided to shift register by the output of using shift-register circuit.Being used to the circuit of power supply is provided is to be formed by P channel TFT and resistor configuration.The power consumption of power circuit is not more than the power consumption of shift-register circuit.
According to a further aspect in the invention, the shift-register circuit that becomes by a plurality of register configuration of the peripheral driver circuit of liquid crystal electro-optical and be used for the circuit that power supply is added on each register or each part is constituted.When signal enters n register, stop before (n-2) register and (n+2) register after register power supply is provided.Shift-register circuit of the present invention is made of P channel TFT and resistance.By using the output of shift-register circuit, provide power supply to shift register by power circuit control.Be used to provide the circuit of power supply to constitute by P channel TFT and resistor.The power consumption of power circuit is not more than the power consumption of shift-register circuit.
According to a further aspect in the invention, the shift-register circuit that becomes by a plurality of register configuration of the peripheral driver circuit of liquid crystal electro-optical and be used for the circuit that power supply is added on each register or each part is constituted.When signal enters n register, stop before (n-X) register, providing power supply with (n+Y) register (X 〉=2, and Y 〉=2) register afterwards.Shift-register circuit of the present invention is made of P channel TFT and resistance.By using the output of shift-register circuit, provide power supply to shift register by power circuit control.Be used to provide power circuit to constitute by P channel TFT and resistor.The power consumption of power circuit is not more than the power consumption of shift-register circuit.
According to a further aspect in the invention, the shift-register circuit that becomes by a plurality of register configuration of the peripheral driver circuit of liquid crystal electro-optical and be used for the circuit that power supply is added on each register or each part is constituted.In this outside drive circuit, shift register is further divided into a plurality of, and each of these pieces is formed by the register configuration more than, and power circuit is linked on each of a plurality of independently.When input signal enters when constituting in the register by a plurality of, any that stops outside this piece provides power supply.Shift-register circuit of the present invention is made of P channel TFT and resistance.The power consumption of power circuit is not more than the power consumption of shift register.
In order to reduce the power consumption of whole peripheral driver circuit, externally in the drive circuit the work of shift register of color usefulness will be considered into.The required function of shift register in the peripheral driver circuit is and signal of clock synchronization transmission.That is to say that only the part of peripheral driver circuit is used as shift register.
Therefore, in Fig. 1, when input signal enters n register of shift register 102, stop the register power supply before (n-1) register that transmitted signal, keep this output simultaneously, the last level to impact damper 104 and sampling thief 105 does not have negative effect.In addition, the register that also stops after (n+1) register 107 after the input signal transmission is powered.Similarly, in shift register 108, when input signal enters n register 110, stop register 111 and 112 power supplies of the register after (n+1) register before (n-1) register, keep output simultaneously, impact damper 109 is not had negative effect.
As mentioned above, though when entire circuit is worked, need high power consumption, by only making relevant circuit working, even when its relative section power consumption does not become, overall power is reduced.
In Figure 12 A, the peripheral driver circuit that comprises the shift-register circuit that formed by a plurality of register configuration and the liquid crystal electro-optical of power supply is provided to each register or each several part is shown.When input signal enters n register, stop before (n-2) register and (n+2) register after the register power.
In shift register, when two adjunct registers produced effective output simultaneously, (n-1) register also produced effectively output when input signal arrives n register, like this, can stop the register power supply before (n-2) resistor.
When pulsewidth is when being determined by a clock time cycle, when arriving n register, input signal begins to (n+1) register power supply that need not produce effective output, and subsequently, when next clock changed, input signal was positively spread out of.As a result, when input signal arrives n register, can stop the register power supply after (n+2) register.Can allow if postponed any variation of the pulsewidth of the input signal cause by element, the register that then stops to (n+1) register after is powered.
In Figure 18 A, when total parts number wishes to reduce rather than power consumption when reducing, stopping not and being subject to above-mentioned situation of power supply promptly, stops to the product of (n-2) register (n+2) register power supply afterwards being arranged.That is to say, when input signal arrives n register,, then can stop to (n-X) register (X 〉=2) power supply because the work of (n-2) register power supply is continued, and also not to (n-3) or (n-4) register power supply.
When input signal arrives n register, can stop to (n+Y) register (Y 〉=2) power supply, because power supply is added to (n+2) register, and not to (n+3) and (n+4) register power supply.
In Fig. 4, peripheral driver circuit comprises the shift-register circuit that become by a plurality of register configuration and to the circuit of each register or the power supply of each part.Shift-register circuit has a plurality of.Each piece is made of at least two registers.Power circuit links with each piece individually.When input signal enters into the included register of one of each piece, stop to each piece power supply except that a piece.
Fig. 8 illustrates power circuit.Can provide a control circuit to control a single register to each of these registers.After control circuit complicates, several registers are bonded to each other constitute a controll block.Under this state, when input signal is sent out between these pieces/time receiving, at this moment between in the cycle, supply voltage is added on two pieces.Power supply is added to the piece that is used for receiving inputted signal, and stops to be added on the piece of receiving inputted signal not.
In addition, peripheral driver circuit is to be formed by a kind of conductivity type TFT and capacitor arrangements.In other words, peripheral driver circuit comprises a circuit that is used to control power work, and this circuit is to be made of a kind of conductivity type TFT, resistor and capacitor.
According to one aspect of the present invention in the peripheral driver circuit of liquid crystal electro-optical, when power supply is added the circuit part that needs particular pixels, stop the power supply at least a portion of foregoing circuit.
According to a further aspect in the invention, when power supply is added to the circuit part that needs particular pixels, reduce the voltage of at least a portion that is added to the foregoing circuit part.
In addition, according to a further aspect in the invention, in scan line driver circuit, when voltage is added to n pixel or by n sample circuit in the signal line drive circuit during to signal sampling, reduce be added to the part corresponding with pixel after (n+1) pixel and with the supply voltage of (n-2) pixel corresponding part of pixel before.
In peripheral driver circuit according to a further aspect of the invention, after signal after voltage is added to n pixel or sampling was written into n pixel, minimizing was added in the drive circuit with (n+X) pixel (X 〉=1) and (n-Y) voltage on the part that pixel (Y 〉=2) is corresponding.
In peripheral driver circuit according to a further aspect of the invention, after a plurality of pixels with matrix structure are subdivided into a plurality of, and when both not had alive pixel also not write the pixel of vision signal of sampling, stop corresponding at least a portion power supply of pixel in piece.
In peripheral driver circuit according to a further aspect of the invention, after a plurality of pixels with matrix structure are subdivided into polylith, and both do not had its voltage to be added to pixel on a plurality of n the piece when not writing the pixel of vision signal of sampling yet, stop after (n+1) piece and (n-1) piece before the corresponding peripheral driver circuit power supply of at least a portion pixel.
In peripheral driver circuit according to a further aspect of the invention, after a plurality of pixels with matrix structure are subdivided into polylith, and both there be not its voltage to be added to pixel on a plurality of n the piece when not writing the pixel of vision signal of sampling yet, stop to the corresponding peripheral driver circuit power supply of at least a portion pixel of (n+X) piece and (n-Y) piece (X 〉=1, Y 〉=1).
In peripheral driver circuit according to a further aspect of the invention, after a plurality of pixels with matrix structure are subdivided into a plurality of, and when both not had alive pixel also not write the pixel of vision signal of sampling, reduce corresponding at least a portion power supply of pixel in piece.
In peripheral driver circuit according to a further aspect of the invention, after a plurality of pixels with matrix structure are subdivided into polylith, and both do not had its voltage to be added to pixel on a plurality of n the piece when not writing the pixel of vision signal of sampling yet, reduced to (n+1) piece after and the corresponding peripheral driver circuit of at least a portion pixel before (n-1) piece is powered.
In peripheral driver circuit according to a further aspect of the invention, after a plurality of pixels with matrix structure are subdivided into polylith, and both do not had its voltage to be added to pixel on a plurality of n the piece when not writing the pixel of vision signal of sampling yet, reduced to (n+1) piece after and the corresponding peripheral driver circuit of at least a portion pixel before (n-1) piece is powered.
In order to reduce the power consumption in the liquid crystal electro-optical peripheral driver, consider peripheral driver circuit.Need to drive liquid crystal according to the transfer voltage characteristic with the voltage of 5V.When DC voltage is added on the liquid crystal, liquid crystal will degenerate.As a result, when driving liquid crystal by alternating voltage, voltage need about 10V.Like this, the supply voltage of external drive circuit needs more than the 20V.
In dot sequential scanning, because vision signal writes on certain pixel, peripheral driver circuit is to video signal sampling, so that pixel TFT conducting.That is to say that whole peripheral driver circuit work is with a specific pixel.In the following description, the work of mentioning below will be known as " pixel is by specific ".That is to say, vision signal be sampled be at a pixel by by the signal line drive circuit to keeping the electric capacity charging, and/or make the pixel TFT that is linked to sweep trace enter that conducting state realizes by scan line driver circuit.
As a result, even after power supply is added to whole peripheral driver circuit, only have its part to devote oneself to work.Therefore, the circuit part as there not being effect (not working) can reduce its voltage, or stops power supply and prevent misoperation.
It is following to reduce power consumption that the part that externally is used for particular pixels in the drive circuit, supply voltage are reduced to 20V.Realized low-power consumption thus.Usually, when external drive circuit is worked under the following voltage of 20V, when pixel by after specific, only supply voltage is made as 20V, thereby realizes low-power consumption.
Power consumption was higher when as mentioned above, entire circuit was worked.But because high pressure only is added on the required part.When the power consumption of each several part was constant, overall power can reduce.
Specifically, in Figure 34, be used at first according to input signal that the circuit of particular pixels is first circuit, the circuit that is used for last particular pixels is a m circuit.When input signal arrived n circuit, it is effective that the output of this circuit becomes.In Figure 34, the output of (n-1) circuit also becomes effective.As a result, because the output of other circuit is invalid, supply voltage can reduce.Promptly to (n-2), (n-3) ... the voltage of circuit part reduces.In addition to (n+1), (n+2) ... the voltage of circuit part reduces.It should be noted that still (n-2) circuit part voltage, to (n-3), (n-4) ... the voltage of circuit can reduce.In addition, when the supply voltage to (n+1) circuit part does not become, (n+2), (n+3) ... the supply voltage of circuit part can reduce.
In addition, being bonded to each other by n pixel constitutes a piece, and can carry out power supply control to each piece.The piece that is used for an at first specific pixel is known as first, and each piece of back is sequentially numbered.When the circuit of particular pixels appears in n the piece, stop ... the piece power supply, or reduction is to the voltage of its power supply to (n+1), (n+2).In other words, when the power supply of (n+1) piece does not become, can stop to (n+2), (n+3) ... piece power supply, or reduce its supply voltage.In other words, when the power supply of (n-1) piece does not become, can stop to the power supply of (n-2), (n-3) piece or reduce its supply voltage.
Description of drawings
The schematically illustrated peripheral driver circuit that partly constitutes by shift-register circuit and display matrix of Fig. 1;
The schematically illustrated shift register that becomes by the clock inverter configuration in the peripheral driver circuit of Fig. 2;
Fig. 3 is a sequential chart, and the work of the shift register of Fig. 2 is shown;
The schematically illustrated circuit arrangement of Fig. 4 according to embodiment 1;
Fig. 5 schematically illustrates the block scheme of embodiment 1;
Fig. 6 is the sequential chart of embodiment 1;
Fig. 7 is the decoder section of embodiment 1;
Fig. 8 is the power circuit of embodiment 1;
Fig. 9 is the clear circuit of embodiment 1;
Figure 10 is the clock circuit of embodiment 1;
The schematically illustrated circuit arrangement of Figure 11 according to embodiment 2;
Figure 12 is a block scheme, is used to illustrate embodiment 2;
Figure 13 is a sequential chart, is used to show the work of embodiment 2;
Figure 14 is the control circuit of embodiment 2;
A register and an impact damper among the schematically illustrated embodiment 2 of Figure 15;
Figure 16 is a sequential chart, is used to illustrate the operation of embodiments of the invention 3;
The schematically illustrated register of Figure 17, a circuit and an impact damper that is used to select clock at register according to embodiment 3;
The block scheme of the schematically illustrated embodiment 4 of Figure 18;
Figure 19 is a sequential chart, is used to illustrate the operation of embodiment 4;
Figure 20 is according to the control circuit of the register of embodiment 4, a register and an impact damper;
Figure 21 is the shift register that is made of a kind of conducting type TFT according to embodiment 5;
Figure 22 is a sequential chart, is used to illustrate the operation of the shift register of embodiment 5;
The supply voltage on-off circuit of the schematically illustrated shift register that constitutes by a kind of conduction type TFT according to embodiment 5 of Figure 23;
Supply voltage ON-OFF control circuit among the schematically illustrated embodiment 5 of Figure 24;
Figure 25 is a counter and a demoder, and it is distinguished according to embodiment 6;
Power supply termination type counter and the control circuit of the schematically illustrated embodiment 6 of Figure 26;
Figure 27 is a sequential chart, is used to illustrate the operation of the counter circuit of embodiment 6;
The counter and the control circuit of the schematically illustrated low supply voltage type according to embodiment 7 of Figure 28;
The display matrix part of schematically illustrated conventional external drive circuit of Figure 29 and liquid crystal electro-optical;
Shift register that the schematically illustrated clock phase inverter of Figure 30 constitutes and the shift register that sends door;
The shift register that the clock phase inverter of the schematically illustrated CM0S circuit of Figure 31 constitutes;
The schematically illustrated shift register that constitutes by P channel-type TFT and register of Figure 32;
Schematically illustrated conventional external drive circuit of Figure 33 and PEL matrix part;
The signal line drive circuit of the schematically illustrated employing shift register of Figure 34;
The signal line drive circuit of the schematically illustrated employing address decoder of Figure 35;
Figure 36 schematically shows the signal line drive circuit that adopts counter and address decoder;
The scan line driver circuit of the schematically illustrated employing shift register of Figure 37;
Figure 38 schematically shows the basic gate circuit device that is made of a kind of conduction type TFT;
The circuit structure of the schematically illustrated J/K trigger of Figure 39;
The circuit arrangement of schematically illustrated 4 digit counters of Figure 40.
Embodiment
In embodiments of the invention 1-4, adopt the shift register of the circuit that has Fig. 2, represent by the sequential chart of Fig. 3 from the output signal of each register.
Embodiment 1
In embodiment 1, shift register forms to become the piece form, and power supply is added on each piece.In Fig. 4, several registers of shift register 401 are used to form piece 402,403 and 404.Control signal 406,407 and 408 from control circuit 405 is added on each piece.To be known as " shift register piece " below piece 402 grades.
When the input signal 409 that will be shifted appears in the shift register piece 404, be used for providing the control signal 408 of power supply to be input to shift register piece 404.Being used for stopping (interruption) is input to the signal 406 and 407 that power supply is added to each piece in the shift register piece 402 after the displacement input signal is issued, before being sent out, the displacement input signal is input on the shift register piece 403, to stop providing power supply, like this, power consumption can reduce.
In Fig. 5, illustrate and constitute one single situation by 8 registers.Though can measure the input signal that produces control signal, that sets up between control circuit 501 and shift register 502 is used to this control signal of generation in this circuit synchronously.
Signal from clock oscillator 503 is imported on the counter 504 of shift register 502 and control circuit 501.The output of counter 504 becomes control signal 506 through demoder 505.Control signal 506 is imported on the shift register 502.In embodiment 1, control circuit is to be made of the cmos circuit outside the transparent substrates that forms the PEL matrix part thereon.
Fig. 6 is the sequential chart about the control signal 506 of n piece.
According to the clock signal 601 of the clock oscillator 503 of Fig. 5, power supply signal 602, after starting, n shift register piece be used for three signals that initialized reset signal 603 and clock supply signal 604 produce as using control signals 506.
When constituting a piece with 8 registers, power supply constantly 606 rather than produce output cycle 605 during be coupled with, and clock signal was beginning to add constantly in 607 o'clock.606 and 607 is not synchronization constantly, but at a distance of one period 608, like this, output produces after startup really.Behind n block transfer to the (n+1) piece, the power supply that is added on the n piece can stop or interrupt at any time at input signal.In this circuit, add power supply and add clock and operate in constantly 609 and stop.
In Fig. 7, a circuit is shown, it is used for being used to produce the control signal 506 that is added on the 4th when constituting a piece by 8 registers.
The output of the clock oscillator 701 identical with the clock oscillator 503 of Fig. 5 is imported on the binary counter 702.The output of counter 702 is detected by AND circuit 703,704,705, and detected signal by OR circuit 706,707 synchronously to produce control signal.
Select a time cycle with circuit 703, in this cycle, can make the shift register piece in piece, transmit input signal.Select the zero clearing cycle with circuit 704.Select the zero clearing cycles with circuit 705 and with time cycle of transmission input signal.As a result, when with the output of circuit 703,704 and 705 by or circuit 706 is carried out or during logical operation, then produce power supply signal 602.In addition, make with the output of circuit 704 anti-phase by phase inverter 708 to obtain reset signal 603.With the output of circuit 703 and 705 through or the outer reason of circuit 708 and obtain clock signal 604 is provided.
In Fig. 8, be linked on the shift register piece 803 through P channel-type TFT 802 at the power lead 801 of anode.Power supply signal 602 is added to the canopy of P channel TFT 802 and extremely goes up.
Fig. 9 is a clear circuit.The P channel TFT 902 that is used to limit shift register first register (level) 901 storage loopback values links with it and is in operating conditions.Reset signal 603 is added to the canopy of P channel TFT 902 and extremely goes up.In order to limit the loop value output of impact damper 903 is not changed before register work and after the work, when the output of impact damper 903 is in supply voltage following time usually, the drain electrode of P channel TFT 902 is linked on the contact 904, and when the output when impact damper 903 is in ground voltage, is linked on the contact 905.
Figure 10 provides circuit for clock.Clock line 1001 and 1002 is linked on the shift register piece 1005 through P channel TFT 1003 and 1004.The canopy that clock provides signal 604 to be added to P channel-type TFT1003 and 1004 is extremely gone up.
About the shift register of present embodiment, when being used as the peripheral driver circuit of liquid crystal electro-optical, this shift register can make comparisons to power consumption.Should be noted that power consumption in a sign register is that supply voltage square value by each resistor defines out divided by resistance value.
Owing in the register of the traditional devices of Figure 32 three resistors are arranged, and power supply is constantly to offer all registers, and then total power consumption increase will be directly proportional with the total number of register.But in embodiment 1, though three resistance are arranged in single register, power only offers on 8 registers that are used for signal transmission and because four registers that overlap with the control signal of adjacent block do not add power supply on other register.As a result, the power consumption of peripheral driver circuit can obviously reduce.Even after the sum of register increased, power consumption did not change yet.
With next concrete condition is example, works under 20V and resistance when being 300k Ω when the shift register with 640 registers, supposes that its probability of generation of supply voltage output or ground voltage output is 1/2 (50%), and then total power consumption will reduce to 24mW.On the contrary, the power consumption in traditional devices is 1280mW.
Embodiment 2
In embodiment 2, each register has control circuit and the outside signal specific that provides is provided.
In Figure 11, in each register of shift register 1101, adopt control circuit 1102 to detect input signal 1103, like this, control signal 1104 has promptly produced.Specifically, after input signal arrives, because pulsewidth can not be guaranteed by power supply, before half of the fundamental clock before input signal arrives, shift register work, and power supply just in time stops after the one-period that is made as duty is exported or interrupts.That is, in Figure 12 A, the output 1203 of n piece 1202 of shift register 1201 be imported in the control circuit 1204 (n+1) control circuit and (n+2) on the control circuit 1206.
After the output 1203 of n register 1202 started, (n+1) control circuit 1205 produced a control signal 1208, in order to power supply is added on (n+1) register 1207.In addition, after the output 1203 of n register 1202 started, (n-2) control circuit 1206 produced control signals 1210, power supply was added on (n-2) register 1209 in order to stopping.
The signal that Figure 12 B illustrates when these states change end and next clock pulse arrival transmits.For the sampling thief 105 even the unlikely maloperation when the power supply on being added to register begins or stops that make Fig. 1, the output of the impact damper 104 of Fig. 1 should not change.The result, output at the impact damper 104 that can obtain Fig. 1 really, and in the cycle when non-transformer is added on the shift register 1101 of Figure 11, consider that the signal that enters in the shift register 1101 is uncertain situation, in embodiment 2, be used as the input of next register with the output of impact damper.
According to above-mentioned explanation, the sequential of single register shown in Figure 13.N the supply voltage 1304 of adjusting input 1303 produces from the impact damper output 1302 of fundamental clock 1301 and (n-1) register.
Though, the work period of a register of shift register is only grown 1.5 times than the one-period of fundamental clock, because control signal is later than the rise time and/or the fall time of its clock, its cycle signal of being longer than 2 times of fundamental clocks is as the input signal of n register of shift register and produce, and pulsewidth is set to equal the one-period of fundamental clock definitely.That is to say, export the supply voltage 1308 that produces n adjustment input 1307 1306 from the inversion signal 1305 of fundamental clock and the impact damper of (n+1) register.Subsequently, input is adjusted signal 1303 and 1307 warps or logical operation and is produced this adjustment signal 1309 with effective high state.
Because the impact damper output signal 1302 of (n-1) register is later than the fundamental clock 1301 that will change with this understanding, then in the cycle 1310 of adjusting signal 1309, produce wrong operation signal.In the case, impact damper output signal 1302 is shielded by the clock 1311 of long 1.5 times of its period ratio fundamental clock, and like this, operation can correctly be carried out.Can produce the impact damper output 1312 of n register by these signals.Power supply signal 1313 in n register makes the moment before the half period that is provided at the fundamental clock that input signal arrives of power supply, the change of caused input signal width because element is delayed time to avoid out.
As control circuit, the circuit of this no logical circuit needs, because various states can be preserved or keep to this control circuit, and must work under low-power consumption.In embodiment 2, preferably construct a kind of circuit that mainly forms by capacitor arrangements, though its characteristic will degenerate, circuit structure is simple.
Figure 14 illustrates a kind of control circuit.The resistance of label 1406 protection power supplys.When electric capacity 1401 is in Charging state, then interrupt power supply, and produce a control signal output 1402, so that power supply is added to register in discharge condition to register.
Behind the power connection of entire circuit, P channel TFT 1403 is made as initial state with control circuit.That is, before input signal was input to shift register, the ground voltage signal was added to the grid of P channel TFT 1403, so that electric capacity 1401 is charged.
In order to ensure obtain input signal in n control circuit, in the moment of input signal arrival (n-1) register, n register is activated, and subsequently, obtains input signal when follow-up clock changes.Therefore, the output of the impact damper of (n-1) register is used as the input to the P channel TFT 1404 canopy utmost points.As a result, when the impact damper of (n-1) register was output as ground voltage, electric capacity 1401 discharges were used for power supply is added on n the register to produce a signal.
Similarly, in n control circuit, when input signal arrived (n+2) register, n register entered the state that no enabling signal is exported, and like this, the providing of power supply is stopped or interrupts.Thereby the impact damper output of (n+2) register is applied the input to P channel TFT 1405 grids.As a result, when the impact damper output of (n+2) register becomes ground voltage, electric capacity 1401 chargings, and termination is to the power supply of n register.
Figure 15 illustrates n register and impact damper.In signal adjustment member 1501, fundamental clock is added to the grid of P channel TFT 1502, the clock that its period ratio fundamental clock that is used to shield is long 1.5 times is added to the grid of P channel TFT 1503, and the output of the impact damper of (n-1) register is added to the grid of P channel TFT 1504; Like this, the sloping portion of the impact damper of n register output, promptly the signal 1303 of Figure 13 is produced.
The clock that is produced by the anti-phase back of fundamental clock is added to the canopy utmost point of P channel TFT 1505, its cycle that is used to shield clock of being longer than 1.5 times of fundamental clocks is added to the canopy utmost point of P channel TFT 1506, and the output of the impact damper of (n+1) register is added to the grid of P channel TFT 1507, like this, produce the rising part of n register, i.e. the signal 1307 of Figure 13.As a result, the output of signal adjustment member 1501 becomes the signal 1309 of Figure 13.Roughlly speaking, because P channel TFT 1504 and 1507 is in off state, the no current on the resistance 1508 flows through, and control signal is not input to the signal adjustment member.
Traditionally, all registers of shift register are all worked.But according to present embodiment, control signal is added on the grid of TFT 1509,1510 and 1511, and stops power supply in the unwanted cycle, to reduce power consumption in whole shift register.
The clock that its period ratio fundamental clock is long 1.5 times is added to the grid of P channel TFT 1512, and the output of signal adjustment member 1501 is added to the grid of TFT 1513.Like this, when not setting up, produce the impact damper input of one-period in the storage loop.
1.5 the inversion signal of the clock of double-length is added to the grid of TFT 1514, the output that constitutes the phase inverter 1516 in storage loop is added to the grid of TFT 1515.
Roughlly speaking, TFT 1515 and resistance 1517 constitute a phase inverter.The storage loop can be made of this phase inverter and another phase inverter that is configured to by P channel TFT 1518 and resistance 1519.P channel TFT 1520 and resistance 1521 constitute an impact damper.
TFT 1522 is used for limiting in each clear operation each output of shift register, and prevents that the charged state of the capacitor of control circuit from can not implement.When the current capacity of P channel TFT is big, be used to provide the P channel TFT 1509,1510 and 1511 of power supply to combine each other.
Need not guarantee that under the situation of pwm input signal, control signal and fundamental clock are synchronous, and in embodiment 2, power supply is added on the single register only one-period.
In the shift register of present embodiment, the external drive circuit that is used as liquid crystal electro-optical when this shift register can be made comparisons to power consumption.The consumed power of signal resistor is defined divided by resistance value by the supply voltage square value of each resistor.
Because in the register of the traditional devices of Figure 32 three resistance are arranged, power supply constantly is added on all registers, and the increase of total power consumption is directly proportional with the total number of register.But in the peripheral driver circuit shown in the embodiment 2, though adopted three resistance in a register, power supply only constantly is added on three registers, and is not added on other register.As a result, power consumption obviously reduces.Even after the total number of register increased, power consumption did not still have change.
As instantiation, when the shift register with 640 registers is worked under 20V, and resistance supposes that the probability that produces supply voltage output or ground voltage output is 1/2 (50%) when being 300k Ω, and then total power consumption can be kept to 6mW.On the contrary, the power of traditional devices is 1280mW.
Embodiment 3
In embodiment 3, in each register, adopt a control circuit.In embodiment 3, the circuit that adopts the shielding clock to use in circuit part in this circuit part, adopts the clock in 1.5 double-length cycles among the embodiment 2 to prevent maloperation.As a result, the signal Processing of embodiment 3 is similar to the situation of embodiment 2 to control circuit.
In Figure 16, a sequential chart is shown, be used to explain the work of single register.In the signal adjustment member, the supply voltage 1604 of n input 1603 is exported generation in 1602 with the impact damper of (n-1) register from the inversion clock 1601 of fundamental clock.
As the signal that forms the storage loop, need the regularly clock 1605 of preface.But because n control signal becomes signal 1606, the storage loop is the moment after startup 1607 formation just in time, and like this, n input can not be accepted.So clock 1605 controlled signals 1606 and 1608 shieldings like this, produce this loop and form signal 1609.The output 1610 of n impact damper is formed by these signals.
Figure 17 illustrates n register.About signal adjustment member 1701, fundamental clock is added to the grid of P channel TFT 1702, and the impact damper output of (n-1) register is added to the grid of P channel TFT 1703, and like this, after n register is activated (after the initialization), signal is set.
The grid of the circuit 1704 that is used to select clock by n control signal being added to P channel TFT 1705, (n+1) control signal is added to the grid of P channel TFT 1706 and the grid that the inversion clock of fundamental clock is added to P channel TFT 1707 is produced an output 1708.Output signal 1708 anti-phase backs produce a signal that is used to form the storage loop.
Circuit 1709 with 1710 with embodiment 2 in circuit identical.P channel TFT 1711,1712,1713,1714 and 1715 is used to provide power supply, and P channel TFT 1716 is used to carry out clear operation.
In the shift register of present embodiment, when being used as the peripheral driver circuit of liquid crystal optical device, this shift register can make comparison to power consumption.Power consumption on sign register is defined divided by resistance value by the supply voltage square value of each resistance.
Because in the register of the traditional devices of Figure 32 three resistance are arranged, power supply constantly is added on all registers, and the increase of total power consumption is directly proportional with the total number of register.But in the peripheral driver circuit shown in the embodiment 3, though adopted five resistance in a register, power supply only constantly is added on three registers, and is not added on other register.As a result, power consumption obviously reduces.Even after the total number of register increased, power consumption did not still have change.
As instantiation, when the shift register with 640 registers is worked under 20V, and resistance supposes that the probability that produces supply voltage output or ground voltage output is 1/2 (50%) when being 300k Ω, and then total power consumption can be kept to 10mW.On the contrary, the power of traditional devices is 1280mW.
Embodiment 4
In embodiment 4, during two cycles that equal fundamental clock, provide power supply.
In embodiment 2 and 3, in cycle, provide power supply than long 1.5 times of fundamental clock.In contrast, because this power operation is to carry out in two cycles of the fundamental clock of embodiment 4, then entire circuit can be simplified.
Figure 18 A illustrates signal flow.The structure no change of shift register 1801, impact damper 1802 and control circuit 1803.When the output of n register makes itself and clock synchronization by effective output of effective output 1804 of (n-1) register and effectively the time, be changed with the output 1806 of n the corresponding impact damper 1805 of impact damper.
When impact damper output 1806 is imported into (n+2) control circuit 1807 and (n-2) control circuit 1808, the output of n impact damper becomes effectively, in (n+2) control circuit 1807, produce power supply signal 1809, and in (n-2) control circuit 1808, produce power supply termination signal 1810.
Figure 18 B illustrates half fundamental clock another signal flow after the cycle that begins from the state of Figure 18 A.In embodiment 4, the output of n register is used as the input of (n+1) register, and output that need not n impact damper.
Figure 19 illustrates sequential chart.According to clock 1901, obtain input signal, and clocked inverter 1902 constitutes the storage loop.According to control signal 1903, power supply only adds in two cycles of fundamental clock.
The output 1904 usefulness solid lines of n register are represented.Because this signal is what to obtain in the cycle 1905 and 1906 of (n+1) register, picked up signal no longer then at dotted line 1904 places.When being input at n register after signal 1907 in the impact damper is used, impact damper output 1908 maloperation can not occur.
In Figure 20, the circuit diagram of embodiment 4 is shown.The output of n register 2001 is used as the input to the impact damper 2002 of n and (n+1) register.The output of impact damper 2002 becomes the input to (n+2) and (n-2) control circuit 2003, thereby produces a control signal.Shift register disposes like this, like this, is used to provide the P channel TFT 2004,2005 and 2006 of power supply to be connected in series to each phase inverter of shift register shown in Figure 32.Constitute the P channel TFT of phase inverter
2007,2008 and 2009 source electrode can combine on a point, and is linked to through single P channel TFT and is used for control power supply on the power supply.
The related circuit of buffer circuits 2002 and control circuit 2003 and embodiment 2 mutually.That is, corresponding to the input of the grid of the p channel TFT 2011 that makes n control circuit capacitor 2010 discharge with the output of (n-2) impact damper, and the input that the grid that makes P channel TFT 2012 is discharged is corresponding with the output of (n+2) impact damper. P channel TFT 2014 and 2014 is analog switches of clock synchronization, and P channel TFT 2015 and 2016 is used to carry out zero clearing.
As the shift register of present embodiment, when being used as the external drive circuit of liquid crystal electro-optical, this shift register can make comparisons to power consumption.The consumed power of sign register is defined divided by resistance value by the supply voltage square value of each resistor.
Because in the register of the traditional devices of Figure 32 three resistance are arranged, power supply constantly is added on all registers, so the increase of total power consumption is directly proportional with the total number of register.But in the peripheral driver circuit of embodiment 4, though adopted three resistance in a register, power supply only constantly is added on four registers, and is not added on other register.As a result, power consumption obviously reduces.Even after the total number of register increased, power consumption did not still have change.
As instantiation, when the shift register with 640 registers is worked under 20V, and resistance is when being 300k Ω, supposes to produce power supply to press the probability of output or ground voltage output be 1/2 (50%), and then total power consumption can be kept to 8mW.On the contrary, the power of traditional devices is 1280mW.
In according to embodiments of the invention 1-4, power supply only is added on the required register that will work, and like this, the power consumption in the whole peripheral driver circuit of liquid crystal electro-optical can reduce widely.Even when adopting the shift register of high power consumption, also can be whole peripheral driver circuit and realize very low power consumption.The increase that can prevent power consumption like this is associated with the increase of register sum.
In embodiment 5-7, more such circuit structures are provided, after pixel was specifically determined, supply voltage promptly was set to required value.This can be another kind of circuit arrangement also, is used to reduce the supply voltage of the circuit part that does not have effect.
Embodiment 5
In embodiment 5, adopt shift-register circuit to constitute peripheral driver circuit, and in this case, circuit is by adopting a kind of conductivity type TFT, promptly P channel TFT and resistor are realized.Figure 21 illustrates shift-register circuit.In this embodiment, shift-register circuit register (level) 2101 is with corresponding by 2102,2103,2104 and two circuit that analog switch 2105 and 2106 is configured to of three phase inverters.Impact damper 2107 makes analog switch carry out ON/OFF work.
In Figure 22, the solid line representative can drive the supply voltage of liquid crystal, and dotted line represents to realize the supply voltage of low-power consumption.Consider the change in voltage scope of the vision signal that is used to drive liquid crystal, in impact damper, need the supply voltage of about 20V to come the actuating analog switch.Thereby the impact damper output 2201 that is used for the analog switch that ON/OFF is made of the P channel TFT becomes the supply voltage of about 20V usually, and when sampling, becomes ground voltage.As a result, ground voltage need be generally and the wave mode 2202 that is about 20V voltage when sampling is imported as impact damper.
Very obvious, the shift-register circuit that is used to produce the impact damper input with the sampling time sequence displacement as input signal.Therefore, when in shift-register circuit, producing sampling time sequence, when promptly in n shift-register circuit input signal being arranged, suppose that the supply voltage at n register is about 20V, liquid crystal can drive through impact damper and the vision signal as analog switch.When no input signal, the supply voltage of shift-register circuit can be lowered in the certain limit, can misoperation at this scope internal shift register circuit.Always do not using owing to be used to drive the supply voltage of liquid crystal, and supply voltage can drop in this circuit arrangement in the unlikely anti-phase scope of logic, thereby power consumption can reduce.
Figure 23 illustrates a kind of circuit arrangement, and it is used for can driving the supply voltage of liquid crystal and realizing that the supply voltage of low-power consumption offers a register 2301 of shift-register circuit.P channel TFT 2302 enters conducting state, and P channel TFT 2303 also enters conducting state, and supply voltage (high power supply voltage) that can drive liquid crystal and another supply voltage (low supply voltage) that can realize low-power consumption can be provided like this.
Figure 24 illustrates the circuit that is used to control power circuit.In Figure 24, a kind of corresponding control circuit of n register 2401 of and shift-register circuit is shown, and the method for extracting control control circuit working signal is shown.
As follows with the working condition of n the corresponding control circuit capacitor 2402 of register of shift-register circuit.When electric capacity 2402 is charged to the voltage that can drive liquid crystal, can realize that the supply voltage of low-power consumption is added on n the register of shift-register circuit.
On the contrary, when this capacitor discharge during to voltage closely, the supply voltage that can drive liquid crystal is added on n the register of shift-register circuit.
The working condition of control circuit is as follows: at first conducting of P channel TFT 2403, and so that capacitor 2402 is charged on the voltage that can drive liquid crystal.After the charging, TFT 2403 turn-offs.In original state, provide the supply voltage that to realize low-power consumption.The output of (n-1) register 2404 of shift-register circuit is linked on the grid of P channel TFT 2405 through impact damper.As a result, when input signal arrived (n-1) register of shift-register circuit, capacitor was discharged on the voltage that is bordering on ground voltage.Voltage on the capacitor becomes the supply voltage control signal that can drive liquid crystal with clock synchronization by P channel TFT 2406.Subsequently, this control signal becomes another supply voltage control signal that can realize low-power consumption through phase inverter 2407.As a result, after the capacitor with n the corresponding control circuit of register of shift register was discharged, the supply voltage that can drive liquid crystal was added on n the register of shift-register circuit, like this, stopped to realize the providing of power supply of low-power consumption.When the supply voltage of shift register when low, the output of shift register can make control circuit mistakenly with high power supply voltage work.For fear of, the impact damper output that employing can be used under the supply voltage that drives liquid crystal continuously.
In addition, because the time-delay of phase inverter, power control signal might make P channel TFT 2302 and 2303 conductings simultaneously, thereby power supply is by short circuit.Thereby the supply voltage control signal of control liquid crystal can make P channel TFT 2302 postpone to enter the state of conducting because of resistance 2408 distortions.Can avoid power circuit short like this.
Also have, the output of (n-1) register 2409 of shift-register circuit is linked to the canopy utmost point of P channel TFT 2410 through impact damper.When input signal arrived (n+1) register of shift-register circuit, capacitor was charged on the supply voltage that can drive liquid crystal.As a result, can realize that the supply voltage of low-power consumption is added on n the register of shift-register circuit, like this, can stop to provide the power supply that can drive liquid crystal.
With this circuit arrangement, only when the analog switch conducting was used to sample, supply voltage can be set to required value.In other cases, supply voltage is set on the voltage that can realize low-power consumption, can realize the low-power consumption of entire circuit like this.
About the peripheral driver circuit of present embodiment, can make comparisons to power consumption.Define divided by resistance value at the square value of the power consumption on the sign register by the supply voltage on each resistor.The 20V voltage that can drive liquid crystal is added on the circuit shown in Figure 40 continuously, in a register of shift-register circuit three resistance is arranged, and its resistance is 300k Ω, supposes to produce probability that power supply presses output or ground voltage output not 1/2 (50%).When shift-register circuit is to be formed and when removing impact damper, power consumption is 1280mW by 640 register configuration.In this embodiment, can obtain following result.Promptly, suppose that liquid crystal drive voltage is 20V, the voltage of low-power dissipation power supply is 5V, adopt 4 resistors in the register, and resistance value is 300k Ω, the supply voltage that can drive liquid crystal only is added on two registers of the shift-register circuit that is made of 640 registers, realizes that the supply voltage of low-power consumption is added on all the other 638 registers of shift-register circuit.According to this supposition, total power consumption 111mW.Thereby power consumption is lowered in the present embodiment.
Embodiment 6
In embodiment 6, a kind of circuit arrangement is shown, this device only is added to the part of the pixel after specific with power supply, and ends power supply is added to not by the part of specific pixel.In this embodiment, sort circuit is that the supposition pixel is specific by adopting decoder circuit sum counter circuit.
The output of counter circuit (comprise anti-phase after output) is used for a specific signal that pixel is used by the decoder circuit that the door configuration by Figure 38 forms thereby produce.When decoder circuit possessed buffer function, because power consumption reduces, the power that is added to counter circuit reduced.The part that counter circuit is divided into the part that is used for particular pixels and is not used for particular pixels with the circuit arrangement of Figure 40 is impossible, and therefore, this counter circuit can be divided again.
Can not must adopt the counter circuit of Figure 25 by single counter generation and signal wire or sweep trace corresponding address with less figure place.The number of required counter circuit is ready to, and these counter circuits are sequentially driven and produce the local address, thereby makes pixel by specific.As a result, can stop to provide power supply to the counter that need not work.In this figure, label 2501 is represented a PEL matrix; 2502 is the counter circuit after dividing again; 2503 is decoder circuit; 2504 is control circuit.
Figure 26 illustrates counter circuit, decoder circuit and the control circuit that divides again.When producing the pulsation carry in (n-1) counter circuit 2601, power supply begins to be added on n the counter circuit 2602.When its counting work of (n+1) counter circuit 2603 beginnings, stop power supply being added on n the counter circuit.
Control circuit is identical with the control circuit of embodiment 5, be by a kind of conductivity type TFT that is used for initial setting (being P channel TFT 2604), be used for to capacitor discharge with the P channel TFT 2605 that starts the power supply power supply, be used for the electric capacity charging is formed with P channel TFT 2606 of stopping power supply and electric capacity 2607 configurations that are used to store.When power supply began to provide, it is unstable that the output valve of n counter circuit becomes.As a result, when the pulsation carry that produces (n-1) counter circuit and power supply begin to provide, carry out clear operation.The circuit that is used to produce reset signal is made of P channel TFT 2608.
Be used to provide the circuit of power supply to realize by the P channel TFT is connected between the source electrode of P channel-type TFT of Figure 22 and the power circuit, and power supply the control that is subjected to this P channel TFT is provided.In Figure 26, Chuan Lian P channel TFT combines and is designated as P channel TFT 2609 in addition.To allow signal to be added on n the counter circuit 2602 by P channel TFT 2609.The output of decoder circuit 2610 that is used to detect the minimum output valve of (n+1) counter circuit by use stops power supply being fed to n counter circuit.
Figure 27 illustrates the sequential chart of n counter circuit.Power supply 2701 rigidly connect logical after, the output 2704 that produces reset signal 2703, the n counter circuits of n counter circuit by the pulsation carry 2702 of (n-1) counter circuit is input to and is used to produce a decoded signal 2705 on the decoder circuit.Next clock pulse during according to the output of pulsation carry stops to provide power supply to n counter circuit.
At the peripheral driver circuit of present embodiment, can make comparisons to power consumption.Define divided by resistance value at the square value of the power consumption on the sign register by the supply voltage on each resistor.When 640 pixels produce address signal, need 10 digit counters, a position of counter is corresponding with a J/K trigger, and a J/K trigger needs 10 doors.Like this, only the J/K trigger is exactly 100 with the number of resistors that power supply is linked to ground.Need 16 doors in addition, and goalkeeper's power ground just needs 1 resistance.As a result, the resistance with power ground adds up to 116.Resistance value is chosen as 300k Ω, and supply voltage 20V supposes that the probability that produces supply voltage output or ground voltage output is 1/2 (50%).Except the decoder circuit that also possesses pooling feature, power consumption is 77mW.
It is on the contrary, as follows: because the 4 irrelevant digit counters of number of picture elements that used in order can think that 4 digit counters are operate as normal according to the power consumption of present embodiment.In other words, 4 J/K triggers are arranged, and in each J/K trigger, 10 resistance are arranged.Owing to need 8 doors in each J/K trigger, the resistance sum of power ground will be 48.Supply voltage is elected 20V as, and resistance value is 300k Ω, supposes that the probability that produces supply voltage output or ground voltage output is 1/2 (50%).Suppose that thus power consumption is 32mW except that the decoder circuit with buffer function.
In the peripheral driver circuit that only has decoder circuit sum counter circuit, after the number of sweep trace or signal wire increased, total power consumption increased with arithmetic form.But in the present embodiment, total power consumption reduces because of circuit structure.
Embodiment 7
In embodiment 7, a kind of circuit arrangement is shown, when pixel by after specific, supply voltage promptly is set to required value.This is also corresponding a kind of circuit that is used to reduce the supply voltage that not have circuit part that acts on.Similar to embodiment 6, in the present embodiment, this peripheral driver circuit is assumed that its pixel comes specific by adopting decoder circuit sum counter circuit.Counter circuit has 6 outputs.
Figure 28 illustrates a circuit arrangement.Control circuit 2801 has the circuit arrangement similar with embodiment 5.The pulse carry of (n-1) counter circuit 2803 is used as a signal, to start the power supply to n counter circuit 2802.The output of decoder circuit 2805 that is used to detect the minimum output valve of (n+1) counter circuit 2804 is taken as a signal, stops the power supply to n counter circuit.The signal that is used to control the supply voltage that can realize low-power consumption is used as the permission signal of n counter circuit.In cleared condition, n counter circuit waits to allow signal sequence ground to become effectively.As a result, even after supply voltage changes, need not carry out zero clearing.
At the peripheral driver circuit of present embodiment, can make comparisons to power consumption.In the power consumption on the single register is that square value by the supply voltage on each resistor defines divided by resistance value.When 640 pixels produce address signal, need 10 digit counters, a position of counter is corresponding with a J/K trigger, and a J/K trigger needs 10 doors.Like this, only the J/K trigger is exactly 100 with the number of resistors that power supply is linked to ground.Need 16 doors in addition, and goalkeeper's power ground just needs 1 resistance.As a result, the resistance with power ground adds up to 116.Resistance value is chosen as 300k Ω, and supply voltage 20V supposes that the probability that produces supply voltage output or ground voltage output is 1/2 (50%).Except the decoder circuit that also possesses pooling feature, power consumption is 77mW.
On the contrary, the power consumption according to present embodiment is as follows: 640 pixels need 11 6 digit counters.The 20V voltage that can drive liquid crystal is added on 6 the counter, and can provide the 5V voltage of low-power consumption to be added on remaining 10 6 digit counter.In 6 counter circuit, 6 J/K triggers are arranged, and in each J/K trigger, 10 resistance are arranged.Owing to need 12 doors in each J/K trigger, the resistance sum of power ground will be 72.Suppose that resistance value is 300k Ω, the probability that produces supply voltage output or ground voltage output is 1/2 (50%).Suppose that thus power consumption is 62mW except that the decoder circuit with buffer function.
As illustrated in embodiment 5-7, install in a circuit according to the invention, power supply only is added to peripheral driver circuit and wants driven circuit part, and like this, the power consumption of the whole peripheral driver circuit in liquid crystal electro-optical can reduce.In addition, high voltage is added on the required part of peripheral driver circuit, and low-voltage is added on the unwanted part.Like this, the power consumption of the whole peripheral driver circuit of liquid crystal electro-optical can reduce.

Claims (23)

1. a liquid crystal display device has active matrix circuit, signal line drive circuit and scan line driver circuit, and each in described signal line drive circuit and the described scan line driver circuit all comprises:
Shift-register circuit has a plurality of registers that are connected in series; With
Power circuit has a plurality of control circuits, and described a plurality of control circuits are connected to each in the described register, provides electric power with in described register each;
Wherein, when extremely the input signal of described shift-register circuit is maintained in n the register of described shift-register circuit, the power supply of the register except that the n of described shift-register circuit, (n-1) individual and (n+1) individual register is stopped, wherein n is an integer, and n 〉=1.
2. liquid crystal display device as claimed in claim 1, each in the wherein said register comprise a P channel-type thin film transistor (TFT) and a resistor.
3. liquid crystal display device as claimed in claim 1, wherein said power circuit is according to the power supply of the output of described register control to described register.
4. liquid crystal display device as claimed in claim 1, each in the wherein said control circuit comprise a P channel-type thin film transistor (TFT), a resistor and a capacitor.
5. liquid crystal display device as claimed in claim 1, the consumed power of wherein said power circuit is equal to or less than the consumed power of described shift-register circuit.
6. a liquid crystal display device has active matrix circuit, signal line drive circuit and scan line driver circuit, and each in described signal line drive circuit and the described scan line driver circuit all comprises:
Shift-register circuit has a plurality of registers that are connected in series; With
Power circuit has a plurality of control circuits, and described a plurality of control circuits are connected to each in the described register, provides electric power with in described register each;
Wherein, when extremely the input signal of described shift-register circuit is maintained in n the register of described shift-register circuit, the power supply of the register except that the n of described shift-register circuit, (n-1) individual and (n+1) individual register is stopped, wherein n is an integer, and n 〉=1, and
Wherein, half fundamental clock of each in the described register before described input signal arrives was activated before the cycle.
7. liquid crystal display device as claimed in claim 6, each in the wherein said register comprise a P channel-type thin film transistor (TFT) and a resistor.
8. liquid crystal display device as claimed in claim 6, wherein said power circuit is according to the power supply of the output of described register control to described register.
9. liquid crystal display device as claimed in claim 6, each in the wherein said control circuit comprise a P channel-type thin film transistor (TFT), a resistor and a capacitor.
10. liquid crystal display device as claimed in claim 6, the consumed power of wherein said power circuit is equal to or less than the consumed power of described shift-register circuit.
11. the liquid crystal display device with active matrix circuit and driving circuit, described driving circuit comprises:
Shift-register circuit has a plurality of registers that are connected in series; With
Power circuit has a plurality of control circuits, and described a plurality of control circuits are connected to each in the described register, provides electric power with in described register each;
Wherein, when extremely the input signal of described shift-register circuit is maintained in n the register of described shift-register circuit, the power supply of the register except that the n of described shift-register circuit, (n-1) individual and (n+1) individual register is stopped, wherein n is an integer, and n 〉=1.
12. as the liquid crystal display device of claim 11, each in the wherein said register comprises a P channel-type thin film transistor (TFT) and a resistor.
13. as the liquid crystal display device of claim 11, wherein said power circuit is according to the power supply of the output of described register control to described register.
14. as the liquid crystal display device of claim 11, each in the wherein said control circuit comprises a P channel-type thin film transistor (TFT), a resistor and a capacitor.
15. as the liquid crystal display device of claim 11, the consumed power of wherein said power circuit is equal to or less than the consumed power of described shift-register circuit.
16. as the liquid crystal display device of claim 11, wherein said active matrix circuit and described drive circuit are formed on the substrate.
17. the liquid crystal display device with active matrix circuit and driving circuit, described driving circuit comprises:
Shift-register circuit has a plurality of registers that are connected in series; With
Power circuit has a plurality of control circuits, and described a plurality of control circuits are connected to each in the described register, provides electric power with in described register each;
Wherein, when extremely the input signal of described shift-register circuit is maintained in n the register of described shift-register circuit, the power supply of the register except that the n of described shift-register circuit, (n-1) individual and (n+1) individual register is stopped, wherein n is an integer, and n 〉=1, and
Wherein, half fundamental clock of each in the described register before described input signal arrives was activated before the cycle.
18. as the liquid crystal display device of claim 17, each in the wherein said register comprises a P channel-type thin film transistor (TFT) and a resistor.
19. as the liquid crystal display device of claim 17, wherein said power circuit is according to the power supply of the output of described register control to described register.
20. as the liquid crystal display device of claim 17, each in the wherein said control circuit comprises a P channel-type thin film transistor (TFT), a resistor and a capacitor.
21. as the liquid crystal display device of claim 17, the consumed power of wherein said power circuit is equal to or less than the consumed power of described shift-register circuit.
22. as the liquid crystal display device of claim 17, wherein said active matrix circuit and described drive circuit are formed on the substrate.
23. the driving method of the shift register in the driving circuit of a liquid crystal display device, described shift register comprise a plurality of registers that are connected in series, described driving method may further comprise the steps:
With input signal from (n-1) individual register shift to n register;
Respond described input signal, send output signal to control circuit from described n register;
Respond the described output of described n register, produce first control signal and second control signal by described control circuit;
Be input to (n-2) individual register with one in described first and second control signals, the power supply to described (n-2) individual register is stopped thus; And
In described first and second control signals another is input to (n+1) individual register, and the power supply to described (n+1) individual register is begun thus, and wherein n is an integer, and n 〉=1.
CN2007100840894A 1994-08-16 1995-08-16 Peripheral driver circuit of liquid crystal electro-optical device Expired - Lifetime CN101004899B (en)

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JP21425894 1994-08-16
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JP27056494 1994-10-07

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Publication number Priority date Publication date Assignee Title
CN101004899B (en) * 1994-08-16 2011-09-28 株式会社半导体能源研究所 Peripheral driver circuit of liquid crystal electro-optical device
JP2007233450A (en) * 2006-02-27 2007-09-13 Mitsubishi Electric Corp Image composition device

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US4963860A (en) * 1988-02-01 1990-10-16 General Electric Company Integrated matrix display circuitry
US5128974A (en) * 1989-11-02 1992-07-07 Sony Corporation Shift register apparatus with improved clock supply
US5250931A (en) * 1988-05-17 1993-10-05 Seiko Epson Corporation Active matrix panel having display and driver TFT's on the same substrate
CN1920936A (en) * 1994-08-16 2007-02-28 株式会社半导体能源研究所 Peripheral driver circuit of liquid crystal electro-optical device

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CN1920936A (en) * 1994-08-16 2007-02-28 株式会社半导体能源研究所 Peripheral driver circuit of liquid crystal electro-optical device

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