CN101027772A - 在相同工艺流程内被独立访问的双栅和三栅晶体管 - Google Patents

在相同工艺流程内被独立访问的双栅和三栅晶体管 Download PDF

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CN101027772A
CN101027772A CNA2005800323149A CN200580032314A CN101027772A CN 101027772 A CN101027772 A CN 101027772A CN A2005800323149 A CNA2005800323149 A CN A2005800323149A CN 200580032314 A CN200580032314 A CN 200580032314A CN 101027772 A CN101027772 A CN 101027772A
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B·多伊尔
P·常
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Abstract

描述了一种在同一工艺流程中制造的独立访问的双栅和三栅晶体管。一绝缘塞从I-栅器件而不是三栅器件的半导体主体上去除。这例如能够允许金属化以形成在三栅器件的三个侧面上,并允许用于I-栅器件的独立栅极。

Description

在相同工艺流程内被独立访问的双栅和三栅晶体管
发明领域
本发明涉及半导体加工工艺领域。
现有技术和相关领域
半导体加工工艺中一个新近的发展是独立受控的双栅(I-栅)晶体管。该晶体管具有被放置在一沟道的相对两侧的两个栅极,每个栅极都受到独立控制。独立的栅极控制提供了某些独特的晶体管特性,并能够实现例如单体、动态随机存取存储器(DRAM)单元。
半导体加工工艺中的另一个新近的发展是三栅晶体管。此处,在沟道区的三个侧面上各形成一栅极。该晶体管特别是在与高k值绝缘体和金属栅一起使用的情况下,能够大幅改进性能。
现已提出了若干I-栅结构。此种和其他相关技术在如下文献中有所描述:C.Kuo跟随M.Chan发表在1994年1月的Electron Device Letters上之后而在2002年12月在IEDM上发表的;C.Kuo等人发表在2002年12月的IEDM上的“AHypothetical Construction of the Double Gate Floating Body Cell”;T.Ohsawa等人发表在2002年11月的IEEE Journal of Solid-State Circuits.第11期卷37;David M.Fried等人发表在2004年4月的IEEE Electron Device Letters.第4期卷25的“High-Performance P-Type Independent-Gate FinFETs”以及David M.Fried等人发表在2003年9月的IEEE Electron Device Letters.第9期卷24上的“ImprovedIndependent Gate N-Type FinFET Fabrication and Characterization”。
三栅极结构在例如公开号为U.S.2004-0036127-A1的美国专利中有所描述。
附图简述
图1A是包括带有覆盖其上的绝缘构件的两个硅主体的衬底的立体图。
图1B是沿图1A中的线段1B-1B切开的图1的结构的横截面正视图。
图2A示出了图案化牺牲层之后的图1的结构。
图2B是沿图2A中的线段2B-2B切开的图2的结构的横截面正视图。
图3是沉积了层间电介质(ILD)之后的图2A的结构的立体图。
图4A是平坦化之后的图2A的结构的立体图。
图4B是沿图4A中的线段4B-4B切开的横截面正视图。
图5是覆盖了其上制造I-栅晶体管的部分衬底之后的图4的结构的立体图。
图6A是蚀刻步骤之后的图5的结构的立体图。
图6B是沿图6A中的线段6B-6B切开的图6的结构的横截面正视图。
图7A是去除了图案化的牺牲层之后的图6A的结构的立体图。
图7B是沿图7A中的线段7B-7B切开的图7的结构的横截面正视图。
图8是形成了绝缘层和金属层之后的图7A的结构的立体图。
图9A是平坦化金属层之后的图8的结构的立体图。
图9B是去除了ILD的图9A的结构的横截面正视图。
详细描述
在以下描述中记述了一种在公共衬底上被独立访问的双栅(I-栅)晶体管和三栅晶体管的制造。将阐明诸如特定材料等多个具体细节以提供对本发明的透彻理解。本领域普通技术人员显而易见的是无需这些具体细节也能实践本发明。在其他实例中,不会详细描述已知的加工步骤以免淡化本发明的主题。例如,对已知的清洗步骤以及在集成电路制造中经常使用的某些保护层将不作描述。
如下的方法描述了在单个工艺流程中I-栅晶体管和三栅晶体管的同时形成。虽然仅示出了单个I-栅晶体管和单个三栅晶体管的制造,但是本领域普通技术人员显而易见的是在典型的集成电路中可以同时制造多个此类晶体管。此外,可以在集成电路中需要的任何地方制造I-栅和三栅晶体管。于是,诸如缓冲器等单个电路也可以同时具有I-栅和三栅晶体管。在某些情况下,例如在DRAM中,可以制造仅使用I栅晶体管的存储器单元阵列并将其连接至同时使用I-栅和三栅晶体管的外围电路。使用I-栅存储器单元的存储器在由于2004年3月31日提交的题为“Memorywith Split-Gate Devices and Method of Fabrication”且序列号为No.10/816,282的专利申请中有所描述,该申请转让给本发明的受让人。
在一个实施例中,在形成于硅衬底12上的氧化层10上制造晶体管。晶体管主体由放置在层10上的单晶硅层14(如在图1A和1B中的点划线所示)制得。绝缘体上硅(SOI)衬底在半导体行业中是公知的,其中如图所示层14被放置在层10上。例如,SOI衬底可以通过将氧化层10和硅层14粘合在衬底12上,并在随后平坦化层14以使其相对较薄而制成。这一相对较薄的低底(low body)效应层可用于形成上述有源器件主体。用于形成SOI衬底的其他技术包括例如将氧气注入硅衬底以形成掩埋氧化层。在随后的横截面视图中,晶体管被示出在氧化层10上制造,而其下的硅衬底12则未示出。
层14可在要制造n沟道器件的区域中用n型掺杂物来选择性地离子注入,并在要制造p沟道器件的区域中用p型掺杂物来选择性地离子注入。这可用于提供通常可在CMOS集成电路中制造的MOS器件的沟道区中找到的相对较轻的掺杂。I-栅和三栅晶体管可由上述工艺制成p沟道或n沟道器件。(对晶体管沟道区的掺杂可以在诸如图1A或7A所示的工艺流程中的点等工艺流程中的其他点处实现。)
在用于一个实施例的加工工艺中,在沉积了氮化硅层之后在硅层14上放置保护性氧化物(未示出)。对氮化物层进行掩模以定义多个绝缘构件,诸如图1A和图1B中的构件17和18。随后与这些构件对齐地蚀刻其下的硅层14,从而得到硅主体15和16。
硅主体15和16的宽度在具体工艺中可以是临界尺寸,例如在30纳米(nm)栅极长度工艺中,这些主体可以具有30nm的宽度。层14以及形成构件17和18的氮化硅层的厚度例如各自可以位于10-50nm范围之间。
现在,可以在氧化层10上的图1A的结构上沉积一牺牲层。在一个实施例中,该层可以是50-100nm厚的多晶硅层。其他材料也可用于该牺牲层。用于该牺牲层的材料应该能够保护器件的沟道区在如下将描述的源极和漏极区的形成期间免于离子注入。此外,牺牲层应该能够被蚀刻而不损坏在如下将描述的图案化之后围绕牺牲层形成的ILD的完整性。此外,绝缘构件必须能够在有牺牲层存在的情况下被选择性地蚀刻。
接着,牺牲层被图案化为如图2A的构件20和22所示的栅极定义构件。构件20占据了在其中制造用于I-栅晶体管的两个栅极的区域以及允许这些栅极与将在随后示出的栅极相接触的“翅片”。构件22占据了在其中制造用于三栅晶体管的三栅的区域以及同样用于接触的翅片。
在加工工艺的这一点处,可以与构件20和22对齐地蚀刻氮化硅构件17和18,由此露出下面的硅主体15和16的某些部分。如箭头25所示,这些硅主体因未被构件20和22覆盖而被离子注入以形成用于I-栅和三栅晶体管的源极和漏极区。通常会实现但未示出的是,为p沟道和n沟道器件使用分开的离子注入步骤,其中保护层被用于允许用于p沟道和n沟道器件的源极和漏极分开注入。
可选地,氮化硅构件17和18可以保持在原位,而源极和漏极区则以一角度被注入,使得掺杂物进入硅主体15和16的各侧。
此外,可以形成隔片以允许与沟道区相邻地注入的更轻掺杂的源极和漏极区,以及与沟道区隔开的更重掺杂的源极和漏极区。这在以上引用的序列号为10/816,282的申请中有所描述。
现如图3所示在绝缘层10上形成ILD 30。ILD 30围绕构件20和22,并如可以见到的,允许一旦在去除多晶硅之后就进行金属镶嵌。ILD 30例如可以是化学气相沉积(CVD)二氧化硅层。
现在例如可在化学机械抛光(CMP)工艺的条件下平坦化图3的结构以露出氮化硅绝缘构件17和18。这在图4A和4B中都有示出。注意到构件17和18可以与构件20和22一样也与ILD 30的上表面齐平。
现在在图4A和4B的结构上沉积光刻胶层并形成图案以保留在I-栅晶体管区域上的原位。光刻胶层50覆盖绝缘构件17。如图5所示,光刻胶层50让三栅晶体管器件的绝缘构件18得以露出。
随后,如图6A和6B所示,可使用蚀刻工艺来去除塞形氮化硅构件18。使用在氮化硅与ILD 30和牺牲层之间区别对待的蚀刻剂来使ILD 30和构件22保持基本完整。可以使用干法或湿法蚀刻剂。一旦去除了构件18,则如图6B所示露出其下的硅主体16。
接着可以使用例如湿法蚀刻工艺来去除多晶硅牺牲层。所得的结构如图7A和7B所示。剩余的ILD 30现在定义了在其中可以制造用于晶体管的栅极的形状。
从图8中可知,栅介电层60在每个半导体主体15和16之上和周围形成。更具体地,可以沉积栅极电介质以使其覆盖半导体主体16和绝缘构件17的顶面以及每一半导体主体的相对的侧壁。该栅极电介质理想地具有高介电常数,诸如HfO2或ZrO等金属氧化物电介质或者诸如PZT或BST等其他高k电介质。高k介电膜可通过诸如化学汽相沉积(CVD)等任何已知技术形成。另外,栅极电介质可以是生长电介质。在一个实施例中,栅介电层60可以是使用干法/湿法氧化工艺生长的二氧化硅膜。例如,二氧化硅膜可以生长至5至50的厚度。(被保形沉积的介电层如图8所示)。
接着如图8所示,在栅介电层60上形成栅电极(金属)层61。栅电极层61可通过合适的栅电极材料的毯式沉积来形成。在一个实施例中,栅电极材料包括诸如钨、钽、钛和/或其氮化物和合金等金属膜。对于n沟道I-栅和三栅晶体管而言,可以使用范围在4.0至4.6eV的功函数。对于p沟道I-栅和三栅晶体管而言,可以使用范围在4.6至5.2eV的功函数。因此对于带有n沟道和p沟道晶体管的衬底而言,就需要使用两个分开的金属沉积工艺。
金属层61例如可使用CMP来平坦化,并且该平坦化至少持续到如图9A所示露出绝缘构件17的上表面。这样做是为了确保没有金属跨越构件17,因为否则的话I-栅晶体管中的栅极将被一并缩短。从图9中可见,存在用于I-栅晶体管的两个独立栅极62和64以及用于三栅晶体管器件的单个栅极65。
用于三栅晶体管的栅极65具有与底面相对的顶面,并且具有可从图9B中最佳了解的邻近三栅结构形成的相对侧壁。这些侧壁可以连接到硅主体的上表面上。由此,栅极围绕三栅晶体管三侧上的沟道区。对于I-栅晶体管而言,两个独立的栅极62和64由绝缘构件17分隔,而这同样可从ILD被示为已去除的图9B中最佳地了解。
同样可从图9B中最佳地了解,示出了硅主体15和16位于绝缘层10上。沿着漏极区71和72示出了用于每个晶体管的源极区68和70。独立栅极62和64连同其被正交放置的翅片一起可以被很容易地观察到。对于栅极65而言也是一样的。如接触区80、81和82所示,这些翅片允许更容易地形成从覆盖其上的金属化层到栅极的接触。虽然未在图9B中示出,但是可以形成从覆盖其上的金属化层到源极和漏极区以及栅极的接触,尽管该接触未示出。
I-栅晶体管可与三栅晶体管一并用于逻辑电路。I-栅晶体管具有合乎某些电路需要的特性。例如,单个I-栅晶体管可以取决于施加在一个或两个栅极上的电位而提供高电流和中间电流器件。这些器件可以提供“强截止”器件以降低休眠模式或断电模式下的漏电流。I-栅晶体管通过允许滴流(trickle current)还提供用于预充电行的器件。在上述专利申请中,I-栅器件可用作DRAM单元,而上述工艺则可以结合该DRAM制造一并使用。在此情况下,硅主体15是在多个平行且隔开的行内形成的细长体并可在DRAM单元阵列中使用。
虽然在附图中示出了两个分隔的硅主体,但是应该理解也可以使用单个主体。于是就可制造相互串联的三栅和I-栅晶体管。在此情况下,串联的晶体管具有一个源极/漏极区。
以上描述了一种工艺以及所得的用于集成电路的在一公共衬底上同时具有I-栅和三栅结构的结构。

Claims (20)

1.一种方法,包括:
形成具有覆盖其上的绝缘构件的至少两个硅主体;
图案化定义栅极区并与所述硅主体相交的牺牲层;
将所述图案化的牺牲层封入一介电材料;
覆盖所述绝缘构件之一;
去除所述绝缘构件中的另一个;
去除所述图案化的牺牲层;
在所述栅极区内形成绝缘层和金属层。
2.如权利要求1所述的方法,其特征在于,包括平坦化所述介电材料以露出所述绝缘构件。
3.如权利要求2所述的方法,其特征在于,所述硅主体包括单晶硅。
4.如权利要求3所述的方法,其特征在于,所述绝缘构件包括氮化硅。
5.如权利要求4所述的方法,其特征在于,所述牺牲层包括多晶硅。
6.如权利要求5所述的方法,其特征在于,所述平坦化包括化学机械抛光。
7.如权利要求1所述的方法,其特征在于,包括去除所述绝缘构件以达到在所述牺牲层的图案化之后能够被露出的程度。
8.如权利要求1所述的方法,其特征在于,包括在所述牺牲层的图案化之后在所述硅主体内形成源极和漏极区。
9.如权利要求8所述的方法,其特征在于,在两个掺杂过程中完成对所述源极和漏极区的掺杂,一个掺杂过程在侧壁隔片形成之前,而另一个在侧壁隔片形成之后。
10.如权利要求1所述的方法,其特征在于,使用对所述绝缘构件的蚀刻率高于对所述介电材料的蚀刻率的蚀刻剂来完成对所述绝缘构件中的另一个的去除。
11.一种方法,包括:
在绝缘层上定义各自带有第一和第二绝缘构件的第一和第二硅主体;
去除所述第一绝缘构件的至少一部分同时将所述第二绝缘构件保持在原位;
在所述第二硅主体的相对两侧上形成第一栅极结构,所述第一栅极结构具有两个独立的栅极;以及
在所述第二硅主体的三个侧面上形成第二栅极结构。
12.如权利要求11所述的方法,其特征在于,所述第一和第二栅极结构是通过高k绝缘体与它们各自的硅主体绝缘的金属。
13.如权利要求12所述的方法,其特征在于,所述栅极结构是通过去除被层间电介质围绕的牺牲层而形成的。
14.如权利要求13所述的方法,其特征在于,所述牺牲层包括多晶硅,并且所述绝缘构件包括氮化硅。
15.一种集成电路,包括:
衬底;
在所述衬底上并具有第一主体的第一晶体管,所述第一主体在三个侧面上被第一金属栅极围绕;以及
在所述衬底上并具有第二主体的第二晶体管,所述第二主体具有在所述第二主体的相对两侧上的两个独立金属栅极。
16.如权利要求15所述的电路,其特征在于,所述第一和第二主体包括单晶硅。
17.如权利要求16所述的电路,其特征在于,包括放置在所述独立栅极之间的第二主体上的绝缘构件。
18.如权利要求17所述的电路,其特征在于,所述绝缘构件包括氮化硅。
19.如权利要求15所述的电路,其特征在于,包括多个所述第一和第二晶体管,所述晶体管中的某一些是n沟道晶体管,而其他是p沟道晶体管。
20.如权利要求19所述的电路,其特征在于,所述晶体管的主体包括单晶硅。
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US20060128131A1 (en) 2006-06-15
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US8268709B2 (en) 2012-09-18
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US7037790B2 (en) 2006-05-02
US20060071299A1 (en) 2006-04-06
DE112005002428B4 (de) 2010-11-18
CN101027772B (zh) 2011-01-12
US8399922B2 (en) 2013-03-19
US20060068550A1 (en) 2006-03-30
DE112005002428T5 (de) 2009-03-05
US7422946B2 (en) 2008-09-09
US20100297838A1 (en) 2010-11-25
US20130009248A1 (en) 2013-01-10
US7859053B2 (en) 2010-12-28

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