CN101030564A - 多排引线框 - Google Patents

多排引线框 Download PDF

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Publication number
CN101030564A
CN101030564A CNA2007100843924A CN200710084392A CN101030564A CN 101030564 A CN101030564 A CN 101030564A CN A2007100843924 A CNA2007100843924 A CN A2007100843924A CN 200710084392 A CN200710084392 A CN 200710084392A CN 101030564 A CN101030564 A CN 101030564A
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China
Prior art keywords
row
terminal
tube core
lead frame
lead
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Granted
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CNA2007100843924A
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CN100595912C (zh
Inventor
王飞莹
何伟强
王浩宏
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN101030564A publication Critical patent/CN101030564A/zh
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Publication of CN100595912C publication Critical patent/CN100595912C/zh
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    • H01L2924/181—Encapsulation

Abstract

一种用于半导体器件的引线框(10)包括围绕管芯接纳区(14)的第一排端子(12)以及与第一排端子(12)间隔开并围绕其的第二排端子(16)。第一和第二排端子(12，16)具有第一高度(H1)。第一排端子(12)包括具有较大高度(H2)的台阶(26)。将管芯盘(34)连接到第一排端子(12)的导线(36)在端子(12)的第二高度H2部分上方延伸，并附装到端子(12)的第一高度H1部分。台阶(26)确保附装到带台阶端子(12)的接合导线(36)具有高的导线扭结外形，从而使这些导线在后面的工艺步骤中不太容易受损。

Description

多排引线框
技术领域
本发明一般地涉及半导体封装，更具体而言，涉及一种引线框和一种使用该引线框封装半导体器件的方法。
背景技术
在半导体封装中广泛使用导线接合在集成电路(IC)管芯和引线框之间提供电连接。在导线接合应用中，在IC管芯的管芯盘和引线框的引线指(lead finger)之间形成导线环。通常，在各个管芯盘上形成第一导线接合部(wire bond)，并在相应端子上形成第二导线接合部。在某些应用中需要导线环具有对第二导线接合部的大的接近角度，例如用于在将引线指与引线框的管芯接纳区分开的单片化操作过程中防止损伤。通过在接合线中形成高尾部扭结(tail kink)，即，在与第二导线接合部基本竖直间隔处的接合线尾端中形成弯曲，而产生这样的环状外形。但是，因为接合线离第一导线接合部越远就越软，所以难以使接合线的尾端成形。因此，具有尾部扭结的环状外形常常不一致。尾部扭结有时形成得太低，相应的导线环在随后的封装步骤中容易受损。
考虑到以上情况，期望形成具有一致的环状外形的导线接合半导体器件。更具体而言，期望形成一种半导体器件，其中接合线具有在预定高度处形成的尾部扭结。
附图说明
在结合附图阅读时将更好地理解下面对本发明优选实施例的详细说明。本发明通过示例示出而不受附图限制，附图中类似的标号指示类似的元件。应该理解到附图并不按比例并且为了便于理解本发明而进行了简化。
图1是根据本发明实施例的引线框的放大俯视图；
图2是图1的引线框沿线X-X的放大剖视图；
图3是附装到图2的引线框的管芯接纳区上的集成电路(IC)管芯的放大剖视图；
图4是根据本发明的引线框端子的一个实施例的放大立体图；和
图5是用成型化合物(mold compound)封装的管芯和图3的引线框的一部分的放大剖视图。
具体实施方式
下面结合附图进行的详细说明是对本发明目前的优选实施例的说明，而非表示可以实现本发明的唯一形式。应该理解到相同或等同的功能可以由包括在本发明的精神和范围内的不同实施例实现。
附图中的某些特征为了便于图示已被放大，并且附图及其元素不一定成正确的比例。另外，本发明示为在方形扁平无引线(QFN)式封装中实现。但是，本领域普通技术人员将容易理解本发明的细节并且本发明会应用于其它封装类型。在所有附图中，类似的标号用于指示类似的元件。
为了形成具有一致的环状外形的导线接合半导体封装并实现上述和其它优点，本发明提供了一种用于半导体器件的引线框。该引线框包括围绕管芯接纳区的第一排端子、以及与第一排端子间隔开并围绕第一排端子的第二排端子。第一排端子和第二排端子具有第一高度。第一排端子包括台阶，使得第一排端子还具有第二高度。
本发明还提供了一种半导体器件，其包括管芯接纳区、围绕管芯接纳区的第一排端子、以及与第一排端子间隔开并围绕第一排端子的第二排端子。第一排端子和第二排端子具有第一高度。第一排端子包括台阶，使得第一排端子具有第一高度部分和第二高度部分。集成电路(IC)管芯附装到管芯接纳区。管芯包括多个管芯盘。多根导线电连接到各个第一排端子和第二排端子以及管芯盘。连接到第一排端子的导线与第一高度部分连接并在第二高度部分上方延伸。第二高度部分确保导线具有高的最后扭结外形。
本发明还提供了一种封装半导体器件的方法，包括形成引线框的步骤，该引线框具有管芯接纳区、围绕管芯接纳区的第一排端子、以及与第一排端子间隔开并围绕第一排端子的第二排端子。第一排端子和第二排端子具有第一高度。第一排端子包括台阶，使得第一排端子还具有第二高度。集成电路(IC)管芯附装到引线框的管芯接纳区。管芯包括多个管芯盘。第一排端子和第二排端子中的端子利用多根导线电连接到各个管芯盘。管芯、导线以及第一排端子和第二排端子用封装剂封装，使得第一排端子和第二排端子的至少一个底表面露出。例如用划片机将第一排端子与管芯接纳区分离。台阶状的端子确保连接到其上的导线具有高的最后扭结外形，从而它们不会被划片机切割或切口。
图1至4示出了根据本发明的实施例的一种封装半导体器件的方法。
现在参照图1，示出了引线框10，该引线框具有第一排(即内排)端子12和第二排(即外排)端子16，第一排端子12与管芯接纳区14间隔开并围绕管芯接纳区14，第二排端子16与第一排端子12间隔开并围绕第一排端子12。确定管芯接纳区14的尺寸和形状以接纳集成电路(IC)管芯。如本领域技术人员所知，管芯接纳区的尺寸按照管芯的尺寸而变化。一个典型的管芯尺寸是5mm×5mm。管芯接纳区14一般是方形的，但也可以按照管芯的形状而具有其它形状。在此具体实施例中，管芯接纳区14的各个角部经由多个联结杆(tie bar)18中的各个而连接到引线框10的相应角部。第一排端子12利用第一连杆20连接到管芯接纳区14并从管芯接纳区14向外延伸，而第二排端子16利用第二连杆24从引线框10的侧部22向内(向着管芯接纳区14)延伸。
现在参照图2，示出图1的引线框10沿线X-X的放大剖视图。如图所见，第一排端子12和第二排端子16具有第一高度H1。此外，第一排端子12包括台阶26，使得第一排端子12具有第一高度H1部分28和第二高度H2部分30。第二高度H2约为第一高度H1的两倍。第二高度H2优选至少约8密耳。在本发明的一个实施例中，第二高度H2是10密耳，并且第一高度H1是5密耳。无论如何，本领域技术人员将理解到本发明并不受第一排端子12和第二排端子16的高度H1和H2的限制。
引线框10中的台阶26可以用半刻蚀工艺形成。更具体而言，第一排端子12开始形成为具有高度H2的均匀形状(例如矩形)。然后，例如使用已知的刻蚀工艺刻蚀端子12来形成台阶，其中较低台阶部分或第一高度H1部分28(即被刻蚀部分)远离管芯接纳区14，而第二高度H2部分30接近管芯接纳区14。但是，本领域技术人员将理解到，台阶26可以用其它方式形成。例如，如果第一排端子12开始具有均匀的高度H1，则可以通过增高端子12中最靠近或接近管芯接纳区14的部分(例如用聚酰亚胺带或环氧树脂)来形成该台阶。台阶26还可以使用机械模压(coining)工艺形成。如图2所示，引线框10的第一连杆20和第二连杆24以及侧部22可以具有稍小于第一高度H1的高度。
现在参照图3，集成电路(IC)管芯32附装到如图所示的引线框10的管芯接纳区14。管芯32可以是本领域技术人员已知的类型，例如在硅晶片上形成并从其切割的电路，并且管芯32用已知方式附装到管芯接纳区14，例如用粘性材料层或粘性带。管芯32包括多个管芯盘34，这些管芯盘34可以在管芯32的顶表面上排列成排或在管芯32的顶表面上排列成阵列。第一排端子12和第二排端子16中的各个与管芯盘34经由多根导线电连接。更具体而言，第一导线36用于将管芯盘34中的预定多个电连接到第一排端子12，而第二导线38用于将管芯盘34中的预定多个电连接到第二排端子16。利用本领域已知的导线接合工具40例如毛细管件(capillary)，将第一导线36和第二导线38连接到管芯盘34以及第一排端子12和第二排端子16。第一导线36和第二导线38可以由金(Au)、铜(Cu)、铝(Au)或其它本领域已知且商业上可得到的导电材料制成。
从图3可见，台阶26用于在将管芯盘34与第一排端子12相连接的第一导线36中形成尾部扭结42。更具体而言，第一导线36连接到管芯盘34，然后连接到第一排端子12的第一高度H1部分28，从而第一导线36在第二高度H2部分30上方延伸，这使得第一导线36具有高的最后扭结的导线外形。不需要使导线36的尾端成形的附加步骤。于是，可以使用传统的导线接合工艺形成导线36。另外，因为台阶26具有预定高度H2，所以在距第二导线接合部基本不变的竖直间隔处形成尾部扭结42。由此，所有将管芯盘34连接到第一排端子12的第一导线36具有一致的环状外形。通过用作支承平台，台阶26有助于防止随后的封装工艺过程中的导线扫掠(wire sweep)，如下所述。
参照图4，可以在台阶26中形成凹槽44。凹槽44从第二高度H2部分30的顶表面向着第一导线所附装到的第一高度H1部分28延伸。当第一导线36配合装入凹槽44中时，由此防止将管芯32连接到第一排端子12的第一导线36在封装工艺过程中横向运动，从而防止导线扫掠。
现在参照图5，示出了几乎完整的QFN封装50的剖视图。QFN封装50包括附装到管芯接纳区14的管芯32、以及将管芯盘34电连接到第一排端子12和第二排端子16的第一导线36和第二导线38。管芯32、第一导线36和第二导线38、以及引线框的至少一个顶表面用封装剂或成型化合物52覆盖。如本领域已知的，使用成型工艺例如注入成型工艺来进行封装。封装剂52可以包括商业上可得到的公知成型材料，例如塑料或环氧树脂。通过例如划割单片化(saw singulation)将侧部22和第二连杆24从引线框10割下，使得第二排端子16在其底部和侧部露出来。
进行另一单片化操作来将第一排端子12与管芯接纳区14分离。在此具体实施例中，通过利用划片机例如钻石轮划片机(dicing saw)沿线A-A和B-B进行深度受控切割，而将第一排端子12与管芯接纳区14分离。由于将管芯盘34连接到第一排端子12的第一导线36具有高的最后扭结的导线外形42，所以防止了第一导线36在单片化操作过程中被划片机刀具损伤或切断，该外形42确保了在单片化操作过程中在各个第一导线36和划片机刀具之间保持足够的间隙。
于是，将理解到本发明提供了一种封装半导体器件的方法，包括：形成引线框的步骤，该引线框具有管芯接纳区、围绕管芯接纳区的第一排端子、以及与第一排端子间隔开并围绕第一排端子的第二排端子，其中第一排端子和第二排端子具有第一高度，且第一排端子包括台阶，使得第一排端子还具有第二高度；以及将集成电路(IC)管芯附装到引线框的管芯接纳区，随后利用多根导线将IC管芯上的管芯盘电连接到第一排端子和第二排端子中的端子，并最后用封装剂封装管芯、导线以及第一排端子和第二排端子的步骤，其中使第一排端子和第二排端子的至少一个底表面露出。例如通过深度受控的切割进行的划割而将第一排端子与管芯接纳区分离。连接到第一排端子的端子上的导线附装到台阶的较低(第一高度)部分，并且台阶的第二高度部分导线具有高的最后扭结，从而导线不会被划片机切割或切口。在另一实施例中，各个台阶包括凹槽，导线配合装入该凹槽中以限制导线扫掠问题。
从以上说明很明显，本发明提供了一种引线框和一种使用该引线框封装半导体器件的方法，其相对于现有产品和工艺具有优点。例如，通过在第一排(内排)端子上形成台阶，本发明确保在接合导线中的预定高度处一致地形成尾部扭结，由此防止封装工艺过程中导线受损。此外，可以使用传统的导线接合工艺形成尾部扭结。另外，由于该台阶用作支承平台，防止了在随后的封装工艺过程中的导线扫掠。
为了解释和说明对本发明优选实施例进行了描述，但此描述并非穷尽性的且不应将本发明局限于所公开的形式。本领域技术人员将认识到可以对上述实施例进行改变而不脱离其宽泛的发明概念。例如，本发明可以在引线框面板上实现。另外，可以形成具有多于两排端子的引线框，其中内排中的一排或多排是台阶状的。因此，应该理解到本发明并不限于所公开的具体实施例，而应覆盖落入由所附权利要求限定的本发明的精神和范围内的修改。

Claims (10)

1.一种用于半导体器件的多排引线框，包括：
用于接纳半导体集成电路(IC)管芯的管芯接纳区；
第一排端子，所述第一排端子与所述管芯接纳区间隔开并围绕所述管芯接纳区；以及
第二排端子，所述第二排端子与所述第一排端子间隔开并围绕所述第一排端子，其中所述第一排端子和第二排端子具有第一高度，且所述第一排端子包括台阶，使得所述第一排端子还具有第二高度。
2.根据权利要求1所述的多排引线框，其中所述台阶对将所述管芯接纳区上的管芯连接到所述第一排端子的导线提供支承，以确保所述导线具有高的最后扭结的导线外形。
3.根据权利要求1所述的多排引线框，其中在所述台阶中形成凹槽。
4.根据权利要求1所述的多排引线框，其中所述第二高度约是所述第一高度的两倍。
5.根据权利要求4所述的多排引线框，其中所述第二高度至少约为8密耳。
6.根据权利要求4所述的多排引线框，其中所述第一高度是约5密耳。
7.根据权利要求1所述的多排引线框，其中所述台阶用半刻蚀工艺形成。
8.根据权利要求1所述的多排引线框，其中所述台阶用模压工艺形成。
9.根据权利要求1所述的多排引线框，其中通过在所述第一排端子的顶表面的至少一部分上分布环氧树脂并使所述环氧树脂固化来形成所述台阶。
10.根据权利要求1所述的多排引线框，其中通过在所述第一排端子的顶表面的至少一部分上附装聚酰亚胺带来形成所述台阶。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102625516A (zh) * 2011-01-26 2012-08-01 无锡华润华晶微电子有限公司 功率ic、引线框以及包括该功率ic和引线框的封装结构
CN103633056A (zh) * 2013-12-06 2014-03-12 矽力杰半导体技术(杭州)有限公司 引线框、封装组件及其制造方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007089209A1 (en) * 2006-02-01 2007-08-09 Infineon Technologies Ag Fabrication of a qfn integrated circuit package
US20080029855A1 (en) * 2006-08-04 2008-02-07 Yi-Ling Chang Lead Frame and Fabrication Method thereof
TW200937667A (en) * 2008-02-20 2009-09-01 Advanced Optoelectronic Tech Package structure of chemical compound semiconductor device and fabricating method thereof
US8492883B2 (en) * 2008-03-14 2013-07-23 Advanced Semiconductor Engineering, Inc. Semiconductor package having a cavity structure
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
JP5532570B2 (ja) * 2008-09-29 2014-06-25 凸版印刷株式会社 リードフレーム型基板とその製造方法ならびに半導体装置
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US20110193207A1 (en) * 2010-02-09 2011-08-11 Freescale Semiconductor, Inc Lead frame for semiconductor die
US8508026B2 (en) 2010-11-30 2013-08-13 Stats Chippac Ltd. Integrated circuit packaging system with connection supports and method of manufacture thereof
JP5953703B2 (ja) * 2011-10-31 2016-07-20 ソニー株式会社 リードフレームおよび半導体装置
US8937376B2 (en) * 2012-04-16 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor packages with heat dissipation structures and related methods
US9496214B2 (en) * 2013-05-22 2016-11-15 Toyota Motor Engineering & Manufacturing North American, Inc. Power electronics devices having thermal stress reduction elements
CN104112728B (zh) * 2013-11-22 2017-10-31 广东美的制冷设备有限公司 器件安装结构和集成电路模块
JP6276338B2 (ja) * 2016-07-25 2018-02-07 ラピスセミコンダクタ株式会社 半導体装置及び計測機器

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4809135A (en) * 1986-08-04 1989-02-28 General Electric Company Chip carrier and method of fabrication
JPS6418246A (en) * 1987-07-14 1989-01-23 Shinko Electric Ind Co Lead frame for semiconductor device
US5532905A (en) * 1994-07-19 1996-07-02 Analog Devices, Inc. Thermally enhanced leadframe for packages that utilize a large number of leads
KR0145768B1 (ko) * 1994-08-16 1998-08-01 김광호 리드 프레임과 그를 이용한 반도체 패키지 제조방법
US5886396A (en) * 1995-06-05 1999-03-23 Motorola, Inc. Leadframe assembly for conducting thermal energy from a semiconductor die disposed in a package
US6407333B1 (en) * 1997-11-04 2002-06-18 Texas Instruments Incorporated Wafer level packaging
JP3545200B2 (ja) * 1997-04-17 2004-07-21 シャープ株式会社 半導体装置
US6545342B1 (en) * 1999-05-03 2003-04-08 Texas Instruments Incorporated Pre-finished leadframe for semiconductor devices and method of fabrication
US6864423B2 (en) * 2000-12-15 2005-03-08 Semiconductor Component Industries, L.L.C. Bump chip lead frame and package
US6348726B1 (en) * 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
US6720207B2 (en) * 2001-02-14 2004-04-13 Matsushita Electric Industrial Co., Ltd. Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device
JP3877985B2 (ja) * 2001-08-15 2007-02-07 富士通株式会社 磁気抵抗ヘッド及びその製造方法
US6838751B2 (en) * 2002-03-06 2005-01-04 Freescale Semiconductor Inc. Multi-row leadframe
US6777265B2 (en) * 2002-04-29 2004-08-17 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7042071B2 (en) * 2002-10-24 2006-05-09 Matsushita Electric Industrial Co., Ltd. Leadframe, plastic-encapsulated semiconductor device, and method for fabricating the same
US20060170081A1 (en) * 2005-02-03 2006-08-03 Gerber Mark A Method and apparatus for packaging an electronic chip

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102625516A (zh) * 2011-01-26 2012-08-01 无锡华润华晶微电子有限公司 功率ic、引线框以及包括该功率ic和引线框的封装结构
CN102625516B (zh) * 2011-01-26 2016-01-06 无锡华润华晶微电子有限公司 功率ic、引线框以及包括该功率ic和引线框的封装结构
CN103633056A (zh) * 2013-12-06 2014-03-12 矽力杰半导体技术(杭州)有限公司 引线框、封装组件及其制造方法
US9559043B2 (en) 2013-12-06 2017-01-31 Silergy Semiconductor Technology (Hangzhou) Ltd. Multi-level leadframe with interconnect areas for soldering conductive bumps, multi-level package assembly and method for manufacturing the same
CN103633056B (zh) * 2013-12-06 2017-09-01 矽力杰半导体技术(杭州)有限公司 引线框、封装组件及其制造方法

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US7301225B2 (en) 2007-11-27
TWI325169B (en) 2010-05-21

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