CN101053234A - 精确有限自动机(dfa)处理 - Google Patents

精确有限自动机(dfa)处理 Download PDF

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CN101053234A
CN101053234A CNA200580034214XA CN200580034214A CN101053234A CN 101053234 A CN101053234 A CN 101053234A CN A200580034214X A CNA200580034214X A CN A200580034214XA CN 200580034214 A CN200580034214 A CN 200580034214A CN 101053234 A CN101053234 A CN 101053234A
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dfa
stored
image
instruction
cache
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CN101053234B (zh
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格雷格·A·鲍查德
大卫·A·卡尔森
理查德·E·科斯勒
穆罕默德·R·休斯塞恩
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Kawim Co., Ltd.
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Cavium Networks LLC
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Abstract

一种用于越过实时具有输入的分组数据的精确自动图像的处理器。处理器包括至少一个处理器内核和DFA模块,该DFA模块对至少一个处理器内核异步操作用于越过存储在具有存储在连贯缓冲存储器中的分组数据的非缓冲存储器中的至少一个DFA图像。

Description

精确有限自动机(DFA)处理
相关申请
本专利要求保护2004年9月10日提交的第60/609,211号临时申请,和2005年4月8日提交的第60/669,672号临时申请的权益。上述申请的全部教导通过认证在此并入本文。
背景技术
开放式通信系统互联参考模型(OSI)定义了用来在传输媒体上进行通信的七个网络协议层(L1-L7)。上层(L4-L7)负责端到端的通信,下层(L1-L3)负责本地通信。
网络应用认知系统需要处理、过滤、交换L3到L7网络协议层,例如,L7网络协议层,诸如超文本传输协议(HTTP)和简单邮件传输协议(SMTP),以及L4网络协议层,比如传输控制协议(TCP)。除处理网络协议层外,网络应用认知系统要同时以线速保证这些协议的访问和内容的安全性通过L4-L7网络协议层包括防火墙,虚拟专用网(VPN),安全套接字协议层(SSL),入侵检测系统(IDS),互联网协议安全性(IPSec),反病毒(AV)和反垃圾邮件功能。
网络处理器对于高处理能力的L2和L3网络协处理是有必要的,也就是说,执行处理以线速转寄数据包的数据包。通常,通用处理器被用来处理需要较高智能处理的L4-L7网络协议。例如,L4网络协议的传输控制协议(TCP)需要多计算精度任务,包括数据包中的整个有效载荷的检查和、TCP片段缓冲器的管理、保留每一次连接的所有次数的多次计数。虽然通用处理器可以执行计算精度任务,但是它不能提供足够的性能来处理数据,以致数据不能够以线速被转寄。
而且,检查数据包内容的内容认知应用需要在数据流中搜索包含混合字符串和多次重复的特征类的表达式。可以在软件中使用几种搜索算法来运行这种任务。一种算法是精确有限自动机(DFA)。使用DFA搜索算法时有许多局限性,例如,在重复模式的数据流中以指数形式增长的图像大小和错误的匹配。
由于这些局限性,内容处理应用需要对模式搜索产生的结果进行足够量的后处理。后处理需要用其他连接状态信息限定匹配模式,例如连接类型、数据包中协议头中的某些值。还需要其他类型的计算精度限定,例如,模式匹配只有在数据流中的某种位置范围内时才有效,或被另一种模式所跟随而且与前面的模式在某种排列中或在前面模式特定分支之中或之后。例如,规则表达式匹配把不同的操作符和允许将被结构化的复杂表达式的单个字符合并。
发明内容
本发明用于提高处理器运行内容处理应用的速度。处理器包括至少一个处理器内核和精确有限自动机模块(DFA),该精确有限自动机模块异步操作至少一个处理器内核,来越过存储在具有存储在第二存储器中的分组数据的第一存储器内的至少一个DFA图像转换。
DFA模块可以包括第一存储控制器、至少一个DFA线程引擎和指令输入逻辑。处理器内核可以通过指令输入逻辑生成的指令队列提交DFA指令到DFA模块。DFA指令可以指示存储在第二存储器中的分组数据用以使用和存储在第一存储器中的DFA图像以越过。DFA模块可以部署DFA指令到DFA线程引擎。DFA线程引擎可以取得存储在第二存储器中的分组数据,并且发布与所取得的分组数据相对应的存储器寻址指令。
例如,第一存储器可以是非缓冲存储器,第二存储器可以是连贯缓冲存储器。DFA线程引擎顺序取得存储在连贯存储器中的分组数据,每次一个字节。DFA线程引擎然后每字节的从连贯缓冲存储器中接收到的分组数据发布非缓冲存储器加载指令以越过存储在非缓冲存储器中DFA图像的下一个状态。DFA线程引擎也可以将中间或最终结果写入连贯缓冲存储器。
附图说明
本发明的前述和其它方面、特征和优点,从下面更加具体的描述中可以体现出来,附图中相同的参考数字指代不同附图中的相同部件。附图并不是严格按照比例所绘制的,其重点在于示出本发明的原理。
图1A是根据本发明的原理的包括网络处理器的网络服务处理系统框图;
图1B是图1A中显示的网络服务处理器框图;
图2A和2B图示了可仿效的DFA图像;
图3A是根据本发明原理的精简指令集计算(RISC)处理器的框图;
图3B是图3A中的DFA模块的框图;
图4A示出DFA指令队列的结构;
图4B示出下一块缓冲区指针指令格式;
图5A示出典型DFA图像的另一个实施方案;
图5B示出图5A中DFA图像的不同的可能的节点标识;
图6显示了直接模式结构化将由DTE处理的数据的实施例;
图7A显示了结构化将由DTE处理的数据的集合模式的实施例;
图7B示出DFA集合指针指令格式;
图8A示出DFA指令格式;以及
图8B示出DFA结果格式;
具体实施方式
本发明优选的实施方案的描述如下所述:
图1A是根据本发明原理的包括网络服务处理器110的安全设备100的框图。安全设备100是独立的系统,可以将从一个以太网端口(Gig E)上所接收的数据包转发到另一个以太网端口(Gig E),并且在转寄数据包之前对收到的数据包执行多种安全功能。例如,安全设备100能够在将处理过的数据包传递到本地网之前对从广域网接收到的数据包进行安全处理。
网络服务处理器110包括硬件数据包处理、缓冲、工作分发、排序、同步化和连贯缓存支持以加快所有数据包处理任务。网络服务处理器110处理压缩到接收的数据包中的开放式系统互联网L2-L7层协议。
网络服务处理器110通过物理接口PHY104a、104b从以太网端口(Gig E)接收数据包,对接收到的数据包运行L7-L2层网络协议的处理,并通过物理接口104a、104b或PCI总线106转寄处理过的数据包。网络协议处理可以包括网络安全协议的处理,如防火墙,应用防火墙,包括IP安全性(IPSEC)和/或安全套接字层(SSL)的虚拟专用网(VPN),入侵检测系统(IDS)和反病毒(AV)
网络服务处理器中的动态随机存储器(DRAM)控制器133(图1B)控制对被连接到网络服务处理器110上的扩展DRAM108的访问。DRAM108储存从PHY接口104a,104b或可扩展外部设备组件互联(PCI-X)接口106接收到的数据包供网络服务处理器110处理。
网络服务处理器110中的低延迟存储控制器360(图3B)控制低延迟存储器(LLM)118。LLM118可以被网络服务或安全设备使用进行快速查询,包括可能是入侵检测系统(IDS)或反病毒(AV)设备所需要的规则表达式匹配。
规则表达式是表示字符串匹配模式的通同方法。规则表达式的原子元素是要被匹配的单个字符。这些元素与元字符操作符合并允许用户表示连接,交替,星号等等。串连被用来创建来自单个字符(或者子字符串)的多个字符匹配模式,而使用交替(|)创建可以匹配两个或更多子字符串中的任何一个的模式。星号(*)允许模式匹配字符串中的模式的零(0)或更多次的出现。合并不同的操作符和单独字符允许复杂的将被结构化的表达式。例如,表达式th(is|at)*)会匹配th,this,that,thisis,thisat,thatis,thatat,等等。
图1B是图1A中所示网络服务处理器110的框图。网络服务处理器110通过使用结合图1A所描述的至少一个处理器内核120来执行高应用性能。
数据包被接收用于通过SPI-4.2或RGMII接口,由GMX/SPX单元122a,122b中的任何一个处理。数据包也可以通过PCI接口124而被接收。GMX/SPX单元(122a,122b)通过检查包括在接收到的数据包中的L2网络协议头中的各个区域对接收到的数据包执行预处理,然后将数据包转寄给数据包输入单元126。
数据包输入单元126对包含在接收到的包中的网络协议头(L3层和L4层)进行进一步的预处理。这个预处理包括对传输控制协议(TCP)/用户数据包协议(UDP)(L3层网络协议)的检查和检查。
自由池分配器(FPA)128保持二级缓冲存储器130和DRAM108的自由存储器的指针池。输入包处理单元126使用指针池中的一个来存储接收到的分组数据在二级缓冲存储器130或DRAM108中,另一个指针池来为处理器内核120分配工作队列入口。
包输入单元126将分组数据以一种方便在至少一个处理器内核120中执行的更高层软件以进一步处理更高级网络协议的格式写入二级缓冲存储器130或DRAM108的缓冲区中。
I/O接口(IOI)136管理总的协议和分配,提供连贯的I/O分割。IOI136包括I/O桥(IOB)138和取和加单元(FAU)140。FAU140中的寄存器用来保持被用于通过包输出单元126转寄处理的包的输出队列的长度。IOB138包括缓冲队列,用于存储将在I/O总线142,连贯存储器总线144,包输入单元126和包输出单元146之间传递的信息。
包次序/工作(POW)模块148为处理器内核120排列和分配工作。通过增加工作队列入口到队列中来排列工作。例如,通过包输入单元126增加工作队列入口用于每个包的到达。计时器单元150用来为处理器内核分配工作。
处理器内核120从POW模块148中请求工作。POW模块148为处理器内核120选择(即,分配)工作,返回指向描述工作的工作队列入口的指针到处理器内核120。
处理器内核120包括指令缓冲152,一级(L1)数据缓冲154和加密加速156。在一个实施方案中,网络服务处理器110包含十六个超级标量RISC(精简指令集计算机)型处理器内核120。在一个实施方案中,每个超级标量RISC型处理器内核120是MIPS64处理器内核第二版的扩展。
二级(L2)缓冲存储器130和DRAM108由所有处理器内核120和I/O联合处理器设备共享使用。每个处理器内核120通过连贯存储器总线144耦合到二级缓冲存储器130上。连贯存储器总线是用于所有存储器以及在处理器内核120,IOB138和二级缓冲存储器130和二级缓冲存储器131之间I/O事务处理的通讯通道。在一个实施方案中,连贯存储器总线144对16个处理器内核120是可升级的,通过高缓冲和优先列入I/O支持完全连续一级数据缓冲154的写入。
二级存储控制器131保持存储参考一致性。无论块是存储在二级缓冲存储器130,DRAM108或在传输中,它都为每个请求返回块的最新拷贝。在每个处理器内核120中,它还为数据缓冲154存储标志的副本。它对缓冲块存储的请求和数据缓冲标记进行比较,当从另一个处理器内核或一个I/O组件通过IOB138传来的存储指令时,将处理器内核120的数据缓冲标志设为无效(所有拷贝)。
DRAM控制器133支持达到16兆的DRAM。DRAM控制器133支持到DRAM108的64比特或128比特的接口。DRAM控制器133支持DDR-I(双倍数据速率)和DDR-II协议。
在数据包被处理器内核120处理后,包输出单元(PKO)146从存储器读取分组数据,运行L4层网络协议后处理(例如,产生TCP/UDP检查和),通过GMX/SPC单元122a,122b将包传递,释放包使用的二级缓冲130/DRAM108。
低延迟存储控制器360(图3B)管理传递中的事务(加载/存储)到/从LLM118。低延迟存储器(LLM)118由所有的处理器内核120共享使用。LLM118可以是动态随机访问存储器(DRAM)、精简延迟动态随机访问存储器(RLDRAM)、同步随机访问存储器(SRAM)、快周期随机访问存储器(FCRAM)、或者在本领域内已知的任何其它类型的低延迟存储器。RLDRAM提供30纳秒的存储器延迟或更好,也就是,所消耗的时间用来满足处理器120发起的存储请求。每个处理器内核120通过低延迟存储器总线158直接与LLM控制器360相耦合。低延迟存储器总线158是用于在处理器内核120和LLM控制器360之间进行内容认知应用处理的通讯通道。LLM控制器30在处理器内核120和LLM118之间被耦合,用来控制对LLM118的访问。
网络服务处理器110也包括除去处理器内核120的特殊协同处理器,这样网络服务处理器获得高处理能力。压缩/解压缩协同处理器132对接收到的包专门运行压缩和解压缩。精确有限自动机(DFA)模块134包括专门的DFA引擎370(图3B)来加速为反病毒(AV)、入侵检测系统(IDS)和达到4Gpps的其它内容处理应用的模式和签名匹配需要。
内容认知应用处理利用存储在LLM118里的模式/表达式(数据)。模式/表达式可以是精确有限自动机(DFA)形式。DFA是状态机器。DFA状态机的输入是字节字符串(8位)(即,DFA的字母是字节)。每个输入字节使状态机从一个状态转变为下一个状态。如图2A中所示,状态和转变功能可以被图像200表示,其中每个图像节点(节点0到3)是状态,连接不同节点的不同曲线表示不同输入字节的状态转换。状态可能包含某些跟状态相关的字母,例如′A...Z,a...z,0...9,′等等。状态机的现在状态是选择特定图像节点的节点标识。小型图像,节点的数量可以从几个到128,000左右。大的图像可以有1,000,000甚至更多的点数。
在说明性实施例中,DFA图像200被设计城搜索目标字符串表达式‘abc’。因此,DFA图像用来对输入数据进行搜索,查找对字符串‘abc’的精确匹配。这个表达式是固定长度的表达式,也就是说,图像的节点数量和深度是知道的(例如,固定)。
为了创建DFA图像,表达式被传递,编译器创建根节点(即,节点0),为目标表达式添加节点1-3到图像(即,目标字符串中的每个字符的一个附加节点)。继续这个例子,输入字符流包含可仿效的串‘12abc3’。通过使用DFA图像标识目标字符串表达式‘abc’,输入串被搜索。
DFA图像的初始状态是节点‘0’。按顺序读取每个字符或字节,DFA一直保持在节点0,直到读到目标字符串表达式的第一个字符。例如,在输入流中检测目标字符串表达式的第一个字符是‘a’时,从节点0到1的曲线标记为‘a’。读取输入流中的下一个字符。如果检测到的是目标字符串表达式(例如,‘b’)之外的其它字符,从1回到0的曲线标记为‘非b’。然而,在输入流中检测到的下一个字符是字符‘b’时,一段标记为‘b’的曲线从节点1到节点2。读取输入流中的下一个字符。如果检测到的是目标字符串表达式(例如,‘c’)之外的其它字符,从2回到0的曲线标记为‘非c’。然而,在输入流中检测到的下一个字符是字符‘c’时,一段标记为‘c’的曲线从节点2到节点3。由于目标字符串表达式‘abc’是一个固定长度的表达式,节点3就是终端节点,报告作为搜索的结果,也就是说,在输入流中找到了表达式‘abc’及位置。
此外,通过编译器为目标表达式需要的图像创建合适的节点,分析一个或更多的目标表达式,更复杂的DFA图像可以被简单地创建。因此,单个图像可以用来搜索复合表达式,该符合表达式可以是固定长度、可变长度、或固定长度跟可变长度的合并。
图3A是根据本发明原理的精简指令集计算(RISC)处理器的框图。处理器(处理器内核)120包括集成执行单元302,指令分配单元304,指令获取单元306,存储器管理单元(MMU)308,系统接口310,低延迟接口350,加载/保存单元314,写缓冲316和安全加速器156。处理器内核120还包括EJTAG接口330,允许执行调试操作。系统接口310控制对扩展存储器的访问,也就是,处理器120的扩展存储器,例如,扩展二级缓冲存储器130或者首/主存储器108。
集成执行单元302包括乘法器单元326,至少一个寄存器文件(主寄存器文件)328和两个保持寄存器330a,330b。保持寄存器330a和330b用来保存要写入LLM118的数据和使用LLM加载/保存指令从LLM118中读出的数据。通过在停止流水线前允许两个未解决的负载,保持寄存器330a和330b提高了指令流水线的效率。虽然显示了两个保持寄存器,但可能使用一个或多个保持寄存器。乘法器单元326有64位直接寄存乘法器。指令读取单元306包括指令缓冲(ICache)152。加载/保存单元314包括数据缓存154。在一个实施方案中,指令缓存152是32K字节,数据缓存154是8K字节,写入缓冲器316是2K字节。存储器管理单元308包括翻译后援缓冲器(TLB)340。
在一个实施方案中,处理器120包括加密加速模块(安全加速器)156,加密加速模块包括用于三重数据加密标准(3DES),高级加密标准(AES),安全散列算法(SHA-I),信息摘要算法#5(MD5)密码体系的加速。加密加速器模块156通过移动到执行单元302中的主寄存器文件328或者从其中移出进行通讯。在乘法器单元326中运行RSA和密钥交换(DH)算法。
图3B是图3A中DFA模块134的框图。DFA模块134包括低延迟DRAM控制器360、至少一个DFA线程引擎(DTE)370(16显示),和指令输入逻辑380。指令输入逻辑380包括DFA指令队列382和报警器384。DFA指令队列382排列存储在L2/DRAM(130/108)中的DFA指令,报警器指示在DFA指令队列382中存储了多少DFA指令。内核120软件可以对每个单独的DFA指令进行报警器写操作,也可以累积多个DFA指令到一个报警器写操作中。每个DFA指令包括DFA模块134需要的信息,来开始DTE370、读取输入数据,转换保存在LLM118中的DFA图像以及把结果写入L2/DRAM(130/108)。DFA指令的格式会在以后结合图8A进行描述。
DTEs370可以用来运行模式搜索。通常,DTEs370越过具有进入的分组数据(在L2/DRAM(130/108)中)的图像200(图2)(在LLM118中)以便在分组数据中查找特定的表达式。例如,网络服务处理器可能同时跟踪上到1000个TCP输入流,其中每个流被发送到不同的DTE来查找特定的表达式。在内核120中的软件越过之前必须先(I)借助LLM总线158预装DFA图像到LLM118中;(II)预装DFA指令到L2/DRAM(130/108)中;(III)借助IOB142提交DFA指令到DFA模块134。DFA指令指示DFA图像200通过进入的分组数据而越过。之后,DFA模块134取得并排列DFA指令,分配每个DFA指令到16个可用的DTE370中的一个。所有DTE370都是相同的和相当的,因此任何DFA指令都可以被分配给任一个可用的DTE370。DTE370一旦收到指令,它同时(a)通过IOB142从L2/DRAM(130/108)取得分组数据;(b)每字节分组数据发布一个LLM DRAM负载以越到字节的下一个DFA图像状态;(c)通过IOB142将中间或最终结果返回给L2/DRAM(130/108)。
通常,DTE370是状态机,可以使用硬件、软件或软硬件混合来实现。在一些实施方案中,DTE370在使用组合逻辑的硬件中被实现。在另一种实施方案中,每个DTE370分别由不同的处理器来实现。还有的其它的实施方案中,DTE370使用普通处理器来实现。例如,每个DTE370可以是运行在适于提供共享的、多任务处理的通用处理器上的单独的任务(即,指令的次序)。多任务处理是应用在操作系统中以在多个独立的工作中(即,DTE370)共享单个处理器的一种技术。交替的或附加的,每个DTE370可以是运行在适于提供多线程操作能力的通用处理器中的单独处理线程。多线程处理操作与多任务处理不同的是线程通常彼此间比任务共享更多的环境。例如,当线程共享一个地址空间和全局变量集时可以被它们的程序计数器和栈指针区分开来。
图4A图示了存储在L2/DRAM(130/108)中的DFA指令队列400的结构。每个指令队列是信息块/缓冲器402的链表。每个信息块402包括至少三个DFA指令404,组成全部信息块大小406。如果有其它信息块(例如402)存在,下一个信息块缓冲器指针408立刻跟随信息块402中的最后一个指令404。
向DFA指令队列400插入数据包,内核120软件将DFA指令404写入DFA指令队列400,如果需要的话会分配信息块,然后通过把把DFA指令404的数量加入到DFA指令队列400写入DFA报警器384。DFA模块134从DFA指令队列400(开始于尾部410)读取,并当到达一个信息块(例如404/404)的最后一个指令时,DFA模块134从DFA指令队列400(从尾410开始)读取和转换下一个信息块缓冲器指针408到下一个块(例如402/402)。当DFA模块134跳到块402,释放前面的信息块(例如402/404)给FPA128(图1B)。
DFA模块134保持DFA指令队列的尾指针410,内核120软件保持DFA指令队列的头指针412。尾指针410和头指针412之间的距离是DFA指令队列400的长度和未完成的报警器记数。DFA指令队列400的大小仅仅受可用的存储器和DFA指令队列400的20位未完成报警器记数器的限制。
图4B列举了下一个信息块缓冲器指针格式450。下一个信息块缓冲器指针是64位的单字,包含36位的地址(Addr)段452。在包含下一个DFA指令402的下一个信息块400中,地址段452选择有效的L2/DRAM(130/108)字节位置。
图5A图示存储在LLM118中的DFA图像500的结构。DFA图像500包括N个节点510a-510n。DFA图像500中的每个节点510是一个256次节点指针512的简单排列,每个对应一个唯一的输入字节值。每个次节点指针512包含次节点标识号514用来对输入字节直接进行标识。
DFA模块134支持18位次节点指针存储格式516或36位次节点指针存储格式518。对于18位指针,每个节点510需要18X256比特或512字节的LLM118存储空间。每个次节点指针516是17位次节点标识ID和奇偶校验位。奇偶校验是偶校验(即,P=XOR(或OR)17位次节点ID514的所有位)。对于36位指针,每个节点510需要36X256比特或1KB的LLM118存储空间。复制可以提高存储空间需求。每个次节点518是20位次节点标识ID,2位类型值,7位SECDED ECC码和7个必须置零的未用位。DTE370使用36位指针中的SECDED ECC码修复所有单位错误和检查所有双位错误。类型值指示下一个节点类型,例如:0=正常;1=已标记;2=终端。
DTE370支持三种特殊节点指针条件:
1.PERR-次节点指针包含错误。DTE370生成结果字指示失败的LLM118位置。DTE370终止图像500的转换;
2.TERM-下一个节点是终端节点,图像转换为停止。DTE370生成结果字指出转换到终端节点的字节,前一个节点ID,下一个节点ID。DTE370终止图像500的转换;
3.MARKED-内核120软件为了以后的分析标记这个临界点。DTE370生成结果字指出转换到标记节点的字节,前一个节点ID,后一个节点ID。DTE370继续图像500的转换;
对于18位模式,DTE370通过比较下一个节点ID决定特定的TERM和MARKED条件。在这种情况下,所有进入被标记节点的过渡都被标记。对于36为模式,DTE370直接根据下一个节点指针中的类型字段决定特定的TERM和MARKED条件。独立的过渡,不仅仅独立的节点,在36位模式下都会被标记。
图5显示了所有可能的17位节点标识ID和它们在18位模式下是怎么被分类的。终端节点标识ID502不会被实际LLM118向后存储。不过,普通节点504和被标记的节点506被实际LLM118向后存储。DFA指令404(图8A)包含终端节点的数目,存储在IW0RD3(图8A)中的Tsize,被标记节点的数目507,同样存储在IW0RD3(图8A)中的Msize
当DTE370转换图像500时,它们产生的结果字会作为异常条件出现。下一个节点指针是异常的MARKED,TERM或PERR。两个异常条件是:输入数据的完成和结果空间的清空。虽然对一个输入字节的图像转换可以产生多种异常条件,但是一个输入字节只能产生至多一个结果字。例如,最后一个输入字节会遇到输入数据条件的完成,会产生结果字。最后一个输入字节也可能遇到被标记的次节点,但是不会产生第二结果字。当(优先排序)PERR,TERM,输入数据的完成和结果空间清空的异常条件发生时,图像转换停止,DTE370报告最高优先性条件。例如,根据图2中的图像,下一个节点是到达节点‘c’的终端节点,DTE370终止图像转换。
每个DFA指令可以指定对保存在L2/DRAM中的数据进行怎样的处理。在任一种情况(直接或一起),DFA模块134从L2/DRAM(130/108)中读取字节。
图6显示了直接模式600取得将被DTE370处理的数据的实施例。DFA指令404直接指定开始位置和字节数。处理相应DFA指令404的DFA370从L2/DRAM(130/108)中读取相临的字节并处理它们。
图7显示了集合模式700取得将被DTE370处理的数据的实施例。DFA指令404直接指定开始位置和DFA集合指针710列表的大小。每个DFA集合指针710列表条目指定开始位置和DTE370要处理的字节数目。DTE370的所有输入字节流是每个集合指针列表条目指定字节的连接。
图7B显示64位DFA集合指针710的格式。DFA集合指针710包括长度712(字节)和地址段714(L2/DRAM地址)。DFA集合指针710是在64位边界自然对准的,但是它指向的L2/DRAM中的字节可以是任何字节对准。在集合模式700下,字节总数是所有DFA集合指针710中的长度字段之和。
再根据图4A,每个DFA指令404提供DFA模块134需要的信息用以:(i)开始DTE370;(ii)读取输入数据;(iii)转换LLM118中的图像200;(iv)写入结果。DFA指令404可以包含多个指令字,例如图8A中例举的指令格式。每个DFA指令404包含4个独立的字455’,455”,455,455””(通常455)。每次字包含64位,代表了二级缓冲存储器130或DRAM108中全部的32字节。优选的是,每个DFA指令404在32位字节边界是自然对准的。DFA指令404被分配后由DTE370进行处理。DFA指令404包含标识输入字节位置和结果位置的字段。
在操作中,当DFA指令队列382具有有效的DFA指令404时,DFA模块134从二级缓冲存储器130或DRAM108中读取DFA指令404和输入数据,然后在创建它们的时候(例如,一个一个字节的)写入结果。DFA模块134也可以在完成后选择性地提交将被POW148(图1B)分配的工作队列条目,所以DFA指令404可以包含用于工作队列指针的字段。
更详细的,第一DFA指令字455’包含开始节点标识ID460指示将被它第一节点使用的特定DFA图像。第一字404也提供附加信息,例如副本字段462,该副本字段462存储与被存储在LLM118中的标识的图像的副本数量相对应的副本数值。也可以提供类型值464,指示使用地址的类型(18或36位)。典型的64位字也可以包含一个或更多的保留字段。
第二DFA指令字455”包含长度字段470,指示DFA模块要处理的字节的数量和地址段474,指示二级缓冲存储器130或DRAM108中需要处理的分组数据的位置。
第三DFA指令字455包含结果地址段482,指示任何结果要写入的地址(例如,在二级缓冲存储器130或DRAM中的地址),和一个最大结果字段480,指示保存最大允许的结果数的值。更进一步,DFA模块134也可以在完成后选择性的提交工作队列条目,因此DFA指令404包含工作队列处理(WQP)段490,用于一个或更多工作队列指针。
图8B显示的是DFA指令404的结果格式800。DFA结果800在L2/DRAM(130/108)中有两个或更多64位字。每个字在L2/DRAM(130/108)中自然排列。在对DFA指令404的处理中和处理后,DFA模块134将这些字写入L2/DRAM(130/108)。这个结构是可变长度以适应等于可变数量的标记节点的DFA指令404,但是结果的长度可以被DFA指令字段的最大结构数限制。
如上所述,通过使用36位指针518提供的类型字段(图5A),节点类型与DFA图像的一个或多个节点联系成为可能。当DTE370转换图像时,它们产生结果字异常条件出现。至少一个异常条件是终端节点。当DTE370遇到终端节点时,它记录DFA图像已经到达结尾,DTE370运行的转换会停止。另一个异常条件的例子是标记节点。跟终端节点相比,当DTE370遇到标记节点时图像的转换不需要停止。然而,结果会被写到输出字中,指出特殊标记的节点为以后分析。因此,当图像中相应的节点被转换时,标记的节点可以用来区分。
注意,DFA模块134可能会不只一次写操作DFA结果800中的字0。只有最后一次写入字0会包含有效的DFA结果800。虽然DFA模块134可以多次写操作字0,但仅仅最后一次写操作可以设置位16,位16只有DFA模块完成DFA指令404后才能被设置。在提交DFA指令404到DFA模块134之前通过设置结果中字0中的位16为零,软件可以轮询字0的位16以确定DFA模块134何时完成DFA指令。当DFA的字0的位16被设置,整个结果就出现了。
图2B中图示的另外一个实施例,图2A的图像是要查找两个不同的字符串‘abed’和‘abce’的一个或多个的出现次数。因此,两个额外节点,节点4和5,增加到了图2A中,一个节点分别用于每个字符串的第四个字符(例如,节点4用于d,节点5用于e)。节点4和5都连接到节点3,如图,每个字符串的前三个字符是相同的。优选的,在输入字符串中每个字符串的出现都会标注上一个“pass”。
可仿效的输入字符串,比如字符串‘xwabcd454abceabcdsfk’通过一遍,DFA生成三个“已标记”过渡。标记的过渡发生在输入字符串结尾段(例如,在‘d’或‘e’出现的每个位置)。因此,三个标记的过渡指出三个字符串发现的位置。第一个和最后一个标记显示从节点3到节点4的过渡,指出在输入字符串中字符串‘abed’的存在(例如,DTE byte=5,previous 3,next 4 and DTEByte 17,previous=3,next=4)。中间标记的节点显示了从节点3到节点5的过渡,指出在输入字符串中字符串‘′abce′的存在(例如,DTE Byte=13,previous=3,next=5)。使用18位的指针,节点4和5被标记。使用36位的指针,从节点3到4和5的弧线被标记。因此,通过使用DFA标记技术结合DFA线程引擎,在单独输入通道中,可以在相同的输入字符串中查找到多个不同字符串的存在和位置。
本发明相关资料:2004年9月10日提交的美国第60/609,211号临时专利;2004年12月28日提交的美国第11/024,002号临时专利;2005年4月8日提交,文章名为“Deterministic FiniteAutomata(DFA)Instruction”的美国第60/669,603号临时专利;2005年4月8日提交,文章名为“Selective Replication of DataStructures”的美国第60/669,655号临时专利。上述申请的全部教导通过认证在此并入本文。
虽然本发明已经对关于其优选的实施方式进行了具体的描述和介绍,但本领域技术人员应当理解,在不脱离本发明所附权利要求保护的范围的情况下,本发明在形式和细节上可以进行多种改变。

Claims (18)

1.一种网络处理器,包括:
至少一个处理器内核;以及
确定性有限自动机(DFA)模块,异步操作至少一个处理器内核,该DFA模块越过存储在带有存储在连贯缓冲存储器中的分组数据的非缓冲存储器中的至少一个DFA图表的多个节点以响应来自至少一个处理器内核中的指令。
2.根据权利要求1所述的网络处理器,DFA模块包括:
适于访问存储DFA图表的存储器的非缓冲存储控制器;
至少一个DFA线程引擎与非缓冲存储控制器保持通讯;
指令输入逻辑用来设定从至少一个处理器内核到至少一个DFA线程引擎的指令。
3.根据权利要求2所述的网络处理器,进一步包括指令队列,至少一个处理器内核将与DFA模块相关的DFA指令提交到指令队列中。
4.根据权利要求3所述的网络处理器,DFA模块保持指向指令队列的指针。
5.根据权利要求3所述的网络处理器,DFA指令标示要使用的存储在连贯缓冲存储器中的分组数据和用于越过的存储在非缓冲存储器中的至少一个DFA图像。
6.根据权利要求3所述的网络处理器,DFA模块分配DFA指令给至少一个DFA线程引擎。
7.根据权利要求6所述的网络处理器,其中至少一个DFA线程引擎:
取得存储在连贯缓冲存储器中的分组数据;
每字节从连贯缓冲存储器中接收的分组数据发布非缓冲存储器加载指令用以转换存储在非缓冲存储器中的DFA图像的下一个状态;以及
将中间的和最终结果写到连贯缓冲存储器中。
8.根据权利要求7所述的网络处理器,还包括中间的和最终结果被写到其中的结果字。
9.根据权利要求8所述的网络处理器,其中结果字当设置时包括指示DFA指令完成的指令完成字段。
10.根据权利要求1所述的网络处理器,其中DFA模块方面包括:
关联在具有至少一个处理器内核的共享配置中的多个DFA线程引擎,每个DFA线程适于转换存储在非缓冲存储器中的至少一个DFA图像。
11.根据权利要求1所述的网络处理器,进一步包括节点类型标识符用于标识DFA图像的节点的类型。
12.根据权利要求11所述的网络处理器,节点类型标识符是标记的节点,图象的标记节点不受阻碍转换的转换。
13.一种转换具有进入的分组数据转换的DFA图像的方法,其包括:
存储至少一个DFA图像到非连贯缓冲存储器中;
存储DFA指令到连贯缓冲存储器中,DFA指令指示要使用的存储在连贯缓冲存储器中的分组数据和要转换的存储在非缓冲存储器中的至少一个DFA图像;
使用存储的分组数据转换DFA图像并将中间和最终结果写入连贯缓冲存储器。
14.根据权利要求13所述的方法,其中至少一个处理器内核提交DFA指令到DFA模块。
15.根据权利要求13所述的方法,其中DFA模块分配DFA指令到至少一个DFA线程引擎。
16.根据权利要求15所述的方法,其中至少一个DFA线程引擎:
取得存储在连贯缓冲存储器中的分组数据;
每字节的从连贯缓冲存储器中取得的分组数据分配一个非缓冲存储器加载指令;
越过与取得的每字节分组数据相对应的存储在非缓冲存储器中的DFA图像的下一个状态;以及
将中间和最终结果写入连贯缓冲存储器。
17.根据权利要求16所述的方法,进一步包括为标识DFA图像中每个节点各自的节点类型提供的节点类型标识符,通过节点类型标识符决定中间和最终的结果。
18.网络处理器,所述的网络处理器包括:
用于将至少一个DFA图象存储到连贯非缓冲存储器中的装置;
用于将DFA指令存储到连贯缓冲存储器中的装置,改DFA指令指出存储在连贯缓冲存储器中的分组数据用以使用以及用于越过的存储在非缓冲存储器中的至少一个DFA图象;以及
使用存储的分组数据越过DFA图象的装置,该装置将中间和最终结果写入连贯缓冲存储器。
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CN100533372C (zh) 2009-08-26
CN101040256A (zh) 2007-09-19
US7941585B2 (en) 2011-05-10
US20060059310A1 (en) 2006-03-16
CN101036117B (zh) 2010-12-08
CN101128804A (zh) 2008-02-20
CN101069170A (zh) 2007-11-07
US20060059286A1 (en) 2006-03-16
CN101069170B (zh) 2012-02-08
CN101053234B (zh) 2012-02-29
CN101036117A (zh) 2007-09-12
US20060059316A1 (en) 2006-03-16
US20140317353A1 (en) 2014-10-23
CN101128804B (zh) 2012-02-01

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