CN101061587A - 应变全耗尽绝缘层上覆硅半导体装置及其制造方法 - Google Patents

应变全耗尽绝缘层上覆硅半导体装置及其制造方法 Download PDF

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CN101061587A
CN101061587A CNA200580035899XA CN200580035899A CN101061587A CN 101061587 A CN101061587 A CN 101061587A CN A200580035899X A CNA200580035899X A CN A200580035899XA CN 200580035899 A CN200580035899 A CN 200580035899A CN 101061587 A CN101061587 A CN 101061587A
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相奇
N·苏巴
W·P·麦斯扎拉
Z·克里沃卡皮克
M-R·林
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Abstract

本发明提供一种在其上具有绝缘体(104)的半导体衬底(102)，其中该绝缘体(104)上有半导体层(106)。形成深沟隔离区(108)，将应变导引入至该半导体层(106)。在该半导体层(106)上形成栅极电介质(202)与栅极(204)。围绕着该栅极(204)形成间隔体(304)，且将在该间隔体(304)外部的半导体层(106)与绝缘体(104)除去。在该间隔体(304)外部形成凹入式源极/漏极(402)。

Description

应变全耗尽绝缘层上覆硅半导体装置及其制造方法
技术领域
本发明大致是关于绝缘层上覆硅(silicon-on-insulator)半导体装置，尤其是指全耗尽绝缘层上覆硅晶体管。
背景技术
目前电子产品几乎应用于生活中的各个层面，而该些电子产品的心脏即是集成电路。集成电路应用于飞机、电视到手表的各种产品上。
以极复杂系统，需要数百甚至是数千个精密控制的程序的协调，在硅晶圆内或硅晶圆上制作集成电路，而得一完成的半导体晶圆。每一完成的半导体晶圆有数百至数万个集成电路，而每一晶圆价值数百或数千美元。
集成电路由数百至数百万个独立组件所构成。一种常用的组件即为半导体晶体管。目前最常使用且重要的半导体技术，是以硅为基础，而最佳以硅为基础的半导体装置即为互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)。
互补金属氧化物半导体晶体管的主要组件，通常由具有氧化物浅沟隔离区，用以隔离晶体管区的硅衬底组成。硅衬底上，晶体管区于氧化硅栅极或栅极氧化物上含有复晶硅(polysilicon)栅极。稍微掺杂复晶硅栅极两侧的硅衬底使具导电性。该些硅衬底稍微掺杂的区域称为″浅源极/漏极″，由该复晶硅栅极下面的沟道区隔开。复晶硅栅极侧边的弯曲氧化硅或氮化硅间隔体(spacer)，称为″侧壁间隔体(sidewallspacer)″，可使另外的掺杂沉积而形成浅源极/漏极的更重度掺杂区，称为″深源极/漏极(deep S/D)″。
将氧化硅介电层沉积以覆盖复晶硅栅极、弯曲间隔体与硅衬底，以完成晶体管的制作。为提供晶体管的电性连接，在复晶硅栅极与源极/漏极的氧化硅介电层蚀刻开孔。该些开孔以金属填充而形成电性接触。为完成集成电路的制作，将该些接触连接至另外的介电材料层中的另外线路层，使达至该介电材料外部。
一种改进互补金属氧化物半导体晶体管的方法，使用绝缘衬底，称为绝缘层上覆硅(silicon on insulator，SOI)。互补金属氧化物半导体与高速场效晶体管(field effect transistors，FETs)使用绝缘衬底的优点，包括消除闭锁现象(latch-up immunity)、提高辐射抵抗力(radiationhardness)、降低寄生接面电容、降低接面漏电流以及降低短沟道效应。该些优点许多可转成增加场效晶体管的速度性能。
绝缘层上覆硅场效晶体管于半导体衬底上譬如硅衬底上，制成具有譬如二氧化硅的绝缘体。整个场效晶体管，包括其源极接面、沟道、漏极接面、栅极、欧姆接触与接线沟道，形成于绝缘体的硅岛上，且与任何固定电位隔绝。此会导致所谓的″浮体(floating body)″问题，因为该浮体或沟道区的电位漂浮，并可获得能干扰场效晶体管正常功能的电位的缘故。因为半导体衬底对沟道而言呈现漂浮，所以浮体问题导致高的漏电流与寄生双极作用。此问题不利于阈值电压(thresholdvoltage)的控制与电路操作。
为了解决浮体问题，需要将硅岛完全耗尽(deplete)。此意味当场效晶体管处于不导通状态(off state)与二接面皆接地时，使硅岛薄至让整个浮体区域厚度缺乏大多数载子的程度。为了完全耗尽该硅岛并产生全耗尽绝缘层上覆硅(fully depleted silicon on insulator，FDSOI)，已发现须使硅岛变得非常薄。
然而，薄硅岛于制造全耗尽绝缘层上覆硅互补金属氧化物半导体(FDSOI CMOS)中，形成具有低寄生串联电阻的源极与漏极时，会产生问题。一个解决方法是将源极与漏极提升至该薄硅岛上。以选择性外延生长(selective epitaxial growth，SEG)的方式，形成提升的源极与漏极。但不幸地，于极薄的硅岛上，很难均匀地生长出高品质、单晶的源极与漏极。此外，在选择性外延生长前，进行诸如氧化、预清理(pre-clean)与氢气焙烤制程时，会除去所有或部份的选择性外延生长所需的薄硅。
制造FDSOI CMOS的另一重要课题为改善性能之机制。改善性能之一种方法是将拉伸应变或压缩应变导引入至沟道。沿着电流流动方向的拉伸应变，增加了电子与电洞的移动性。另一方面，压缩应变增加了电洞的移动性但使电子的移动性降低。藉沟槽隔离区的充填而将应变导引入至沟道。然而，FDSOI CMOS的制造，传统上系使用没有沟槽蚀刻与充填的平台式隔离。
因此，当于沟道产生应变时，需要一种能均匀生长高品质、单晶源极与漏极的方法。
如何克服上述该些问题已为人们长期探讨，但先前的开发并未教示或建议任何解决方案，所以，熟悉本领域者已长期盼望有解决该些问题的方法。
发明内容
本发明提供一种在其上具有绝缘体的半导体衬底，且该绝缘体上有半导体层。形成深沟隔离区，在该半导体层产生应变。在该半导体层上形成栅极电介质与栅极。围绕该栅极形成间隔体，并将该间隔体外部的该半导体层与该绝缘体移除。在该间隔体外部形成凹入式(recessed)源极/漏极。
本发明某些实施例具有除以上所述之外，或替代以上所述的其它优点。对熟悉本领域者，阅读以下详细的说明并参考附图后，这些优点将变得很明显。
附图说明
图1为全耗尽绝缘层上覆硅半导体晶圆的剖面图；
图2显示图1的结构上形成有栅极；
图3显示图2的结构上沉积有线性区与间隔体；
图4显示依据本发明的实施例的具有凹入式源极/漏极的图3构造；
图5显示依据本发明的实施例的进行硅化后的图4构造；
图6显示依据本发明的另一实施例的具有接触蚀刻停止层的图5构造；以及
图7为依据本发明的制造应变全耗尽绝缘层上覆硅半导体装置的方法的流程图。
具体实施方式
以下说明将提供许多明确的细节，使能充分了解本发明。然而，本发明很显然地，得于无该些明确细节下施行。为了避免模糊本发明，一些习知装置组态与制程步骤将不再详细叙述
同样地，显示装置实施例的图形，是半示意式而非按比例绘制，特别是某些图中的尺寸，为使说明清晰而过份放大。
本说明书中所用″水平面(horizontal)″一词，定义成与衬底或晶圆平行的平面。″垂直″一词，指与如前项所定义的水平面垂直的方向。其它用语诸如″上″、″以上(above)″、″以下(below)″、″底部″、″顶部″、″侧(如″侧壁″)、″较高″、″较低″、″之上(over)″、″之下(under)″，皆指相对于水平面而言。
本说明书中所用″加工(processing)″一词，在形成所述构造时，所需步骤包括：材料或光阻之沉积、图案化、曝光、显影、蚀刻、清理(cleaning)以及/或是除去该材料或光阻。
图1显示全耗尽绝缘层上覆硅(FDSOI)晶圆100的剖面图，包括譬如为p掺杂硅(Si)之材料的半导体衬底102。半导体衬底102顶部上有埋入氧化层(buried oxide layer，BOX)104，该埋入氧化层104系譬如二氧化硅(SiO2)之材料的绝缘层；以及硅薄层的沟道层106。
为了控制具有25纳米(nm)或更小栅极长度的45纳米及45纳米以下节点的短沟道效应，已发现沟道层106厚度必须薄于100埃()。
将间隔开的位于凹入式源极/漏极402外部(见图4)的深沟隔离区(deep trench isolation，DTI)108，加至全耗尽绝缘层上覆硅晶圆100。形成具有深沟蚀刻(蚀刻穿过沟道层106、埋入氧化层104并进入衬底102)的深沟隔离区108。为保持装置的隔离，深沟隔离区的深度必须大于凹入式源极/漏极402(见图4)。在产生的深沟填入譬如SiO2之材料的介电质，以完成深沟隔离区108的制作。
图2显示图1的结构经习用沉积、图案化、光刻以及蚀刻制程后，而形成由诸如SiO2、氮氧化硅(silicon oxynitride，SiON)或氮化硅(Si3N4)之材料所构成的栅极电介质202，以及由诸如可能经掺杂或未掺杂的复晶硅或非晶硅(amorphous silicon)之材料所构成的栅极204。
图3显示经进一步加工后的图2构造。深沟隔离区108的凹入蚀刻(recess etch)制备用以于深沟隔离区108内形成间隔体之晶圆100。材料譬如为SiO2的线性区302系沉积于栅极204、沟道层106与深沟隔离区108上。材料譬如为Si3N4的间隔体304系围绕线性区302的栅极部分且在深沟隔离区108内形成。
制造FDSOI CMOS的重要课题之一，即形成具有低寄生串联电阻的源极与漏极。一个解决方法是将源极与漏极提升。通过选择性外延生长能形成提升的源极与漏极。不幸地，在极薄的硅岛上，如沟道层106上，很难均匀地生长出高品质、单晶的源极与漏极。此外，在选择性外延生长前，进行诸如氧化、预清洁与氢气焙烤制程，能除去所有或部份的选择性外延生长所需的薄硅。
图4显示依据本发明之实施例之加工后的图3构造。凹入式源极/漏极402已加至全耗尽绝缘层上覆硅晶圆100。沟道层106已被蚀刻而形成沟道404。
为形成凹入式源极/漏极402，而应用适当的制程譬如蚀刻，以穿过位于栅极204与深沟隔离区108间的沟道层106与埋入氧化层104。已发现100至600的薄埋入氧化层104提供最佳的厚度。然后在衬底102之表面与沟道404的侧壁上进行选择性外延生长(SEG)。此确保即使当沟道层106的硅可以部分或甚至全部为前面制程消耗时，凹入式源极/漏极402的选择性外延生长具有连续、高品质的硅表面。
当克服薄硅上选择性外延生长的问题时，产生的结构保有提升源极/漏极的优点，譬如低寄生串联电阻。于此阶段，藉凹入式源极/漏极402之选择性外延生长的修改能使性能改善。
图5显示依据本发明之实施例之进一步加工后的图4构造。于栅极204与源极/漏极402上进行硅化反应以生成NiSi层504。
应明了形成凹入式源极/漏极402与深沟隔离区108的次序系可变化，且以上所述顺序是为了方便的缘故。凹入式源极/漏极402能于凹入式源极/漏极402选择性外延生长期间或藉由离子植入与快速热回火(thermal anneal)而就地(in situ)形成。经应变处理的沟槽充填介电质，深沟隔离区108将应变导于沟道404，且适合做为晶体管间的隔离。
将拉伸应变或压缩应变导入于FDSOI CMOS装置的沟道以改善性能。沿着电流流动方向的拉伸应变，使NMOS中之电子与电洞移动性皆增加。另一方面，压缩应变藉增加电洞移动性而改善PMOS的性能。如此一来，施加适当应变至沟道404大幅增加沟道移动性，结果藉由显著部分的移动性增加，而使驱动电流提高。
已发现于FDSOI PMOS晶体管中，通过硅锗(silicon germanium，SiGe)的选择性外延生长，能进一步改善应变。如此一来，凹入式源极/漏极402的SiGe有效地于FDSOI PMOS晶体管的沟道404中产生应变。因为凹入式源极/漏极402紧邻沟道404，并导入比能导入提升的源极/漏极中之应变更多的应变，因此亦使该应变更有效。
此外，已发现在FDSOI NMOS晶体管中，通过碳化硅(siliconcarbide，SiC)的选择性外延生长，能进一步改善应变。如此一来，凹入式源极/漏极的SicC有效地在FDSOI NMOS晶体管的沟道404中产生应变。因为凹入式源极/漏极402紧邻沟道404，并能导入比能导入提升的源极/漏极中之应变更多的应变，因此亦使该应变更有效。
以上应变控制能施行做为从深沟隔离区108之应变控制的辅助(adjunct)，或做为凹入式源极/漏极402形成前，深沟隔离区108形成的基本控制。
图6显示依据本发明之另一实施例之进一步加工后的图5构造。经蚀刻步骤已将间隔体304(见图5)且深沟隔离区108(见图5)之介电质充填物移除，留下沟槽602。蚀刻后，接触蚀刻停止层604沉积在沟槽602中且在源极/漏极402、线性区302与栅极204之上。沟槽602中的接触蚀刻停止层604将另外的应变导入沟道404。
图7显示依据本发明之制造应变全耗尽绝缘层上覆硅半导体装置的方法700的流程图。方法700包括于步骤702中，提供其上具有绝缘体的半导体衬底，其中该绝缘体上具有半导体层；在步骤704中，在该半导体层上形成栅极电介质与栅极；在步骤706中，在间隔体外部形成间隔开的深沟隔离区，并将应变导引入至该半导体层；在步骤708中，围绕该栅极形成间隔体；在步骤710中，除去该间隔体外部的该半导体层与该绝缘体；以及在步骤712中，在该间隔体外部形成凹入式源极/漏极。
如此，已发现本发明的半导体装置与制造方法，对FDSOI CMOS提供重要且迄今为止尚未为人所知或使用的解决方法、能力与功能上的优点。该所得之制程与组态系直接、经济、不复杂、高度弹性、精确、灵敏及有效，且能适用于习知组件而容易去制造与应用。
参照特定的最佳实施例，本说明书已经对本发明进行揭示。应明了，许多的改变、修饰与变化对熟悉本领域者而言，以上的说明将使其变得很明显。因此，所有该些改变、修饰与变化皆涵盖于以下的申请专利范围内。本说明书中所揭示的内容或显示的附图是用于解释本发明，而非用于限制本发明的范畴。

Claims (10)

1.一种制造半导体装置的方法(700)，包括下列步骤：
提供在其上具有绝缘体(104)的半导体衬底(102)，该绝缘体(104)上有半导体层(106)；
形成深沟隔离区(108)，将应变引入至该半导体层(106)；
在该半导体层(106)上形成栅极电介质(202)与栅极(204)；
围绕该栅极(204)形成间隔体(304)；
除去在该间隔体(304)外部的该半导体层(106)与该绝缘体(104)；以及
在该间隔体(304)外部形成凹入式源极/漏极(402)。
2.如权利要求1所述的方法(700)，其中，在该间隔体(304)外部形成凹入式源极/漏极(402)的步骤进一步包括通过选择性外延生长在该间隔体(304)外部形成凹入式源极/漏极(402)。
3.如权利要求1所述的方法(700)，其中，在该间隔体(304)外部形成凹入式源极/漏极(402)的步骤进一步包括在该间隔体(304)外部形成凹入式碳掺杂的硅源极/漏极(402)，将应变引入至该半导体层(106)。
4.如权利要求1所述的方法(700)，其中，在该间隔体(304)外部形成凹入式源极/漏极(402)的步骤进一步包括在该间隔体(304)外部形成凹入式硅锗源极/漏极(402)，将应变引入至该半导体层(106)。
5.如权利要求1所述的方法(700)，另外包括：
除去该间隔体(304)；
除去该深沟隔离区(108)，留下沟槽(602)；以及
在该沟槽(602)中、该凹入式源极/漏极(402)上及该栅极(204)上沉积层(604)，将应变引入至该半导体层(106)。
6.一种半导体装置，包含：
在其上具有绝缘体(104)的半导体衬底(102)，该绝缘体(104)上有半导体层(106)；
在该半导体层(106)上的栅极电介质(202)与栅极(204)；
可选的围绕该栅极(204)的间隔体(304)；
在该间隔体(304)外部的凹入式源极/漏极(402)；以及
在该间隔体(304)外部的间隔开的沟槽(602)，可选地作为深沟隔离区(108)将应变引入至该硅层。
7.如权利要求6所述的半导体装置，其中，在该间隔体(304)外部的该凹入式源极/漏极(402)进一步包含通过选择性外延生长形成在该间隔体(304)外部的凹入式源极/漏极(402)。
8.如权利要求6所述的半导体装置，其中，在该间隔体(304)外部的该凹入式源极/漏极(402)进一步包含将应变引入至该半导体层(106)的在该间隔体(304)外部的凹入式碳掺杂的硅源极/漏极(402)。
9.如权利要求6所述的半导体装置，其中，在该间隔体(304)外部的该凹入式源极/漏极(402)进一步包含将应变引入至该半导体层(106)的在该间隔体(304)外部的凹入式硅锗源极/漏极(402)。
10.如权利要求6所述的半导体装置，另外包含将应变引入至该半导体层(106)的在该沟槽(602)中、该凹入式源极/漏极(402)上以及该栅极(204)上的层。
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