CN101065811B - 制造隧穿纳米管场效应晶体管的方法 - Google Patents
制造隧穿纳米管场效应晶体管的方法 Download PDFInfo
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Abstract
一种制造隧穿纳米管场效应晶体管的方法，包括在纳米管中形成被所述晶体管的未掺杂沟道区分隔的n掺杂区和p掺杂区。为所述掺杂区和栅电极提供电接触，所述栅电极形成在沉积于所述晶体管的至少部分所述沟道区上的栅极介质层上。
Description
技术领域
本发明一般涉及在半导体衬底上制造器件的方法。更具体地说，本发明涉及在半导体衬底上制造隧穿纳米管场效应晶体管的方法。
背景技术
通常，在半导体衬底上制造微电子器件作为集成电路。互补金属氧化物半导体(CMOS)场效应晶体管是集成电路中的核心元件之一。为了获得集成电路的更高性能和封装密度，COMS晶体管的大小和工作电压连续减小或按比例减小。尤其是，在这类晶体管中阈值电压Vth(即为使晶体管开通所需的电压)减小。
可以通过本领域中被称为反亚阈值斜率(inverse sub-threshold slope)的参数，说明CMOS晶体管的开关特性，该反亚阈值斜率测量将经过器件的电流改变一个数量级所需的栅极电压。在常规CMOS晶体管中，反亚阈值斜率约为60mV/十(decade)，且为了降低阈值电压Vth，需要减小晶体管的开通和关断状态下输出电流之间的差异。过小的开通/关断电流比会阻止包括这些晶体管的数字电路的正常工作，因此被视为是最终缩放器件中的主要挑战之一。
由此，本领域中需要一种制造场效应晶体管的改进方法。
发明内容
在一个实施例中，本发明公开了一种制造隧穿纳米管场效应晶体管的方法。所述方法包括在纳米管(或纳米线，即没有轴向开口的纳米管)中形成被所述晶体管中的未掺杂沟道区分隔的n掺杂区和p掺杂区。为所述掺杂区和栅电极提供电接触，所述栅电极形成在沉积于所述晶体管的沟道区上的栅极介质层上。
本发明的另一方面是一种使用本发明的方法制造的隧穿纳米管场效应晶体管。该晶体管可以用作n型晶体管器件或p型晶体管器件。
附图说明
通过结合附图考虑下面的详细说明，可以容易地理解本发明的内容，其中：
图1示出了根据本发明一个实施例制造隧穿纳米管场效应晶体管的方法的流程图；
图2示出了使用图1的方法所制造的示例性隧穿纳米管场效应晶体管的示意图；
图3示出了将图2的晶体管用作p型晶体管器件的示例性电路结构；
图4示出了将图2的晶体管用作n型晶体管器件的示例性电路结构；
图5示出了示例性曲线图，示例了图2的晶体管的纳米管材料中导带和价带分布；以及
图6-8示出了示例性曲线图，示例了图2的晶体管的特性。
为了便于理解，只要有可能，使用相同的参考标号表示各图共用的相同的元件。
然而，应注意，附图仅仅示例了本发明的示例性实施例，因此不被认为限制本发明的范围，因为本发明允许其它等效的实施例。
具体实施方式
本发明是一种使用纳米管的选择性掺杂部分来制造隧穿纳米管场效应晶体管的方法。这里，术语“纳米管”可互换地用于纳米管和纳米线(即没有轴向开口的纳米管)。该方法可以用于制造超大规模集成(ULSI)电路和器件。
图1示出了作为方法100的制造隧穿纳米管场效应晶体管的本发明方法的一个实施例的流程图。该方法100包括在衬底上进行的处理步骤，在其中制造至少一个隧穿纳米管场效应晶体管。在一个示例性实施例中，按照所示出的次序顺序进行这些处理步骤。在可选实施例中，可以同时或按照不同的次序，进行至少两个处理步骤。常规子工艺例如光刻掩模或牺牲和保护层的施加和去除、清洁工艺等是本领域公知的，在图1中没有示出。
图2示出了使用图1的方法所制造的示例性隧穿纳米管场效应晶体管200的示意图。为了示例的目的，图2中的图形并没有按照比例绘制，且进行了简化。为了最好地理解发明，读者应同时参考图1和图2。
方法100始于步骤101，进而进行步骤102。在步骤102，在例如硅(Si)或玻璃晶片等的衬底(未示出)上，形成具有半导体特性的纳米管202。使用这样的纳米管可以获得最好的效果，在所述纳米管中，电荷载流子(即电子和空穴)具有最小和相似的有效质量(例如，小于约0.1m0，其中m0是自由电子质量)以及最小的截面尺寸，并便于电荷转移的弹道机制。在例如共同指定的于2002年3月20日提交的美国专利申请序列号10/102,365中公开了适于形成这种纳米管的方法，这里引入其内容作为参考。在一个示例性实施例中，纳米管202是其外径214不大于约5nm(优选地，从约1至3nm或更小)且其长度216为约25至1000nm的碳(C)纳米管。在可选实施例中，可以使用由其它材料(例如，硅或化合物半导体，例如砷化镓(GaAs)、磷化铟(InP)、砷化铟镓(InGaAs)等)构成的半导体纳米管制造晶体管200。
在步骤104，在纳米管202的中心区222内形成栅极介质层204。该区222可具有从5至200nm范围内的长度218，且代表所制造的晶体管200的本征沟道区。在一个示例性实施例中，栅极介质层204包括二氧化硅(SiO2)，且形成为约1至5nm的厚度。可选地，栅极介质层204可以由高介电常数(高k)材料，例如氧化铝(Al2O3)、二氧化铪(HfO2)等形成。在所示出的实施例中，栅极介质层204在整个中心区222内形成，且包裹(wrap)纳米管202。
在步骤106，在栅极介质层204上形成栅电极206。通常，栅电极206具有5至50nm的厚度，且可包括金属、金属合金或导电化合物中的至少一种。栅电极206的合适材料具有高电导率，并与栅极介质层204的材料和用于电布线(例如，铜(Cu)布线)的材料兼容，其中所述电布线将所制造的晶体管200与外部集成电路和器件互连(下面参考图3-4讨论)。在一个示例性实施例中，栅电极206由钛(Ti)形成。
栅极介质层204和栅电极206可以使用常规真空沉积技术，例如原子层沉积(ALD)、物理气相沉积(PVD)、化学气相沉积(CVD)、等离子体增强CVD(PECVD)、蒸发等形成。
在步骤108，通过使用至少一种n型掺杂剂选择性地掺杂区域220，在邻近沟道区222的纳米管202中形成第一漏极/源极区220。在一个示例性实施例中，第一漏极/源极区220的长度230为约10至400nm。在所示出的实施例中，第一漏极/源极区220从沟道区222延伸至纳米管202的第一端234。在可选实施例中，纳米管202的末梢部分236可以不被掺杂。合适的n型掺杂剂包括电子施主，例如钾(K)、钠(Na)、聚氮丙啶分子等，其中聚氮丙啶分子是聚合物，且在该意义上是分子长链。在纳米管的部分220被n掺杂时，可以通过例如使用抗蚀剂层、掩蔽层等保护纳米管的其它部分，以防止对纳米管的其它区域的掺杂。
在步骤110，通过使用至少一种p型掺杂剂选择性地掺杂区域224，在邻近沟道区222的纳米管202中形成第二漏极/源极区224。在一个示例性实施例中，第二漏极/源极区224的长度232为约10至400nm。在所示出的实施例中，第二漏极/源极区224从沟道区222延伸至纳米管202的第二端238。在可选实施例中，纳米管202的末梢部分240可以不被掺杂。合适的p型掺杂剂包括空穴施主，例如氯(Cl2)、溴(Br2)等。并且，在纳米管的部分224被p掺杂时，可以通过例如使用抗蚀剂层、掩蔽层等保护纳米管的其它部分，以防止对纳米管的其它区域的掺杂。
可以使用金属/分子沉积工艺，进行对第一漏极/源极区220和第二漏极/源极区224的选择性掺杂。掺杂剂通常是具有不同的电子或空穴亲和力的材料。在p和n型沉积工艺中，可以利用从各自的掺杂剂向纳米管的电荷转移，在区域220和224中掺杂纳米管202。
在步骤112，分别在第一漏极/源极区220、栅电极206和第二漏极/源极区224上，形成电接触208、210和212。接触208、210和212作为端子，以将晶体管200连接到外部集成电路和器件。在可选实施例中，栅电极206可以用作接触，因此，接触210是可选的。接触208、210和212可以由与各自下伏的和上覆的材料层兼容的至少一种导电材料(例如，金属、金属合金或导电化合物)形成。n接触(接触208)材料的功函数应小于p接触(接触212)材料的功函数。在一个示例性实施例中，使用常规真空沉积技术，由铝(Al)和钯(Pb)分别形成接触208和212，并由钛(Ti)形成接触210。
一旦步骤112完成，隧穿纳米管场效应晶体管200的制造完成。在步骤114，方法100结束。
在集成电路中，隧穿纳米场效应晶体管200可以用作n型晶体管器件或p型晶体管器件。
图3示出了将晶体管200用作p型晶体管器件的示例性电路结构300。在一个实施例中，电路结构300包括晶体管200、耦合到接触208的地电势或公共电势(即接地端子)的源302、耦合到接触212的漏极电压Vds源304和耦合到接触210的栅极电压Vgs源306。工作中，源304和306分别对接触212和210施加控制正电势(即负电压)，而电压Vds和Vgs等于或小于(即负电压)地电势。
图4示出了将晶体管200用作n型晶体管器件的示例性电路结构400。在一个实施例中，电路结构400包括晶体管200、耦合到接触212的地电势源302、耦合到接触208的漏极电压Vds源404和耦合到接触210的栅极电压Vgs源406。工作中，源404和406分别对接触208和210施加控制负电势(即正电压)，而电压Vds和Vgs等于或大于(即正电压)地电势。
图5示出了一系列的示例性曲线图，示例了晶体管200的纳米管材料中导带和价带分布(y轴502)对沿碳纳米管202的距离(x轴504)的依赖性。在所示出的实施例中，晶体管200包括其各自长度230和232约为10nm的第一和第二漏极/源极区220和224以及其长度218约为30nm的沟道区222。所示出的导带和价带曲线图涉及电路结构300，其中在对接触212施加的漏极电压Vds＝-0.1V下，且在从-0.2至-0.5V范围的栅极电压Vgs下，晶体管200用作p型器件。当第一漏极/源极区220中导带的下边界508位于晶体管的沟道区222中价带的上边界510之下时，晶体管200中电荷载流子的有效量子力学隧穿(即穿过晶体管的电荷载流子流)是可能的，由此在导带和价带之间形成了电势或垂直间隙512。如箭头506所示，在碳纳米管202中，在栅极电压Vgs≤-0.3V(例如在Vgs＝-0.5V)，价带和导带之间存在这样的有效隧穿。相应地，在Vgs＞-0.3V(例如在Vgs＝-0.2V)，价带和导带之间没有这样的间隙和有效隧穿。工作中，在Vgs≤-0.3V，p型晶体管200断定为开通(导通)态，相应地，在Vgs＞-0.3V，晶体管断定为关断(非导通)态。
图6示出了一系列的示例性曲线图，示例了输出电流Id(y轴602)对其SiO2栅极介质层204的厚度tox在3至30nm范围内的示例性p型晶体管200的栅极电压Vgs(x轴604)的依赖性。这些曲线图可以用于计算晶体管200的反亚阈值斜率S～dVgs/dlog(Id)。反亚阈值斜率S量度晶体管的开关特性，并确定使晶体管的输出电流Id变化一个数量级(例如，10)的栅极电压Vgs的差异。在其SiO2栅极介质层204的厚度tox＝3nm的晶体管200中，对于在0.1pA至0.1nA范围内的输出电流Id，反亚阈值斜率S约为16mV/十，而对于在1pA至1nA范围内的输出电流Id，反亚阈值斜率S约为27mV/十。因此，晶体管200显著胜过其反亚阈值斜率S～60mV/十的常规互补金属氧化物半导体(CMOS)场效应晶体管，同时其在与COMS晶体管相同的栅极电压Vgs下工作。
图7示出了一系列的示例性曲线图，示例了输出电流Id(y轴702)对在-0.1至-0.4V范围内的漏极电压Vds下其厚度tox＝3nm的图6的示例性p型晶体管200的栅极电压Vgs(x轴704)的依赖性。与其它p型晶体管器件相同，晶体管200的特性保持不变，且在负栅极电压Vgs下没有出现漏极感应势垒下降类(DIBL类)效应。
图8示出了一系列的示例性曲线图，示例了图2的p型晶体管200的输出特性。更具体地说，图8中的曲线示出了在-0.4至-0.7V范围内的栅极电压Vgs下，输出电流Id(y轴802)对漏极电压Vds(x轴804)的依赖性。晶体管200的输出特性具有在小的漏极电压Vds下的线性区806和在大的漏极电压下的饱和区808。
本发明的隧穿纳米管场效应晶体管具有有利的用于集成电路的特性结合：与低的反亚阈值斜率S结合的小占用面积(footprint)和最小的功率消耗，在漏极电压的宽范围内，该反亚阈值斜率S与漏极电压无关，且在低阈值电压和低栅极和漏极电压下可以实现。并且，隧穿纳米管场效应晶体管具有可与CMOS晶体管的兼容的输出特性，因此，可以与COMS晶体管一起或作为COMS晶体管的替代来用于集成电路中。
虽然上述内容旨在本发明的示例性实施例，但只要不偏离本发明的基本范围，可以对本发明的其它和更进一步的实施例进行修改，并且本发明的范围由下面的权利要求书确定。
Claims (30)
1.一种制造隧穿纳米管场效应晶体管的方法，包括：
提供具有半导体特性的纳米管；
在所述纳米管中限定所述晶体管的沟道区、第一漏极/源极区和第二漏极/源极区，所述第一漏极/源极区邻近所述沟道区的第一端，且所述第二漏极/源极区邻近所述沟道区的第二端；
在所述沟道区上形成栅极介质层；
在所述栅极介质层上形成栅电极；
使用n型掺杂剂选择性地掺杂所述第一漏极/源极区；
使用p型掺杂剂选择性地掺杂所述第二漏极/源极区；以及
在所述栅电极和所述漏极/源极区的每一者上形成至少一个电接触。
2.根据权利要求1的方法，其中所述纳米管没有轴向开口。
3.根据权利要求1的方法，其中所述纳米管是碳纳米管、硅纳米管和包括化合物半导体的纳米管中的一种。
4.根据权利要求3的方法，其中所述化合物半导体是砷化镓、磷化铟和砷化铟镓中的一种。
5.根据权利要求1的方法，其中所述纳米管的外径小于5nm。
6.根据权利要求1的方法，其中掺杂便于在所述沟道区中电荷载流子的有效量子力学隧穿。
7.根据权利要求1的方法，其中所述n型掺杂剂包括钾、钠和聚氮丙啶分子中的至少一种。
8.根据权利要求1的方法，其中所述p型掺杂剂包括氯和溴中的至少一种。
9.根据权利要求1的方法，其中使用金属/分子沉积工艺进行掺杂。
10.根据权利要求1的方法，其中所述栅极介质层由厚度为1至10nm的SiO2、HfO2和Al2O3中的至少一种形成。
11.根据权利要求1的方法，其中所述栅电极由金属、金属合金或导电化合物中的至少一种形成。
12.根据权利要求1的方法，其中至少一个电接触由金属、金属合金或导电化合物中的至少一种形成。
13.根据权利要求1的方法，其中使用真空沉积工艺形成所述栅极介质层、栅电极和至少一个电接触。
14.一种隧穿纳米管场效应晶体管，包括：
沟道区，限定在纳米管中，所述沟道区具有半导体特性；
栅极介质层，形成在所述沟道区上；
栅电极，形成在所述栅极介质层上；
第一漏极/源极区，形成在邻近所述沟道区的第一端的所述纳米管中，所述第一漏极/源极区被使用n型掺杂剂选择性地掺杂；
第二漏极/源极区，形成在邻近所述沟道区的第二端的所述纳米管中，所述第二漏极/源极区被使用p型掺杂剂选择性地掺杂；以及
在所述栅电极和所述漏极/源极区的每一者上的至少一个电接触。
15.根据权利要求14的晶体管，其中所述第一漏极/源极区耦合到地电势源，所述第二漏极/源极区耦合到漏极电压源，且所述栅电极耦合到栅极电压源，由此形成p型晶体管器件。
16.根据权利要求15的晶体管，其中在所述第二漏极/源极区和栅电极处的电压都等于或小于所述地电势。
17.根据权利要求14的晶体管，其中所述第二漏极/源极区耦合到地电势源，所述第一漏极/源极区耦合到漏极电压源，且所述栅电极耦合到栅极电压源，由此形成n型晶体管器件。
18.根据权利要求17的晶体管，其中在所述第一漏极/源极区和栅电极处的电压都等于或大于所述地电势。
19.根据权利要求14的晶体管，其中所述纳米管没有轴向开口。
20.根据权利要求14的晶体管，其中所述纳米管是碳纳米管、硅纳米管和包括化合物半导体的纳米管中的一种。
21.根据权利要求20的晶体管，其中所述化合物半导体是砷化镓、磷化铟和砷化铟镓中的一种。
22.根据权利要求14的晶体管，其中所述纳米管的外径小于5nm。
23.根据权利要求14的晶体管，其中掺杂便于在所述沟道区中电荷载流子的有效量子力学隧穿。
24.根据权利要求14的晶体管，其中所述n型掺杂剂包括钾、钠和聚氮丙啶分子中的至少一种。
25.根据权利要求14的晶体管，其中所述p型掺杂剂包括氯和溴中的至少一种。
26.根据权利要求14的晶体管，其中使用金属/分子沉积工艺进行掺杂。
27.根据权利要求14的晶体管，其中所述栅极介质层由厚度为1至10nm的SiO2、HfO2和Al2O3中的至少一种形成。
28.根据权利要求14的晶体管，其中所述栅电极由金属、金属合金或导电化合物中的至少一种形成。
29.根据权利要求14的晶体管，其中所述至少一个电接触由金属、金属合金或导电化合物中的至少一种形成。
30.根据权利要求14的晶体管，其中使用真空沉积工艺形成所述栅极介质层、栅电极和所述至少一个电接触。
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| WO2006073477A3 (en) | 2007-01-25 |
| JP5263755B2 (ja) | 2013-08-14 |
| EP1754262A4 (en) | 2012-03-14 |
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| WO2006073477A2 (en) | 2006-07-13 |
| EP1754262A2 (en) | 2007-02-21 |
| US7180107B2 (en) | 2007-02-20 |
| CN101065811A (zh) | 2007-10-31 |
| TW200603228A (en) | 2006-01-16 |
| JP2008500735A (ja) | 2008-01-10 |
| EP1754262B1 (en) | 2015-04-08 |
| US20050274992A1 (en) | 2005-12-15 |
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