CN101141129B - Voltage controlled oscillator circuit - Google Patents
Voltage controlled oscillator circuit Download PDFInfo
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- CN101141129B CN101141129B CN 200710163753 CN200710163753A CN101141129B CN 101141129 B CN101141129 B CN 101141129B CN 200710163753 CN200710163753 CN 200710163753 CN 200710163753 A CN200710163753 A CN 200710163753A CN 101141129 B CN101141129 B CN 101141129B
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Abstract
The utility model provides a voltage control oscillating circuit that consists of a ring shape oscillating circuit that consists of a plurality of delay circuit units that are connected in series, theoutput end of the ahead is electrically connected with the input end of the delay circuit unit so as to from a knot; a plurality of controlled delay circuit units, the input end of certain controlled delay circuit unit is electrically connected with the first knot and the second knot of the ring shape oscillating circuit, the amount of the delay circuit units possessed by the first and the second knot is the same, and each controlled delay circuit unit is controlled by a signal to switch between the on status and the off status so as to change the frequency of a plurality of oscillating signa ls that has different phases and are outputted by the knot. The invention can increase the property of the voltage controlling the oscillating circuit.
Description
Technical field
The present invention is a kind of voltage-controlled oscillator circuit, and finger is applied to the voltage-controlled oscillator circuit in the phase-locked loop clock pulse generator especially.
Background technology
See also Fig. 1, it is a phase-locked loop (Phase Locked Loop, abbreviation PLL) the function block schematic diagram of clock pulse generator (clock generator), it is mainly by phase (Phase/Frequency Detector, be called for short PFD) 1010, (Voltage C ontrol Oscillator, be called for short: VCO) element such as 1013 and one frequency divider 1014 constitutes for charge pump (charge pump) 1011, loop filter (Loop Filter) 1012, voltage controlled oscillator.Wherein the phase difference between the feedback clock signal just exported according to reference clock signal Fref and frequency divider 1014 of phase 1010 export represent two phase differences between clock signal go up number/count down signal, count/count down the conversion of signal and go up through charge pump 1011 and loop filter 1012, export a control voltage at last to voltage controlled oscillator 1013, make that the phase place of a clock pulse signal Fout of voltage controlled oscillator 1013 output can continue to reach consistent with phase place with reference to clock signal.
And in technological means now, there are many circuit can be used for finishing above-mentioned voltage controlled oscillator 1013, LC oscillator and ring oscillator (RingOscillator) or the like are for example arranged, and wherein ring oscillator is simple and the characteristics such as clock signal of a plurality of outs of phase can be provided because of simple in structure, element, therefore is widely used in finishing the voltage controlled oscillator on integrated circuit.And Fig. 2 is the function block schematic diagram of a traditional endless oscillator, it forms (n is the odd number more than or equal to three) by n digital inverter 21～2n serial connection usually, and each digital inverter is exported the output clock signal of out of phase respectively, and the frequency of each output clock signal is all 1/ (2 * n * τ), and τ is the time of delay (delay time) of an above-mentioned digital inverter.Therefore, as long as adjust the size of the supply voltage be supplied to digital inverter, the length of time of delay that just can corresponding control figure inverter, and then change the frequency f o of output clock signal Fo, so just can reach the function of a voltage controlled oscillator.
And can find out by above-mentioned explanation, the frequency size of clock signal that ring oscillator is exported is inversely proportional to numerical value n, but be directly proportional with the quantity of the output clock signal of available out of phase, therefore in the design of ring oscillator, the clock signal of generation high frequency is to conflict mutually with two requirements of the quantity of the output clock signal that increases out of phase.And be to improve this problem, the leggy ring oscillator with subloop shown in Fig. 3 a is just developed, its detailed content can be referring to L.Sun, T.A.Kwasniewski, A 1.25-GHz 0.35-μ m monolithic CMOS PLL basedon a multiphase ring oscillator, the explanation of IEEE J.Solid-State Circuits 36 (6) (2001) 910-916..Its main concept is that script n digital inverter M1～Mn serial connection is formed in the ring oscillator circuit of (n is the odd number more than or equal to three), add n interpolation inverter (interpolating inverter) S1～Sn again, and then set up the subloop that n has fast path, wherein X1～Xn represents n the circuit node between digital inverter M1～Mn, and i then represents the inverter number in this subloop.And be example with n=5, i=3, the function block schematic diagram of the 5 rank leggy ring oscillators as shown in Fig. 3 b just we can draw with subloop.And as can be seen from Figure, because the inverter number (3) in this subloop is few than the inverter number in the main feedback loop (5), and according to the physical characteristic of circuit, to divide the weighted sum (weighted sum) of other time of delay to decide by both the subloop and the time of delay of circuit after main feedback loop is in parallel, therefore the frequency of oscillation of circuit will be than the circuit height that does not have subloop among Fig. 3 b, and the quantity (5) that still can possess more out of phase output clock signal.But, requirement at operational frequency range increases now day by day, only can by to digital inverter time of delay length control change the practice of frequency of output clock signal, can't satisfy the demand of present circuit, and how to improve lacking and the operational frequency range of increase voltage controlled oscillator, is development main purpose of the present invention.
Summary of the invention
The present invention is a kind of voltage-controlled oscillator circuit, and it comprises: a ring oscillator circuit, and it is formed by a plurality of delay circuits unit serial connection, and the output of last delay circuit unit is electrically connected to the input of one delay circuit unit, back and forms a node; And a plurality of controlled delay circuit units, wherein the input of a controlled delay circuit unit and output are electrically connected to a first node and the Section Point in this ring oscillator circuit respectively, and the total quantity that includes the described controlled delay circuit unit that had on the subloop of this controlled delay circuit unit and the delay circuit unit in the described ring oscillator circuit between this first node and this Section Point is identical, and each controlled delay circuit unit is subjected to control signal control and switches between a conducting state and an off state, and then changes the frequency of a plurality of oscillator signals of the phase place inequality that described node exports.
The present invention provides a kind of voltage-controlled oscillator circuit in addition, it comprises: a ring oscillator circuit, it is formed by n delay circuit unit serial connection, and the output of wherein last delay circuit unit is electrically connected to the input of one delay circuit unit, back and forms a node, and n is the positive odd number greater than 1; And a plurality of controlled delay circuit units, wherein the input of a controlled delay circuit unit and output are electrically connected to a first node and the Section Point in this ring oscillator circuit respectively, and this first node, the described controlled delay circuit unit that is had on this Section Point and the formed subloop of this controlled delay circuit unit and the total quantity of the delay circuit unit in the described ring oscillator circuit all are all i and i less than n, because of the number of the delay circuit unit in the described ring oscillator circuit that inserting of described controlled delay circuit unit skipped over then for x and x less than n, and x, i, the pass of n is x=n-i+1, and each controlled delay circuit unit is subjected to control signal control and switches between a conducting state and an off state, and then changes the frequency of a plurality of oscillator signals of the phase place inequality that described node exports.
Voltage-controlled oscillator circuit of the present invention can improve the performance of voltage-controlled oscillator circuit.
Description of drawings
Fig. 1, it is the function block schematic diagram of a phase-locked loop clock pulse generator.
Fig. 2, it is the function block schematic diagram of a traditional endless oscillator.
Fig. 3 a, it is the function block schematic diagram with leggy ring oscillator of subloop.
Fig. 3 b, it is the function block schematic diagram with 5 rank leggy ring oscillators of subloop.
Fig. 4 a, it is that the present invention improves any means known disappearance to develop out function block schematic diagram about a voltage-controlled oscillator circuit.
Fig. 4 b, it is the function block schematic diagram with 7 rank leggy ring oscillators of subloop.
Fig. 5 a, it is the preferred embodiment circuit diagram of digital inverter of the present invention.
Fig. 5 b, it is the preferred embodiment circuit diagram of controlled inverter of the present invention.
Fig. 6, it is that the present invention develops the supply unit that cooperates running with this voltage-controlled oscillator circuit a functional circuit block schematic diagram.
Embodiment
The present invention must can get a more deep understanding by following graphic and explanation.
See also Fig. 4 a, it is that the present invention improves any means known disappearance to develop out function block schematic diagram about a voltage-controlled oscillator circuit, its main body is still the delay circuit unit of being made up of n digital inverter M1～Mn and is connected in series the ring oscillator circuit that forms, and n is the positive odd number greater than 1.The output of last digit inverter is electrically connected to the input of back one digital inverter and forms nodes X 1～Xn, and can take out the oscillator signal P1～Pn (this figure is not shown) of a plurality of outs of phase from nodes X 1～Xn respectively.Finish but then use the controlled delay circuit unit instead, for example the controlled inverter C1 shown in the figure～Cn in order to the element of setting up subloop.Wherein the input of arbitrary controlled inverter and output are electrically connected to a first node and the Section Point in the above-mentioned ring oscillator circuit respectively, all be all i and i less than n and include the delay circuit element number that is had on the subloop of this controlled inverter between this first node and this Section Point, skip over because of inserting of controlled inverter (pass over) digital inverter number then for x and x less than n, and the pass of x, i, n is x=n-i+1.To scheme is example, the input of controlled inverter C2 and output are electrically connected to a first node X2 and the Section Point Xx+2 in the above-mentioned ring oscillator circuit respectively, all are all i mutually and include the delay circuit element number that is had on the subloop of this controlled inverter C2 between this first node and this Section Point.As for Fig. 4 b then is to express n=7, i=5, and the example block schematic diagram of x=3 is made of C2, M6, M7, M1, M2 comprising the subloop system that controlled inverter C2 is arranged.
And above-mentioned described controlled inverter C1～Cn can be subjected to control signal control and switch between a conducting state and an off state, and then changes the frequency of the oscillator signal that this nodes X 1～Xn exported.For example as described controlled inverter C1～when Cn is in conducting state, subloop will play a role and allow entire circuit be operated in a first frequency, and as described controlled inverter C1～when Cn is in off state, subloop can not move and allow entire circuit be operated in a second frequency, and wherein first frequency is greater than second frequency.With Fig. 4 b is example, when C1～Cn is in conducting state, subloop with five delay circuit element number will play a role and allow entire circuit be operated in first frequency, and when C1～Cn is in off state, subloop can not move and allow the entire circuit with seven delay circuit element number be operated in second frequency, and wherein first frequency is greater than second frequency.
See also Fig. 5 a again, it is the preferred embodiment circuit diagram of digital inverter of the present invention, it is mainly finished by two metal oxide semiconductor transistors 501,502, wherein grid the oscillator signal that receives on these last nodes of the common input of forming 503, through delay with anti-phase after send to next node by output 504 again.And represent the driving force of this digital inverter because of the size of current on the current path between the first voltage source Vct and the second voltage source Vss, therefore pass through the change of size of current on the current path between the first voltage source Vct and the second voltage source Vss, just can change the time of delay of this digital inverter a little, for example the electrorheological senior general shortens time of delay and allows oscillation signal frequency accelerate, and the electrorheological young pathbreaker increases its time of delay and make oscillation signal frequency slack-off, so just can reach the purpose of the frequency of this oscillator signal of fine tune.
As for Fig. 5 b then is the preferred embodiment circuit diagram of above-mentioned controlled inverter, it is mainly finished by four metal oxide semiconductor transistors, wherein 53 of second metal oxide semiconductor transistor 52 and the 3rd metal oxide semiconductor transistors are formed a digital inverter, its input 591 is the oscillator signal that receives on this last node, is sent to next node by output 592 through after anti-phase again.As for the grid system of the grid of first metal oxide semiconductor transistor 51 and the 4th metal oxide semiconductor transistor 54 in order to the inversion signal HIB that receives this control signal respectively and the HI of this control signal own, and the source electrode of first metal oxide semiconductor transistor 51 is electrically connected to this first voltage source Vct, and the source electrode of the 4th metal oxide semiconductor transistor 54 then is electrically connected on this second voltage source Vss.Thus, when the voltage of control signal is high level, first metal oxide semiconductor transistor 51 and the 4th all conductings of metal oxide semiconductor transistor 54, entire circuit will be operated in upper frequency, and when the voltage of control signal is low level, first metal oxide semiconductor transistor 51 and the 4th metal oxide semiconductor transistor 54 are all closed, and entire circuit will be operated in lower frequency.And in this example, this first metal oxide semiconductor transistor 51 is all the P-type mos transistor with this second metal oxide semiconductor transistor 52, and the 3rd metal oxide semiconductor transistor 53 is all N type metal oxide semiconductor transistor with the 4th metal oxide semiconductor transistor 54.But actual practice can be not limited thereto example, and can be selected for use arbitrarily by those skilled in the art.
See also Fig. 6 again, it is that the present invention develops a supply unit that cooperates running with this voltage-controlled oscillator circuit a functional circuit block schematic diagram, this supply unit 60 mainly includes digital control current source 601, five metals belongs to oxide semi conductor transistor 602, the 6th metal oxide semiconductor transistor 603 and an electric capacity 604, and wherein digital control current source 601 can be answered the digital signal B[m-1:0 of a m position] variation and change the size of its output current; The grid that five metals belongs to oxide semi conductor transistor 602 is connected with drain electrode and is connected in series to this digital control current source 601, and the grid of the 6th metal oxide semiconductor transistor 603 is connected to the grid that this five metals belongs to oxide semi conductor transistor 602, and the source electrode that the source electrode of the 6th metal oxide semiconductor transistor 603 and this five metals belong to oxide semi conductor transistor 602 is connected to certain voltage source Vdd jointly.Be connected to the drain electrode of the 6th metal oxide semiconductor transistor 603 as for an end of electric capacity 604, the other end is connected to the second voltage source Vss, size of current on the current path between this electric capacity both end voltage Vct, Vss is subjected to the output current of this digital control current source 601 and changes, and then reaches the fine setting of frequency of the oscillator signal P1～Pn of these a plurality of outs of phase that this voltage-controlled oscillator circuit 61 is exported.
In sum, apparatus of the present invention can provide the user to utilize control signal to come the operator scheme of switched voltage control generator circuit 61, and then can allow voltage-controlled oscillator circuit 61 operate in two kinds of states that frequency band is different, and be under the situation of the quantity of the output clock signal that does not reduce out of phase, reach the requirement that increases operational frequency range, in addition, level change action by control signal, also the script possible operation can be reset at the voltage-controlled oscillator circuit 61 of error condition, and can operate in the state of the oscillator signal P1～Pn of output correct phase relation.And the setting of electric capacity 604 is effectively power supply Vct, the Vss of burning voltage control generator circuit 61 also, and then power supply is disturbed preferable inhibition ability is arranged.Therefore, the present invention really can improve the disappearance of any means known and increase the performance of voltage-controlled oscillator circuit, and then reaches development main purpose of the present invention.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
Phase/frequency detector: 1010
Charge pump: 1011
Loop filter: 1012
Voltage controlled oscillator: 1013
Frequency divider: 1014
Digital inverter: 21～2n
Digital inverter: M1～Mn
Interpolation phase inverter: S1～Sn
Circuit node: X1～Xn
Controlled inverter: C1～Cn
Metal oxide semiconductor transistor: 501,502
Input: 503
Output: 504
First voltage source: Vct
Second voltage source: Vss
First metal oxide semiconductor transistor: 51
Second metal oxide semiconductor transistor: 52
The 3rd metal oxide semiconductor transistor: 53
The 4th metal oxide semiconductor transistor: 54
Input: 591
Output: 592
The inversion signal of control signal: HIB
Control signal: HI
Supply unit: 60
Digital control current source: 601
Five metals belongs to oxide semi conductor transistor: 602
The 6th metal oxide semiconductor transistor: 603
Electric capacity: 604
Oscillator signal: P1～Pn.
Claims (12)
1. a voltage-controlled oscillator circuit is characterized in that, comprising:
One ring oscillator circuit, it is formed by a plurality of delay circuits unit serial connection, and the output of last delay circuit unit is electrically connected to the input of one delay circuit unit, back and forms a node; And
A plurality of controlled delay circuit units, wherein the input of a controlled delay circuit unit and output are electrically connected to a first node and the Section Point in this ring oscillator circuit respectively, and the total quantity that includes the described controlled delay circuit unit that had on the subloop of this controlled delay circuit unit and the delay circuit unit in the described ring oscillator circuit between this first node and this Section Point is identical, and each controlled delay circuit unit is subjected to control signal control and switches between a conducting state and an off state, and then changes the frequency of a plurality of oscillator signals of the phase place inequality that described node exports.
2. voltage-controlled oscillator circuit according to claim 1 is characterized in that, a plurality of delay circuits unit in the described ring oscillator circuit is a n digital inverter, and n is the positive odd number greater than 1.
3. voltage-controlled oscillator circuit according to claim 1 is characterized in that, this controlled delay circuit unit comprises:
One first metal oxide semiconductor transistor, its grid are subjected to the control of this control signal and conducting or open circuit, and its source electrode is electrically connected to one first voltage source;
One second metal oxide semiconductor transistor, its grid is electrically connected on this first node, and its source electrode is electrically connected to the drain electrode of this first metal oxide semiconductor transistor, and its drain electrode is electrically connected on this Section Point;
One the 3rd metal oxide semiconductor transistor, its grid is electrically connected on this first node, and its drain electrode is electrically connected to the drain electrode of this second metal oxide semiconductor transistor; And
One the 4th metal oxide semiconductor transistor, its grid are subjected to the control of this control signal and conducting or open circuit, and its drain electrode is electrically connected to the source electrode of the 3rd metal oxide semiconductor transistor, and its source electrode is electrically connected on one second voltage source.
4. voltage-controlled oscillator circuit according to claim 3, it is characterized in that, this first metal oxide semiconductor transistor and this second metal oxide semiconductor transistor are all the P-type mos transistor, the 3rd metal oxide semiconductor transistor and the 4th metal oxide semiconductor transistor are all N type metal oxide semiconductor transistor, and the grid of this first metal oxide semiconductor transistor is in order to receive an inversion signal of this control signal, and the grid of the 4th metal oxide semiconductor transistor is then in order to receive this control signal.
5. voltage-controlled oscillator circuit according to claim 3 is characterized in that, this first voltage source and this second voltage source are provided by a supply unit, and this supply unit comprises:
One digital control current source, it is answered the variation of a digital signal and changes the size of its output current;
One five metals belongs to oxide semi conductor transistor, and its grid is connected with drain electrode and is connected in series to this digital control current source;
One the 6th metal oxide semiconductor transistor, its grid is connected to the grid that this five metals belongs to oxide semi conductor transistor, and the source electrode that its source electrode and this five metals belong to oxide semi conductor transistor is connected to the certain voltage source jointly; And
One electric capacity, this electric capacity one end is connected to the drain electrode of the 6th metal oxide semiconductor transistor, this electric capacity other end is connected to this second voltage source, voltage difference between these electric capacity two ends is subjected to the output current of this digital control current source and changes, and then the voltage of exporting this first voltage source in its two ends respectively and the voltage of this second voltage source and the source electrode of corresponding respectively first metal oxide semiconductor transistor that exports this controlled delay circuit unit to and the source electrode of the 4th metal oxide semiconductor transistor.
6. voltage-controlled oscillator circuit according to claim 1, it is characterized in that, when described controlled delay circuit unit is in this conducting state, the frequency of this oscillator signal that this node is exported is a first frequency, when described controlled delay circuit unit is in off state, the frequency of this oscillator signal that this node is exported is a second frequency, and wherein first frequency is greater than second frequency.
7. a voltage-controlled oscillator circuit is characterized in that, comprising:
One ring oscillator circuit, it is formed by n delay circuit unit serial connection, and the output of wherein last delay circuit unit is electrically connected to the input of one delay circuit unit, back and forms a node, and n is the positive odd number greater than 1; And
A plurality of controlled delay circuit units, wherein the input of a controlled delay circuit unit and output are electrically connected to a first node and the Section Point in this ring oscillator circuit respectively, and this first node, the described controlled delay circuit unit that is had on this Section Point and the formed subloop of this controlled delay circuit unit and the total quantity of the delay circuit unit in the described ring oscillator circuit all are all i and i less than n, because of the number of the delay circuit unit in the described ring oscillator circuit that inserting of described controlled delay circuit unit skipped over then for x and x less than n, and x, i, the pass of n is x=n-i+1, and each controlled delay circuit unit is subjected to control signal control and switches between a conducting state and an off state, and then changes the frequency of a plurality of oscillator signals of the phase place inequality that described node exports.
8. voltage-controlled oscillator circuit according to claim 7 is characterized in that, n delay circuit unit is n digital inverter.
9. voltage-controlled oscillator circuit according to claim 7 is characterized in that, this controlled delay circuit unit comprises:
One first metal oxide semiconductor transistor, its grid are subjected to the control of this control signal and conducting or open circuit, and its source electrode is electrically connected to one first voltage source;
One second metal oxide semiconductor transistor, its grid is electrically connected on this first node, and its source electrode is electrically connected to the drain electrode of this first metal oxide semiconductor transistor, and its drain electrode is electrically connected on this Section Point;
One the 3rd metal oxide semiconductor transistor, its grid is electrically connected on this first node, and its drain electrode is electrically connected to the drain electrode of this second metal oxide semiconductor transistor; And
One the 4th metal oxide semiconductor transistor, its grid are subjected to the control of this control signal and conducting or open circuit, and its drain electrode is electrically connected to the source electrode of the 3rd metal oxide semiconductor transistor, and its source electrode is electrically connected on one second voltage source.
10. voltage-controlled oscillator circuit according to claim 9, it is characterized in that, this first metal oxide semiconductor transistor and this second metal oxide semiconductor transistor are all the P-type mos transistor, the 3rd metal oxide semiconductor transistor and the 4th metal oxide semiconductor transistor are all N type metal oxide semiconductor transistor, and the grid of this first metal oxide semiconductor transistor is in order to receive an inversion signal of this control signal, and the grid of the 4th metal oxide semiconductor transistor is then in order to receive this control signal.
11. voltage-controlled oscillator circuit according to claim 9 is characterized in that, this first voltage source and this second voltage source system are provided by a supply unit, and this supply unit comprises:
One digital control current source, it is answered the variation of a digital signal and changes the size of its output current;
One five metals belongs to oxide semi conductor transistor, and its grid is connected with drain electrode and is connected in series to this digital control current source;
One the 6th metal oxide semiconductor transistor, its grid is connected to the grid that this five metals belongs to oxide semi conductor transistor, and the source electrode that its source electrode and this five metals belong to oxide semi conductor transistor is connected to the certain voltage source jointly; And
One electric capacity, this electric capacity one end is connected to the drain electrode of the 6th metal oxide semiconductor transistor, this electric capacity other end is connected to this second voltage source, voltage difference between these electric capacity two ends is subjected to the output current of this digital control current source and changes, and then the voltage of exporting this first voltage source in its two ends respectively and the voltage of this second voltage source and the source electrode of corresponding respectively first metal oxide semiconductor transistor that exports this controlled delay circuit unit to and the source electrode of the 4th metal oxide semiconductor transistor.
12. voltage-controlled oscillator circuit according to claim 7, it is characterized in that, when described controlled delay circuit unit is in this conducting state, the frequency of this oscillator signal that this node is exported is a first frequency, when described controlled delay circuit unit is in off state, the frequency of this oscillator signal that this node is exported is a second frequency, and wherein first frequency is greater than second frequency.
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| CN 200710163753 CN101141129B (en) | 2007-10-26 | 2007-10-26 | Voltage controlled oscillator circuit |
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| CN 200710163753 CN101141129B (en) | 2007-10-26 | 2007-10-26 | Voltage controlled oscillator circuit |
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| CN101141129B true CN101141129B (en) | 2010-12-22 |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2795793A4 (en) * | 2011-12-19 | 2015-12-16 | Intel Corp | Multi-phase voltage-controlled oscillator |
| TWI495266B (en) * | 2012-10-23 | 2015-08-01 | Solid State System Co Ltd | Ring oscillator |
| CN103326715B (en) * | 2013-05-31 | 2015-11-18 | 中国人民解放军国防科学技术大学 | A kind of single-ended voltage controlled oscillator of low intrinsic jitter |
| CN104954012B (en) * | 2014-03-28 | 2018-04-10 | 扬智科技股份有限公司 | Layout structure |
| CN104410413B (en) * | 2014-11-20 | 2017-10-20 | 江汉大学 | Atomic frequency standard frequency Correction Method, device and atomic frequency standard |
| CN109167571A (en) * | 2018-08-13 | 2019-01-08 | 中科芯集成电路股份有限公司 | A kind of low-power consumption ring oscillator and its implementation |
| KR20220122717A (en) | 2020-10-28 | 2022-09-02 | 창신 메모리 테크놀로지즈 아이엔씨 | Memory |
| CN114499506A (en) | 2020-10-28 | 2022-05-13 | 长鑫存储技术有限公司 | Oscillator and clock generating circuit |
| CN114417772A (en) * | 2020-10-28 | 2022-04-29 | 长鑫存储技术有限公司 | Oscillator layout |
| JP7387902B2 (en) | 2020-10-28 | 2023-11-28 | チャンシン メモリー テクノロジーズ インコーポレイテッド | Clock generation circuit, memory and clock duty ratio calibration method |
| JP7467655B2 (en) | 2020-10-28 | 2024-04-15 | チャンシン メモリー テクノロジーズ インコーポレイテッド | CALIBRATION CIRCUIT, MEMORY AND CALIBRATION METHOD - Patent application |
| US11424745B2 (en) | 2020-10-28 | 2022-08-23 | Changxin Memory Technologies, Inc. | Oscillation circuit and clock generation circuit |
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| US5563554A (en) * | 1994-09-06 | 1996-10-08 | Nec Corporation | Voltage controlled oscillator and phase-locked loop circuit |
| US5619170A (en) * | 1994-04-19 | 1997-04-08 | Nec Corporation | PLL timing generator with voltage controlled oscillator |
| US6989697B2 (en) * | 2004-01-15 | 2006-01-24 | Organicid, Inc. | Non-quasistatic phase lock loop frequency divider circuit |
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| US5619170A (en) * | 1994-04-19 | 1997-04-08 | Nec Corporation | PLL timing generator with voltage controlled oscillator |
| US5563554A (en) * | 1994-09-06 | 1996-10-08 | Nec Corporation | Voltage controlled oscillator and phase-locked loop circuit |
| US6989697B2 (en) * | 2004-01-15 | 2006-01-24 | Organicid, Inc. | Non-quasistatic phase lock loop frequency divider circuit |
| CN1741384A (en) * | 2004-08-26 | 2006-03-01 | 恩益禧电子股份有限公司 | Clock generating circuit |
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| CN101141129A (en) | 2008-03-12 |
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