CN101141427B - Method and device for performing demodulation to digital signal using synchronous clock signal - Google Patents
Method and device for performing demodulation to digital signal using synchronous clock signal Download PDFInfo
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- CN101141427B CN101141427B CN200710127705XA CN200710127705A CN101141427B CN 101141427 B CN101141427 B CN 101141427B CN 200710127705X A CN200710127705X A CN 200710127705XA CN 200710127705 A CN200710127705 A CN 200710127705A CN 101141427 B CN101141427 B CN 101141427B
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Abstract
The present invention relates to a method for demodulating digital signals by using synchronous clock signals in a digital communication system. The method comprises the steps that first, the bit-synchronous restoration is performed for inputting signals by using two loops and more than two loops of bit-synchronous tracking loops which work within a mutually overlapping locking frequency range in parallel, and then data is output; second, all loops are decoded in parallel, and verification and storage are performed through the output data; third, after the data sent for once is accomplished, a loop of correct demodulated signals is selected and output according to the verification result. The device of the method comprises N loops of paralleled bit-synchronous tracking loops, N loops of verification modules, N loops of storage modules, a signal valid determination module and a selection output module. The present invention solves the problems that because the frequency coverage area of the synchronous tracking loops is insufficient in the prior art, the synchronous clock shakes severely, the synchronous loops are out of lock when the valid data is sent, and the signals cannot be demodulated correctly, thus achieving the effects that the precision of the digital synchronous tracking loops is improved, and the locking range of the digital synchronous tracking loops is increased.
Description
Technical field
The present invention relates to the bit synchronization technical field of digital communication system, utilize synchronizing clock signals digital signal to be carried out the method and apparatus of demodulation in particularly a kind of digital communication system, it can be applicable to RFID (Radio Frequence Identification, radio-frequency (RF) identification) electronic tag also can be applied to the digital communication system that other needs bit synchronization restoration to the bit synchronization restoration of reader signal in the system.
Background technology
In digital communication system, in order to realize the demodulation of signal, a kind of mode is to extract synchronizing clock signals from digital signal, utilizes synchronizing clock signals that digital signal is carried out demodulation again.
With the example that is applied as at RFID, electronic tag to the problem that reader signal exists is: it is discontinuous to send signal, and it is very short once to send signal time; Send the voltage controlled oscillator output of the synchronised clock of signal by chip internal, the clock accuracy difference causes the synchronised clock frequency accuracy of different labels transmission signals poor.The method (as: section's Stas ring) that normally used digital phase-locked loop is synchronous exists lock-in range and the contradiction that locks precision in the use.That is, when lock-in range increased, the locked clock shake increased; And because the signal frequency low precision of label output, the lock-in range on single phase-locked loop road can not satisfy the needs of reading tag data.Another problem is: it is short that label once sends signal time, can not wait until that phase-locked loop locks fully to gather dateout again, but when digital phase-locked loop also fully locking begun the bit synchronization restoration of valid data.
Summary of the invention
The object of the present invention is to provide the method and apparatus that utilizes synchronizing clock signals that digital signal is carried out demodulation in a kind of digital communication system, be used for solving the frequency coverage deficiency of prior art owing to synchronous track loop, the synchronised clock shake is big; Particularly because the transmit leg clock accuracy is poor, one time communication time is very short, and digital phase-locked loop needs under the synchronous situation of certain hour, cause synchronization loop losing lock when valid data send, signal is the problem of demodulation correctly, reach raising digital synchronous track loop precision, increased the effect of digital synchronous tracking loop lock-in range.
For achieving the above object, the present invention is achieved in that
The method of utilizing synchronizing clock signals that digital signal is carried out demodulation in a kind of digital communication system is characterized in that this method step is:
A, N of parallel utilization are operated in the bit synchronization track loop on the locking frequency scope of mutual overlapping, and the baseband signal of input is carried out bit synchronization restoration, and dateout;
B, each loop parallel decoding dateout is carried out verification and storage respectively;
C, once send ED the time, select correct road restituted signal output according to the result of verification;
N is the positive integer more than or equal to 2 in the above-mentioned steps.
Among the described step B data of bit synchronization track loop output are carried out lead code coupling and CRC check.
Described step C further comprises:
C1, the data through verification of each road bit synchronization track loop output are effectively adjudicated;
C2, the effective court verdict of the basis number of it is believed that are selected the output of one road valid data.
The device that utilizes synchronizing clock signals that digital signal is carried out demodulation in a kind of digital communication system is used to implement aforesaid method, it is characterized in that it comprises:
The bit synchronization track loop that the N road is parallel, they are operated in respectively on the locking frequency scope of mutual overlapping carries out bit synchronization restoration to the baseband signal of input, and dateout;
N road verification module, they carry out the lead code coupling to the data of bit synchronization track loop output respectively, enter decoding and verification again after coupling is finished, and check results is delivered to the effective judging module of signal;
N road memory module is used for the current data that once send that the synchronous track loop of bank bit is exported;
The effective judging module of one signal, it selects a road correct useful signal of selection check according to the data check result of each verification module output, and output module is selected in this information input;
One selects output module, and it is according to the output result of the effective judging module of signal, selects the data of storing in the memory module of one road useful signal, and valid data are exported.
Described bit synchronization track loop employing section Stas ring.
The centre frequency of described N road its work of bit synchronization track loop is respectively f1, f2 ..., fn, the cycle separately is respectively 1/f1,1/f2,1/fn regulates step-length and is respectively D* (1/f1), D* (1/f2), D* (1/fn), 0＜D＜0.4.
By technique scheme, the beneficial effect of tool of the present invention is:
1, in the method and apparatus of the present invention, parallel running N bit synchronization track loop stored respectively the output signal of each loop, and binding data verification selection, reduced the shake of single synchronous tracking loop, increases the frequency lock-in range of synchronous tracking loop.
2, the foundation that can switch as phase-locked loop with lead code coupling and CRC check result of the inventive method and device, data that can more effective recovery label output.
3, the inventive method and device can be applicable to the bit synchronization restoration to reader signal of electronic tag in the rfid system, also can be applied to the digital communication system that other needs bit synchronization restoration.
Description of drawings
Fig. 1 is the structural representation of apparatus of the present invention;
Fig. 2 is the basic flow sheet of the inventive method.
Embodiment
See also Fig. 1, it is to utilize synchronizing clock signals digital signal to be carried out the structural representation of device one preferred embodiment of demodulation in a kind of digital communication system of the present invention.It can be applicable to, and electronic tag also can be applied to the digital communication system that other needs bit synchronization restoration to the bit synchronization restoration of reader signal in the rfid system.
As shown in the figure: this installs by bit synchronization track loop 101,102,103, verification module 104,106,108, the effective judging module 110 of signal, the current data that once send and the selection output module 111 of the synchronous tracking loop output of memory module 105,107,109 storages are formed.The function and the annexation of each module are:
The bit synchronization track loop 101,102,103 that the N road is parallel, they are operated in respectively on the locking frequency scope of mutual overlapping carries out bit synchronization restoration to the baseband signal of input, and dateout; Each road bit synchronization track loop 101,102,103 can employing section Stas ring, and the centre frequency of its work is respectively f1, f2 ..., fn.Therefore the cycle separately is respectively 1/f1,1/f2, and 1/fn. regulates step-length and is respectively D* (1/f1), D* (1/f2), D* (1/fn).D is for regulating step-length ratio (can get the value of 0＜D＜0.4 with border situation factually).The adjustable range of each section overlaps each other, may be more than a correct restore data of track loop energy on the frequency that has.The bit synchronization tracking loop is directly followed according to the bit synchronization result and is exported data recovered.
N road verification module 104,106,108, they carry out the lead code coupling to the data of bit synchronization track loop 101,102,103 outputs respectively, enter decoding and verification again after coupling is finished, and check results is delivered to the effective judging module 110 of signal;
N road memory module 105,107,109 is used for the current data that once send that the synchronous track loop 101,102,103 of bank bit is exported;
The effective judging module 110 of one signal, it selects a road correct useful signal of selection check according to the data check result of each verification module 104,106,108 output, and output module 111 is selected in this information input;
One selects output module 111, and it is according to the output result of the effective judging module 110 of signal, selects to store in the memory module of one road useful signal 105,107,109 data, and valid data are exported;
Above-mentioned N is the positive integer more than or equal to 2.
According to said apparatus, the step of utilizing synchronizing clock signals that digital signal is carried out the method for demodulation in the digital communication system of the present invention is:
A, N of parallel utilization are operated in the bit synchronization track loop on the locking frequency scope of mutual overlapping, and the baseband signal of input is carried out bit synchronization restoration, and dateout;
B, each loop parallel decoding dateout is carried out verification and storage respectively;
C, once send ED the time, select correct road restituted signal output according to the result of verification;
Described step C further comprises:
C1, the data through verification of each road bit synchronization track loop output are effectively adjudicated;
C2, the effective court verdict of the basis number of it is believed that are selected the output of one road valid data.
N is the positive integer more than or equal to 2 in the above-mentioned steps.
Among the last step B data of bit synchronization track loop output are carried out lead code coupling and CRC check.
Use said method and device, can store respectively, and carry out data check in conjunction with RFID label data characteristics and select, reduced the shake of single synchronous tracking loop, increase the frequency lock-in range of synchronous tracking loop the output signal of each loop.
Be the preferred embodiments of the present invention only below, be not limited to the present invention, for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the method for utilizing synchronizing clock signals that digital signal is carried out demodulation in the digital communication system is characterized in that this method step is:
A, N of parallel utilization are operated in the bit synchronization track loop on the locking frequency scope of mutual overlapping, and the baseband signal of input is carried out bit synchronization restoration, and dateout;
B, each loop parallel decoding dateout is carried out verification and storage respectively;
C, once send ED the time, select the data of storing in the memory module of a road correct useful signal according to the result of verification, and valid data exported;
N is the positive integer more than or equal to 2 in the above-mentioned steps.
2. the method for utilizing synchronizing clock signals that digital signal is carried out demodulation in the digital communication system according to claim 1 is characterized in that among the described step B data of bit synchronization track loop output being carried out lead code coupling and CRC check.
3. the method for utilizing synchronizing clock signals that digital signal is carried out demodulation in the digital communication system according to claim 1 and 2 is characterized in that described step C further comprises:
C1, the data through verification of each road bit synchronization track loop output are effectively adjudicated;
C2, according to the effective court verdict of signal, select one road valid data output.
4. the device that utilizes synchronizing clock signals that digital signal is carried out demodulation in the digital communication system is used for implementing it is characterized in that as claim 1 or 2 or 3 described methods it comprises:
The bit synchronization track loop that the N road is parallel, they are operated in respectively on the locking frequency scope of mutual overlapping carries out bit synchronization restoration to the baseband signal of input, and dateout;
N road verification module, they carry out the lead code coupling to the data of bit synchronization track loop output respectively, enter decoding and verification again after coupling is finished, and check results is delivered to the effective judging module of signal;
N road memory module is used for the current data that once send that the synchronous track loop of bank bit is exported;
The effective judging module of one signal, the data check result that it is exported according to each verification module, the road useful signal that selection check is correct, and with information input selection output module;
One selects output module, and it is according to the output result of the effective judging module of signal, selects the data of storing in the memory module of one road useful signal, and valid data are exported;
Above-mentioned N is the positive integer more than or equal to 2.
5. the device that utilizes synchronizing clock signals that digital signal is carried out demodulation in the digital communication system according to claim 4 is characterized in that described bit synchronization track loop employing section Stas ring.
6. according to the device that utilizes synchronizing clock signals that digital signal is carried out demodulation in claim 4 or the 5 described digital communication systems, it is characterized in that the centre frequency of described N road its work of bit synchronization track loop is respectively f1, f2, ..., fn, the cycle separately is respectively 1/f1,1/f2, ..., 1/fn regulates step-length and is respectively D* (1/f1), D* (1/f2), ..., D* (1/fn), 0＜D＜0.4.
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| CN200710127705XA CN101141427B (en) | 2007-03-15 | 2007-06-18 | Method and device for performing demodulation to digital signal using synchronous clock signal |
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| CN200710038114 | 2007-03-15 | ||
| CN200710038114.5 | 2007-03-15 | ||
| CN200710127705XA CN101141427B (en) | 2007-03-15 | 2007-06-18 | Method and device for performing demodulation to digital signal using synchronous clock signal |
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| CN101141427B true CN101141427B (en) | 2011-09-21 |
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| CN102752249B (en) * | 2011-04-20 | 2015-05-27 | 上海炬力集成电路设计有限公司 | Signal detection device and method |
| CN104717051B (en) * | 2014-12-29 | 2018-08-21 | 武汉大学 | A kind of Interpolate estimation method in parallel demodulation bit synchronization |
| CN110490015A (en) * | 2019-06-28 | 2019-11-22 | 北京中电华大电子设计有限责任公司 | A kind of method of elevating ultrahigh baud rate (VHBR) communication compatibility |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5389898A (en) * | 1992-06-22 | 1995-02-14 | Matsushita Electric Industrial Co., Ltd. | Phase locked loop having plural selectable voltage controlled oscillators |
| CN1143224A (en) * | 1995-03-31 | 1997-02-19 | 富士通株式会社 | Decoding unit and storage unit |
| US6509825B1 (en) * | 1999-09-24 | 2003-01-21 | Microchip Technology Incorporated | Integrated circuit device having a self-biased, single pin radio frequency signal input |
| CN1461110A (en) * | 2002-05-20 | 2003-12-10 | 富士通株式会社 | Self-adjusting device and method for phaselocked loop frequency synthesizer |
-
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- 2007-06-18 CN CN200710127705XA patent/CN101141427B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5389898A (en) * | 1992-06-22 | 1995-02-14 | Matsushita Electric Industrial Co., Ltd. | Phase locked loop having plural selectable voltage controlled oscillators |
| CN1143224A (en) * | 1995-03-31 | 1997-02-19 | 富士通株式会社 | Decoding unit and storage unit |
| US6509825B1 (en) * | 1999-09-24 | 2003-01-21 | Microchip Technology Incorporated | Integrated circuit device having a self-biased, single pin radio frequency signal input |
| CN1461110A (en) * | 2002-05-20 | 2003-12-10 | 富士通株式会社 | Self-adjusting device and method for phaselocked loop frequency synthesizer |
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Effective date of registration: 20161009 Address after: 300308 Tianjin Airport Economic Zone, Binhai New Area seven East Road No. 2 Zhongxing Industrial Base Patentee after: ZTE INTELLIGENT IOT TECHNOLOGY CO., LTD. Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corporation |
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Granted publication date: 20110921 Termination date: 20190618 |