CN101165862B - High pressure stress film and stress silicon metal oxide semiconductor transistor and its manufacture method - Google Patents
High pressure stress film and stress silicon metal oxide semiconductor transistor and its manufacture method Download PDFInfo
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- CN101165862B CN101165862B CN2006101359854A CN200610135985A CN101165862B CN 101165862 B CN101165862 B CN 101165862B CN 2006101359854 A CN2006101359854 A CN 2006101359854A CN 200610135985 A CN200610135985 A CN 200610135985A CN 101165862 B CN101165862 B CN 101165862B
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Abstract
The invention discloses a high compressive stress film and a stress silicon metal oxide semiconductor transistor and its manufacture method. The method for manufacturing the stress silicon metal oxide semiconductor transistor comprises: providing a semiconductor substrate; forming a gate, at least one spacer and a source/drain region on the semiconductor substrate; then introducing a precursor to make the precursor react with silane and ammonia in order to form the high compressive stress film on the surface of the gate and the source/drain region, wherein the precursor comprises tetramethylsilane, ethers, aldehydes or carboxylic acids. The technology of the invention can be applied to the poly stresssor, the contact etch stop layer (CESL), and the dual CESL manufacture processes.
Description
Technical field
The present invention relates to a kind of method, strain silicon metal oxide semiconductor transistor and manufacture method thereof of making high pressure stress film, refer to a kind of method that on strain silicon metal oxide semiconductor transistor, forms high pressure stress film especially.
Background technology
Along with semiconductor fabrication is more and more accurate, great change also takes place in integrated circuit, makes the operational performance of computer and memory capacity advance by leaps and bounds, and drives peripheral industry and develop rapidly.And semiconductor industry is also predicted as Moore's Law, developing with per 18 months speed of transistor size on integrated circuit that doubles, simultaneously semiconductor fabrication process also from 90 nanometers (0.09 micron) in 0.13 micron, 2003 of 0.18 micron in 1999, calendar year 2001, enters into 2005 65 nanometers (0.065 micron technology grade).
And along with the semiconductor technology grade enters the deep-sub-micrometer epoch, how utilizing heavily stressed film to improve the transistorized drive current of metal-oxide semiconductor (MOS) (MOS) (drivecurrent) in semiconductor fabrication process becomes heat subject gradually.The drive current that utilizes heavily stressed film to improve metal oxide semiconductor transistor at present can be summarized as two aspects: one is applied in the polysilicon stressor layers (poly stressor) before metal silicide such as nickel silicon forms; Then be applied on the other hand contact hole etching stopping layer after metal silicides such as nickel silicon form (contact etch stop layer, CESL).
Generally speaking, the thermal effect (thermalbudget) that the manufacturing process tolerable of polysilicon stressor layers is higher is for example greater than 1000 ℃.Yet, be impatient at the cause of higher thermal effect on the manufacturing process of contact hole etching stopping layer (CESL) because when need to consider forming nickel silicon, therefore must the restriction technological temperature less than 430 ℃.So prior art when the heavily stressed film of making contact hole etching stopping layer (CESL), generally can deposit the film of being made up of silicon nitride (SiN) earlier, and then improve the drive current of metal oxide semiconductor transistor by this film.
Please refer to Fig. 1 to Fig. 3, Fig. 1 to Fig. 3 makes high pressure stress film in the method schematic diagram on PMOS transistor surface for having now.As shown in Figure 1, at first provide the semiconductor-based end 10, silicon base for example, and comprise grid structure 12 at the semiconductor-based end 10.Wherein, grid structure 12 also comprises grid oxic horizon (gate oxide) 14, is positioned at the grid 16 on the grid oxic horizon 14, the cover layer (cap layer) 18 that is positioned at grid 16 top surfaces and oxide-nitride thing-oxide off normal sidewall (ONO offset spacer) 20.Generally speaking, grid oxic horizon 14 is by silicon dioxide (silicon dioxide, SiO
2) constitute, grid 16 is made of doped polycrystalline silicon (doped polysilicon), cover layer 18 then is made up of silicon nitride layer, in order to the protection grid 16.In addition, be surrounded with shallow isolating trough (STI) 22 in addition at the semiconductor-based end 10 of the active region at grid structure 12 places (active area) periphery.
As shown in Figure 2, carry out ion subsequently and inject (ion implantation) technology, in the semiconductor-based end 10 around sidewall 20, to form regions and source 26.Then in the semiconductor-based end 10 and grid structure 12 surface sputtering metal levels (figure does not show), for example nickel metal layer.Being rapidly heated then, (rapid thermal annealing, RTA) technology make this metal level become metal silicide layer with the partial reaction that grid 16 and regions and source 26 contact in annealing.Remove the unreacted metal layer at last again.
As shown in Figure 3, then feed silicomethane (silane, SiH
4) and ammonia (ammonia, NH
3), and carry out plasma reinforced chemical vapour deposition (plasma enhanced chemical vapor deposition, PECVD) technology is covered in grid structure 12 and regions and source 26 surfaces to form high pressure stress film (high compressive stress film) 28.Compress grid 16 belows by high pressure stress film 28 then, be the lattice arrangement at the semiconductor-based end 10 of channel region (channel region), and then improve the hole mobility and the transistorized drive current of strained silicon (strained silicon) PMOS (drive current) of channel region.
Generally speaking, the mode of the power of the high and low frequency radio wave of prior art utilization adjustment manufacturing machine and raising silicomethane and ammonia ratio is produced high-quality high pressure stress film.Yet, have that the highest only can producing has-first plating (as-deposite) film of 1.6GPa stress in the plasma reinforced chemical vapour deposition technology under 400 ℃ now.Because the deficiency of compression stress, this film will have a strong impact on the stress that subsequent thin film produces and the drive current of metal oxide semiconductor transistor.Therefore the stress (stress) that how effectively to improve high pressure stress film is the index of present this area important technology ability.
Summary of the invention
Therefore main purpose of the present invention provides a kind of method, strain silicon metal oxide semiconductor transistor and manufacture method thereof of making high pressure stress film, to solve the existing problem that can't effectively improve high pressure stress film stress.
According to the present invention, disclose a kind of method of making strain silicon metal oxide semiconductor transistor.The semiconductor-based end, at first be provided, and on this semiconductor-based end, form grid, at least one sidewall and regions and source.Feed predecessor (precursor) then, feed silicomethane (silane) and ammonia (ammonia) again, and make this predecessor and silicomethane and ammonia gas react, to form high pressure stress film (highcompressive film) in this grid and this regions and source surface, wherein this predecessor comprises tetramethylsilane, ethers, aldehydes or carboxylic acids.
According to the present invention, a kind of method of making high pressure stress film also is provided, it utilizes predecessor and silicomethane and ammonia gas react, and the high pressure stress film that comprises the Si-R key with formation wherein this predecessor comprises tetramethylsilane, ethers, aldehydes or carboxylic acids.
According to the present invention, a kind of method of making high pressure stress film also is provided, it utilizes predecessor and silicomethane and ammonia gas react, comprises the high pressure stress film of Si-O-R key with formation, and wherein this predecessor comprises tetramethylsilane, aldehydes or carboxylic acids.
According to the present invention, a kind of strain silicon metal oxide semiconductor transistor also is provided, comprising:
The semiconductor-based end;
Grid was located on this semiconductor-based end;
At least one sidewall is located on the sidewall of this grid;
Regions and source was located in this semiconductor-based end;
A plurality of metal silicide layers are located at respectively on this top portions of gates and this regions and source surface; And
High pressure stress film be arranged on this grid, this sidewall and this regions and source surface, and this high pressure stress film is the SiN film and comprises Si-(CH
3) key.
According to the present invention, a kind of strain silicon metal oxide semiconductor transistor also is provided, comprising:
The semiconductor-based end;
Grid was located on this semiconductor-based end;
At least one sidewall is located on the sidewall of this grid;
Regions and source was located in this semiconductor-based end;
A plurality of metal silicide layers are located at respectively on this top portions of gates and this regions and source surface; And
High pressure stress film be arranged on this grid, this sidewall and this regions and source surface, and this high pressure stress film comprises the Si-O-R key.
The present invention feeds the predecessor of being made up of tetramethylsilane, ethers, aldehydes or carboxylic acids earlier before utilizing silicomethane and ammonia to form silicon nitride film, make this predecessor and silicomethane and ammonia gas react then and produce, and then significantly improve the stress of high pressure stress film by these keys as impurity keys such as Si-R key and Si-O-R keys.Therefore, the inventive method is except can be applicable to the making of general polysilicon stressor layers (polystressor), can be applicable to contact the making of hole etching stopping layer and two contacts hole etching stopping layer again, with effective rate of finished products and usefulness of improving strain silicon metal oxide semiconductor transistor.
Description of drawings
Fig. 1 to Fig. 3 makes high pressure stress film in the method schematic diagram on PMOS transistor surface for having now.
Fig. 4 to Fig. 6 makes the method schematic diagram of high pressure stress film in PMOS transistor surface for the present invention.
Fig. 7 is fourier transform infrared spectrometry (FTIR) schematic diagram of high pressure stress film of the present invention.
Fig. 8 is the stress of high pressure stress film of the present invention and existing high pressure stress film and the comparison diagram of PMOS ion gain percentage.
Fig. 9 is the schematic diagram that concerns of high pressure stress film of the present invention and the gain of PMOS ion.
Figure 10 to Figure 12 makes the method schematic diagram of contact hole etching stopping layer for another embodiment of the present invention.
Figure 13 to Figure 18 makes the method schematic diagram of two contacts hole etching stopping layer for another embodiment of the present invention.
The simple symbol explanation
10 grid structures of the semiconductor-based ends 12
14 grid oxic horizons, 16 grids
18 cover layers, 20 sidewall
22 shallow isolating trough, 26 regions and source
The 60 semiconductor-based ends of 28 high pressure stress films
62 shallow isolating trough, 63 grid structures
64 grid oxic horizons, 66 grids
68 cover layers, 70 sidewall
74 regions and source, 76 high pressure stress films
80 gate dielectrics of the semiconductor-based ends 82
84 grids, 86 grid structures
87 layings, 88 sidewall
90 ldd structures, 92 regions and source
94 metal levels, 96 metal silicide layers
The 98 contact 100 semiconductor-based ends of etching stopping layer, hole
102 nmos pass transistor districts, 104 PMOS transistor area
106 shallow isolating trough, 108 NMOS grids
110 PMOS grids, 112 layings
114 gate dielectrics, 115 metal silicide layers
116 regions and source, 117 regions and source
118 lightly doped drains, 119 lightly doped drains
The photoresist layer of 120 high tensile stress film 122 patterns
The photoresist layer of 124 high pressure stress films, 126 patterns
128 interlayer dielectric layers, 130 contact holes
Embodiment
Please refer to Fig. 4 to Fig. 6, Fig. 4 to Fig. 6 makes the method schematic diagram of high pressure stress film in PMOS transistor surface for the present invention.As shown in Figure 4, at first provide the semiconductor-based end 60, for example silicon wafer (wafer) or silicon-coated insulated (SOI) substrate, and comprise grid structure 63 at the semiconductor-based end 60.Wherein, grid structure 63 comprises gate dielectric 64, is positioned at the grid 66 on the gate dielectric 64, the cover layer 68 that is positioned at grid 66 top surfaces and oxide-nitride thing-oxide off normal sidewall (ONO offsetspacer) 70.Generally speaking, gate dielectric 64 can be megohmite insulants such as formed silica such as the technology of utilizing thermal oxidation or deposition or nitrogen silicon compound and constitutes, and cover layer 68 then can be by being formed in order to the silicon nitride layer of protection grid 66.In addition, in addition around shallow isolating trough (STI) 62, be used for making these other elements of PMOS transistor AND gate isolated at the semiconductor-based end 60 of the active region (AA) at grid structure 63 places periphery.
As shown in Figure 5, then carry out ion and inject (ion implantation) technology, in the semiconductor-based end 60 around the grid structure 63, to form regions and source 74.And then annealing (rapid thermal annealing) technology is rapidly heated, utilize 900 to 1050 ℃ high temperature to activate doping in the regions and source 74, and repair the lattice structure on surface, the semiconductor-based ends 60 impaired in each ion implantation technology simultaneously.In addition, also visual product demand and functional consideration, between regions and source 74 and grid structure 63, form lightly doped drain (LDD) or source/drain in addition respectively and extend (source/drain extension), perhaps form again and aim at metal silicide (salicide) voluntarily in regions and source 74 and grid structure 63 surfaces, this is all those of ordinary skill in the art knows, and does not add to give unnecessary details at this.
Then as shown in Figure 6, (plasma enhancedchemical vapor deposition, PECVD) technology is to form high pressure stress film 76 in grid structure 63 and regions and source 74 surfaces to carry out plasma reinforced chemical vapour deposition.In a preferred embodiment of the invention, this PECVD places cvd reactive chamber with the semiconductor-based end 60 earlier, then feeding is made up of tetramethylsilane (tetra-methyl-silane), ethers (ether), aldehydes (aldehyde) or carboxylic acids (carboxylic acid) etc. and is used as predecessor (precursor), feed silicomethane (silane) subsequently again and ammonia principal components such as (ammonia) is carried out plasma reinforced chemical vapour deposition, to form high pressure stress films 76 in grid structure 63 and regions and source 74 surfaces.Wherein, the flow of predecessor is between 30 to 3000 grams, and (standard cubic centimeter per minute, sccm) to 3000sccm, and the flow of this ammonia is between 30sccm to 2000sccm between 30 per minute standard milliliters for the flow of this silicomethane.In addition, the power of the high and low frequency radio wave of formation high pressure stress film 76 is all between 50 watts to 3000 watts.
It should be noted that the present invention in the process of carrying out plasma reinforced chemical vapour deposition technology, the predecessor that is fed can with form silicomethane and the ammonia gas react in the high pressure stress film 76 and produce various impurity (impurity) key, for example O/CH
3/ O-CH
3Deng.Please refer to Fig. 7, Fig. 7 is fourier transform infrared spectrometry (Fourier Transform Infrared Spectroscopy, the FTIR) schematic diagram of high pressure stress film of the present invention.As shown in Figure 7, by the reaction of predecessor and silicomethane and ammonia, the high pressure stress film 76 that the present invention is produced in plasma reinforced chemical vapour deposition technology can produce as Si-O-(CH under the pressure of-2.86GPa and-2.7GPa
3) the Si-O-R key that waits and as Si-CH
3The Si-R key key impurity key of key etc., and significantly improve the stress of high pressure stress film 76 by these keys, with compression grid 66 belows, i.e. the hole mobility and the transistorized drive current of PMOS of the lattice arrangement at the semiconductor-based end 60 in the channel region, and then raising channel region.
Please refer to Fig. 8, Fig. 8 is the stress of high pressure stress film of the present invention and existing high pressure stress film and the comparison diagram of PMOS ion gain percentage.As shown in Figure 8, when the deposit thickness of the high pressure stress film that is deposited as traditional handicraft and the present invention is all 1000 dusts (angstrom), the present invention can be by predecessor feeding with the stress of first plating (as-deposite) film by-1.6GPa significantly be increased to-2.7GPa about, and simultaneously the ion gain percentage (Ion gain percentage) of PMOS is increased to 45% by 24%.
Please refer to Fig. 9, Fig. 9 is the schematic diagram that concerns of high pressure stress film of the present invention and the gain of PMOS ion.As shown in Figure 9, under the condition of identical PMOS ion gain (20%), when the stress of high pressure stress film be-during 1.6GPA, required film thickness is about 850 dusts.According to a preferred embodiment of the invention, the present invention can be increased to the stress of high pressure stress film-2.7GPA, therefore reduce thickness to 450 dust of required film under the condition of (20%) of can gaining in same ion, and then can significantly improve the process allowance (process window) in subsequent etch contact hole.In addition, as the stress of film is kept-2.7GPa, the present invention can increase to the thickness of high pressure stress film 1000 dusts again, and then the ion gain of PMOS can be increased to 45%.
Please refer to Figure 10 to Figure 12, Figure 10 to Figure 12 makes the method schematic diagram of contact hole etching stopping layer (CESL) for another embodiment of the present invention.As shown in figure 10, at first on the semiconductor-based end 80, form the grid structure 86 that is constituted by gate dielectric 82 and grid 84, then carry out the ion implantation step, in the semiconductor-based end 80, to form ldd structure 90.Sidewall in grid structure 86 forms laying 87 and sidewall 88 subsequently, and carries out another ion implantation step, to form regions and source 92 in the semiconductor-based end 80 of sidewall 88 both sides.Then in surface sputtering metal level 94 of the semiconductor-based ends 80, for example nickel metal layer, and metal level 94 is covered in grid 84, sidewall 88 and regions and source 92 surfaces.As shown in figure 11, annealing (rapid thermal anneal then is rapidly heated, RTA) technology, make metal level 94 become metal silicide layer 96 with the partial reaction that grid 84 and regions and source 92 contact, finish and aim at metal silicide technology (salicide) voluntarily, remove unreacted metal layer 94 at last again.
As shown in figure 12, then carry out plasma reinforced chemical vapour deposition (PECVD) technology, to form high pressure stress film with regions and source 92 surfaces in grid structure 86, sidewall 88.In a preferred embodiment of the invention, this PECVD places cvd reactive chamber with the semiconductor-based end 80 earlier, then feeding is made up of tetramethylsilane (tetra-methyl-silane), ethers (ether), aldehydes (aldehyde) or carboxylic acids (carboxylic acid) etc. and is used as predecessor (precursor), feed silicomethane (silane) subsequently again and ammonia principal components such as (ammonia) is carried out plasma reinforced chemical vapour deposition, so that this predecessor and silicomethane (silane) and ammonia (ammonia) reaction produce as O/CH
3/ O-CH
3Deng key, and then form with regions and source 92 surfaces in grid structure 86, sidewall 88 and to contain Si-CH
3The nitrogen silicon compound layer of key and Si-O-R key is as contact hole etching stopping layer 98.Wherein, the flow of predecessor is between 30 to 3000 grams, and the flow of this silicomethane is between 30sccm to 3000sccm, and the flow of this ammonia is between 30sccm to 2000sccm.In addition, form the power of the high and low frequency radio wave that contacts hole etching stopping layer 98 all between 50 watts to 3000 watts.
Subsequently, the user can finish the back at contact hole etching stopping layer 98 and covers interlayer dielectric layer (inter-layer dielectric, ILD) (figure does not show) is in contacting etching stopping layer 98 surfaces, hole.Then utilize the photoresist layer (figure does not show) of pattern, to carry out anisotropic etching then, in this interlayer dielectric layer, to form a plurality of contacts hole (figure does not show), as the bridge of electronic component connection as etching mask.
Please refer to Figure 13 to Figure 18, Figure 13 to Figure 18 makes the method schematic diagram of two contact hole etching stopping layers (dual CESL) for another embodiment of the present invention.As shown in figure 12, at first provide one to separate out the semiconductor-based end 100 of nmos pass transistor district 102 and PMOS transistor area 104, and respectively have NMOS grid 108, PMOS grid 110 on each nmos pass transistor district 102 and the PMOS transistor area 104 and be arranged on each grid and the gate dielectric at the semiconductor-based end 100 114 with shallow isolating trough (STI) 106.Then the sidewall surfaces in NMOS grid 108 and PMOS grid 110 forms the laying 112 that is made of silica layer and silicon nitride layer respectively.
Carry out ion implantation technology then, respectively to form regions and source 116 and 117 at NMOS grid 108 and PMOS grid 110 at the semiconductor-based end 100 on every side.And then the annealing process that is rapidly heated utilizes 900 to 1050 ℃ high temperature to activate dopings in regions and source 116 and 117, and repairs the lattice structure on surface, the semiconductor-based ends 100 impaired in each ion implantation technology simultaneously.In addition, also visual product demand and functional consideration form lightly doped drain (LDD) 118 and 119 respectively in addition between regions and source 116,117 and each grid 108,110.
Then in surface sputtering metal level of the semiconductor-based ends 100 (figure does not show), nickel metal layer for example, annealing (RTA) technology then is rapidly heated, make metal level become metal silicide layer 115, finish and aim at metal silicide technology (salicide) voluntarily with the partial reaction that NMOS grid 108, PMOS grid 110 and regions and source 116 contact with 117.
After removing the unreacted metal layer, then carry out plasma reinforced chemical vapour deposition (PECVD) technology, form high tensile stress films (high tensile stress film) 120 with 115 surfaces of the metal silicide layer in nmos pass transistor district 102 and PMOS transistor area 104.
Then as shown in figure 14, carry out photoresist coating, exposure and developing process, with the photoresist floor 122 that forms pattern and cover whole nmos pass transistor district 102.Then carry out etch process, remove the zone that is not covered, promptly be covered in the high tensile stress film 120 on the PMOS transistor area 104, to form high tensile stress film 120 in NMOS grid 108 and regions and source 116 surfaces by the photoresist layer 122 of pattern.
As shown in figure 15, then remove the photoresist floor 122 of the pattern that is covered in the nmos pass transistor district 102.As shown in figure 16, carry out plasma reinforced chemical vapour deposition (PECVD) technology subsequently: feed earlier by tetramethylsilane (tetra-methyl-silane), ethers (ether), the predecessor (precursor) that aldehydes (aldehyde) or carboxylic acids (carboxylic acid) etc. are formed, feed silicomethane (silane) and ammonia principal components such as (ammonia) again, and make this predecessor and silicomethane (silane) that feeds subsequently and ammonia (ammonia) reaction, on nmos pass transistor district 102 and PMOS transistor area 104, to form high pressure stress film (high compressive stress film) 124.Wherein, the flow of predecessor is between 30 to 3000 grams, and the flow of this silicomethane is between 30sccm to 3000sccm, and the flow of this ammonia is between 30sccm to 2000sccm.In addition, the power of the high and low frequency radio wave of formation high pressure stress film 124 is all between 50 watts to 3000 watts.
As previous described embodiment, the high pressure stress film of present embodiment 124 equally with the predecessor that fed and the silicomethane in the high pressure stress film 124 and ammonia gas react also generation as Si-CH
3Impurity keys such as key and Si-O-R key, and then can significantly improve the compression of high pressure stress film 124 by these keys.
Then as shown in figure 17, carry out photoresist coating, exposure and developing process, with the photoresist layer 126 that forms pattern and cover whole PMOS transistor area 104.Then carry out etch process, remove the zone that is not covered, promptly cover the high pressure stress film 124 in the nmos pass transistor district 102, to form high pressure stress film 124 in PMOS grid 110 and regions and source 117 surfaces by the photoresist layer 126 of pattern.Remove the photoresist layer 126 of the pattern that covers on the PMOS transistor area 104 subsequently.
Embodiment according to this making two contact hole etching stopping layer (dual CESL), the present invention can widen the lattice arrangement at the semiconductor-based end 100 of NMOS grid 108 belows by high tensile stress film 120, utilize high pressure stress film 124 to compress the lattice arrangement at the semiconductor-based end 100 of PMOS grid 110 belows simultaneously, and then improve nmos pass transistor and the transistorized drive current of PMOS.
As shown in figure 18, (inter-layer dielectric, ILD) 128 in high tensile stress film 120 and high pressure stress film 124 surfaces then to cover interlayer dielectric layer.The photoresist layer (figure does not show) that utilizes pattern then is as etching mask, with high tensile stress film 120 and high pressure stress film 124 as contacting the hole etching stopping layer, and carry out anisotropic etching, in interlayer dielectric layer 128, to form a plurality of contacts hole 130, as the bridge of electronic component connection.
In addition, be not limited to the described order of making high tensile stress film and then making high pressure stress film earlier of previous Figure 13 to Figure 18, the present invention can form high pressure stress film again earlier on the PMOS transistor, forms high tensile stress film then after carrying out corresponding etch process on nmos pass transistor.Form again subsequently required interlayer dielectric layer with contact the hole in interlayer dielectric layer on high tensile stress film and high pressure stress film.
In sum, compare with existing method of making high pressure stress film, the present invention feeds the predecessor of being made up of tetramethylsilane, ethers, aldehydes or carboxylic acids etc. earlier before utilizing silicomethane and ammonia to form silicon nitride film, make this predecessor and silicomethane and ammonia gas react then and produce, and then significantly improve the stress of high pressure stress film by these keys as impurity keys such as Si-R key and Si-O-R keys.Therefore, the inventive method is except can be applicable to the making of general polysilicon stressor layers (poly stressor), can be applicable to contact the making of hole etching stopping layer and two contacts hole etching stopping layer again, with effective rate of finished products and usefulness of improving strain silicon metal oxide semiconductor transistor.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (33)
1. method of making strain silicon metal oxide semiconductor transistor, this method comprises the following steps:
The semiconductor-based end, be provided;
Form grid, at least one sidewall and regions and source on this semiconductor-based end;
Feed predecessor; And
Feed silicomethane and ammonia, make this predecessor and this silicomethane and this ammonia gas react, be covered in this grid and this regions and source surface to form high pressure stress film,
Wherein this predecessor comprises tetramethylsilane, aldehydes or carboxylic acids.
2. the method for claim 1, wherein this semiconductor-based end, comprise wafer or silicon-coated insulated substrate.
3. the method for claim 1 also comprises forming gate dielectric at this grid and between this semiconductor-based end.
4. the method for claim 1, wherein the flow of this silicomethane is between 30sccm to 3000sccm.
5. the method for claim 1, wherein the flow of this ammonia is between 30sccm to 2000sccm.
6. the method for claim 1, wherein this method also comprises the annealing process that is rapidly heated after forming this high pressure stress film.
7. the method for claim 1, wherein this strain silicon metal oxide semiconductor transistor is a strained silicon P-type mos transistor.
8. the method for claim 1, the step that wherein forms this high pressure stress film comprises carries out the plasma reinforced chemical vapour deposition processing step.
9. the method for claim 1 wherein forms the high frequency of this high pressure stress film and low frequency radio wave power between 50 watts to 3000 watts.
10. a method of making high pressure stress film comprises the following steps: to feed predecessor; Feed silicomethane and ammonia; Utilize predecessor and this silicomethane and this ammonia gas react, comprise the high pressure stress film of Si-R key with formation, wherein this predecessor comprises tetramethylsilane, aldehydes or carboxylic acids.
11. method as claimed in claim 10, wherein the flow of this silicomethane is between 30sccm to 3000sccm.
12. method as claimed in claim 10, wherein the flow of this ammonia is between 30sccm to 2000sccm.
13. method as claimed in claim 10, the power that wherein forms the high frequency of this high pressure stress film and low frequency radio wave is between 50 watts to 3000 watts.
14. method as claimed in claim 10, wherein this Si-R key comprises Si-(CH
3) key.
15. a method of making high pressure stress film comprises the following steps: to feed predecessor; Feed silicomethane and ammonia; Utilize predecessor and this silicomethane and this ammonia gas react, comprise the high pressure stress film of Si-O-R key with formation, wherein this predecessor comprises tetramethylsilane, aldehydes or carboxylic acids.
16. method as claimed in claim 15, wherein this predecessor comprises ethers.
17. method as claimed in claim 15, wherein the flow of this silicomethane is between 30sccm to 3000sccm.
18. method as claimed in claim 15, wherein the flow of this ammonia is between 30sccm to 2000sccm.
19. method as claimed in claim 15, the power that wherein forms the high frequency of this high pressure stress film and low frequency radio wave is between 50 watts to 3000 watts.
20. method as claimed in claim 15, wherein this Si-O-R key comprises Si-O-(CH
3) key.
21. a strain silicon metal oxide semiconductor transistor comprises:
The semiconductor-based end;
Grid was located on this semiconductor-based end;
At least one sidewall is located on the sidewall of this grid;
Regions and source was located in this semiconductor-based end;
A plurality of metal silicide layers are located at respectively on this top portions of gates and this regions and source surface; And
High pressure stress film be arranged on this grid, this sidewall and this regions and source surface, and this high pressure stress film comprises Si-(CH
3) key,
Wherein, this high pressure stress film forms by making predecessor and silicomethane and ammonia gas react, and this predecessor comprises tetramethylsilane, aldehydes or carboxylic acids.
22. strain silicon metal oxide semiconductor transistor as claimed in claim 21 comprises that also gate dielectric is located at this grid below.
23. strain silicon metal oxide semiconductor transistor as claimed in claim 21 comprises that also laying is arranged between this gate lateral wall and this sidewall.
24. strain silicon metal oxide semiconductor transistor as claimed in claim 21 comprises that also the source/drain elongated area was located in this semiconductor-based end of this sidewall below.
25. strain silicon metal oxide semiconductor transistor as claimed in claim 21, wherein this metal silicide layer comprises the nickle silicide metal level.
26. strain silicon metal oxide semiconductor transistor as claimed in claim 21, wherein this strain silicon metal oxide semiconductor transistor is the PMOS transistor.
27. a strain silicon metal oxide semiconductor transistor comprises:
The semiconductor-based end;
Grid was located on this semiconductor-based end;
At least one sidewall is located on the sidewall of this grid;
Regions and source was located in this semiconductor-based end;
A plurality of metal silicide layers are located at respectively on this top portions of gates and this regions and source surface; And
High pressure stress film is arranged on this grid, this sidewall and this regions and source surface, and this high pressure stress film comprises the Si-O-R key,
Wherein, this high pressure stress film forms by making predecessor and silicomethane and ammonia gas react, and this predecessor comprises tetramethylsilane, aldehydes or carboxylic acids.
28. strain silicon metal oxide semiconductor transistor as claimed in claim 27 comprises that also gate dielectric is located at this grid below.
29. strain silicon metal oxide semiconductor transistor as claimed in claim 27 comprises that also laying is arranged between this gate lateral wall and this sidewall.
30. strain silicon metal oxide semiconductor transistor as claimed in claim 27 comprises that also the source/drain elongated area was located in this semiconductor-based end of this sidewall below.
31. strain silicon metal oxide semiconductor transistor as claimed in claim 27, wherein this metal silicide layer comprises the nickle silicide metal level.
32. strain silicon metal oxide semiconductor transistor as claimed in claim 27, wherein this strain silicon metal oxide semiconductor transistor is the PMOS transistor.
33. strain silicon metal oxide semiconductor transistor as claimed in claim 27, wherein this Si-O-R key comprises Si-O-(CH
3) key.
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| CN102136426A (en) * | 2010-01-27 | 2011-07-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN112038294B (en) * | 2020-11-04 | 2021-04-09 | 晶芯成(北京)科技有限公司 | Semiconductor device and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508067A (en) * | 1993-09-24 | 1996-04-16 | Applied Materials, Inc. | Deposition of silicon nitride by plasma-enchanced chemical vapor deposition |
| US6630413B2 (en) * | 2000-04-28 | 2003-10-07 | Asm Japan K.K. | CVD syntheses of silicon nitride materials |
| CN1630028A (en) * | 2003-11-19 | 2005-06-22 | 松下电器产业株式会社 | Method and apparatus for fabricating semiconductor device |
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2006
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508067A (en) * | 1993-09-24 | 1996-04-16 | Applied Materials, Inc. | Deposition of silicon nitride by plasma-enchanced chemical vapor deposition |
| US6630413B2 (en) * | 2000-04-28 | 2003-10-07 | Asm Japan K.K. | CVD syntheses of silicon nitride materials |
| CN1630028A (en) * | 2003-11-19 | 2005-06-22 | 松下电器产业株式会社 | Method and apparatus for fabricating semiconductor device |
Non-Patent Citations (2)
| Title |
|---|
| JP特开2006-249046A 2006.09.21 |
| 通式(I),化合物No.1、4、6、8. |
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