CN101189727A - 包括具有限定半导体结的区域的超晶格的半导体器件 - Google Patents

包括具有限定半导体结的区域的超晶格的半导体器件 Download PDF

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CN101189727A
CN101189727A CNA200680016440XA CN200680016440A CN101189727A CN 101189727 A CN101189727 A CN 101189727A CN A200680016440X A CNA200680016440X A CN A200680016440XA CN 200680016440 A CN200680016440 A CN 200680016440A CN 101189727 A CN101189727 A CN 101189727A
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semiconductor device
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罗伯特·J.·梅尔斯
罗伯特·约翰·史蒂芬森
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RJ Mears LLC
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Abstract

一种具有包含多个堆叠层组的超晶体结构的半导体器件。超晶格结构的每个层组可以包含限定了基本硅部分和其上的能带修改层的多个基本硅单层。该能带修改层可以含有被约束于相邻的基础硅部分的晶格中的至少一个非半导体单层。在该半导体元件中还可以包含限定至少一个半导体结的至少一对相反掺杂的区域。

Description

包括具有限定半导体结的区域的超晶格的半导体器件
技术领域
[0001]本发明涉及半导体领域，更具体而言，本发明涉及基于能带工程以及相关方法的具有增强的特性的半导体。
背景技术
[0002]目前已经提出了诸如增加载流子的迁移率的结构和技术，用以提高半导体器件的性能。例如，属于Currie等人的美国专利申请No.2003/0057416公开了一种硅、硅锗、和松弛硅的应变材料层，并且还包括无杂质区域，否则会使半导体的性能退化。所获得的上部硅层中的双轴应变可以改变载流子的迁移率从而使元件更高速和/或更低功耗。已公开的属于Fitzgerald等人的美国专利申请No.2003/0034529公开了一种基于类似的应变硅技术的CMOS反相器。
[0003]属于Takagi的美国专利申请中公开了一种半导体器件，包括在硅层之间的硅和碳层，以使得第二硅层的导带和价带受到拉伸应变。由施加在栅极上的电场感生出的、有效质量较小的电子被约束在第二硅层中，从而使n沟道型MOSFET具有更高的迁移率。
[0004]属于Ishibashi等人的美国专利No.4,937,204公开了一种超晶格，其中少于八个单层的多个层交替地外延生长，其中多个层包括二元化合物半导体层或一部分(a fraction)。主电流的方向与该超晶格结构的层垂直。
[0005]属于Wang等人的美国专利No.5,357,119公开了一种通过减少超晶格中的合金散射而实现的更高迁移率的Si-Ge短周期超晶格结构。与之类似，属于Candelaria的美国专利No.5,683,934公开了一种迁移率提高了的MOSFET，它具有包含合金的沟道层，在这种由硅和第二材料构成的合金中，第二材料以使沟道层处于受张应力的状态的百分比取代地出现在硅晶格中。
[0006]属于Tsu的美国专利No.5,216,262公开了一种量子阱结构，它包含两个势垒区和夹在势垒之间的外延生长的半导体薄层。每个势垒区包含交替的SiO2/Si层，厚度通常为2至6个单层。在势垒之间夹着厚的多的硅的部分。
[0007]作者为Tsu，于2000年9月6日在线发表于Applied Physicsand Materials Science&Processing，391-402页的题目为“Phenomenain silicon nanostructure devices”的文章公开了一种硅和氧的半导体-原子超晶格(SAS)。具体地，该Si/O超晶格可用于硅量子和发光器件。尤其是，绿色电致发光二极管结构已经制成并投入测试。在该二极管结构中电流的方向是垂直的，即垂直于SAS。所公开的SAS可以包含由诸如氧原子、CO分子这样的吸收态物质所分隔的半导体层。超出氧的吸收单层的硅生长被描述为具有相当低的缺陷密度的外延生长。一种SAS结构包括厚度为1.1nm的硅部分，该硅部分约为八个硅原子层；另一种结构的硅的厚度为上述厚度的两倍。作者为Luo等人，发表于Physical Review Letters，89卷，No.7(2002年8月12日)的题目为“Chemical Design of Direct-Gap Light-Emitting Silicon”对Tsu提出的发光SAS结构作了进一步的探讨。
[0008]已发表的属于Wang、Tsu和Lofgren的国际专利申请WO02/103,767A1公开了一种包含薄硅和氧、碳、氮、磷、锑、砷或氢的势垒基本单元(barrier building block)，由此将垂直通过晶格的电流的大小减小了不止四个量级。绝缘层/势垒允许低缺陷外延硅紧接着绝缘层沉积。
[0009]已发表的属于Mears等人的英国专利申请2,347,520公开了非周期光子带隙(APBG)结构的原理可以适用于电子带隙工程。尤其是，该申请公开了可以通过调整诸如能带最小值的位置、有效质量等材料参数，从而生成新的具有所需能带结构特性的非周期性材料。诸如电导率、热导率和介电常数或导磁率等其他参数也同样可以依需要而设计在材料中。
[0010]虽然在增加半导体器件的电荷载流子迁移率方面，材料工程已经作了相当的努力，但仍需更大的改进。更高的迁移率可以增加器件的速度和/或降低器件的功耗。更高的迁移率同样可以使半导体器件在不断向小型化发展的同时依旧保持其性能。
发明内容
[0011]基于上述背景，本发明的目的之一是提供一种具有相对高的电荷载流子迁移率的半导体器件。
[0012]本发明的上述及其他目标、特点和优点是通过一种可以具有超晶格结构的半导体器件提供的，超晶格结构包含多个堆叠的层组。超晶格的每个层组包含多个堆叠的基础硅单层，它们限定了基础硅部分和其上面的能带修改层。该能带修改层可以包含被约束在相邻的基础半导体部分的晶格中的至少一个非半导体单层约束。在该超晶格中还可以包括限定至少一个半导体结的至少一对相反掺杂的区域。因此，该半导体器件可以有利地应用在很多方面，例如二极管、场效应晶体管或双极晶体管、光学器件等。
[0013]所述至少一对相反掺杂的区域包括彼此直接接触的第一区和第二区。替代地，上述第一区和第二区也可以相互隔开。另外，所述至少一对相反掺杂的区域可以在垂直方向上排列，使得所述至少一个半导体结在水平方向上延伸；或者，也可以在水平方向上排列，使得所述至少一个半导体结在垂直方向上延伸。
[0014]每个能带修改层可以包含非半导体，例如氧、氮、氟和碳-氧。另外，每个能带修改层的厚度可以为一个单层的厚度，每个基础硅部分的厚度可小于八个单层的厚度。该超晶格还可以在最上面的层组之上包含基础半导体帽层。另外，所有的基础硅部分可以具有相同单层数目的厚度，或者至少一些基础硅部分具有不同的单层数目的厚度。
附图说明
[0015]图1-4是在本发明中，不同实施方案的半导体器件部分的横截面示意图。
[0016]图5为经过大比例放大后的图1所示的超晶格的横截面示意图。
[0017]图6中的原子结构的透视示意图，显示的是图1所示超晶格的一部分。
[0018]图7是另一种实施方案中经大比例放大后的超晶格的横截面示意图，该超晶格有可以应用于图1所示的器件。
[0019]图8A是从伽马(gamma)点(G)计算出的能带结构图，它包括了现有技术下的体硅以及图1、5、6中所示的4/1 Si/O超晶格。
[0020]图8B是从Z点计算出的能带结构图，它包括了现有技术下的体硅以及图1、5、6中所示的4/1 Si/O超晶格。
[0021]图8C是从伽马点和Z点计算出的能带结构图，它包括了现有技术下的体硅以及图7中所示的5/1/3/1 Si/O超晶格。
具体实施方案
[0022]结合表示了本发明的具体实施方案的附图对本发明作进一步的充分说明。然而，本发明可以以很多其他形式实施，而不仅限于这里所阐述的方案。更确切的说，这些实施方案的提供是为了使公开内容充分完整，并且能够使本领域的技术人员充分了解本发明的应用范围。相似的附图标记表示相似的元素，而带撇号和多重撇号的附图标记表示其他实施方案中的相似的元素。
[0023]本发明涉及在原子或分子水平上调整半导体材料的性质，从而使半导体器件的性能得到改进。此外，本发明还涉及鉴别、创造和使用用于半导体器件的导电路径的改进了的材料。
[0024]申请人系统阐述了在此所述的特定的超晶格减小了载流子的有效质量，并使电荷载流子的迁移率得以提高，但本发明并不限于此。在文献中有效质量被以不同定义所描述。申请人用“传导率有效质量张量倒数(conductivity reciprocal effective masstensor)”Me -1、Mh -1来衡量有效质量的改进，其中Me -1、Mh -1分别代表电子和空穴的传导率有效质量张量倒数，定义如下：
对于电子，
M e , ij - 1 ( E F , T ) = Σ E > E F ∫ B . Z . ( ▿ k E ( k , n ) ) i ( ▿ k E ( k , n ) ) j ∂ f ( E ( k , n ) , E F , T ) ∂ E d 3 k Σ E > E F ∫ B . Z . f ( E ( k , n ) , E F , T ) d 3 k
对于空穴，
M h , ij - 1 ( E F , T ) = - &Sigma; E < E F &Integral; B . Z . ( &dtri; k E ( k , n ) ) i ( &dtri; k E ( k , n ) ) j &PartialD; f ( E ( k , n ) , E F , T ) &PartialD; E d 3 k &Sigma; E < E F &Integral; B . Z . ( 1 - f ( E ( k , n ) , E F , T ) ) d 3 k
其中f表示费米-狄拉克分布，EF表示费米能量，T表示温度，E(k，n)表示电子处于波矢为k、第n能带状态时所对应的能量，指标i和j指笛卡尔坐标系的x、y、z，积分在布里渊区(B.Z.)进行，对于电子在具有高于费米能量的能量的能带进行求和，而对于空穴在具有低于费米能量的能量的能带进行求和。
[0025]申请人对于传导率有效质量张量倒数的定义使得传导率有效质量张量倒数越大，对应材料的传导率的张量分量越大。同时，申请人系统阐述了本发明中描述的超晶格设定了传导率有效质量张量倒数的数值，以提高材料的导电特性，典型地，例如对于电荷载流子传输所优选的方向，但本发明并不限于此。适当的张量要素的倒数被称为传导率有效质量。换言之，为了描述半导体材料的结构，上述的电子/空穴的传导率有效质量被用于区分改进的材料，上述的传导率有效质量是在指定的载流子传输的方向计算得出的.
[0026]应用上述标准即可针对具体目的，选择具有改进的能带结构的材料。参照图1，这样的一个例子是包含超晶格25的半导体器件20，它具有限定了半导体结23的一对相反掺杂的区域21、22。该例中，第一区21具有P型导电性，第二区22具有N型导电性，从而形成了P/N结23。半导体器件20的P/N结的结构使其可以有利地应用在很多方面。本领域技术人员可以理解，这些方面例如包括二极管、场效应晶体管或双极晶体管、光学器件等。
[0027]在示例中，第一区21和第二区22彼此直接接触。第一区121和第二区22沿横向排列(例如，并排排列)，使得半导体结23基本在垂直方向上延伸。在图2所示的另一个结构中，第一区21和第二区22也可以沿垂直方向排列，使得半导体结23’基本在水平方向上延伸。
[0028]在图3所示的又一种结构中，半导体器件20”可以包括相邻超晶格的半导体层24”。在示例中，半导体层24”在超晶格25”的垂直的上方，但本领域技术人员可以理解，在其它实施方案中，该半导体层也可以在超晶格的下方或与超晶格横向相邻。在此，P型掺杂剂涵盖整个超晶格25”，N型掺杂涵盖整个半导体层24”，但在其它实施方案中掺杂剂所占的部分可以较少。
[0029]在又一种结构中，第一区21和第二区22可以相互隔开。参见图4，半导体器件20具有P-i-N结构，在具有N型掺杂剂的半导体层24与具有P型掺杂剂的超晶格25之间夹着本征半导体层26。当然，本征区也可以用于N区和P区均位于超晶格25内的情况，例如在器件20的第一区21和第二区22之间、或者在器件20’的第一区21’和第二区22’之间。
[0030]应当指出的是，在一些实施方案中，可以利用多对相反掺杂的区域21、22形成多个半导体(即PN)结。此外，本领域的技术人员会意识到，多于一个的第一区21或第二区22可以与相反掺杂的区域一起形成PNP或NPN结构。此外还应理解，第一区21和第二区22并不总是沿垂直或水平方向排列。也就是说，区域21、22可以在第一斜线方向排列从而使半导体结23在横穿该第一斜线方向的第二斜线方向延伸。本领域技术人员会意识到，这可以通过成角度的掺杂剂注入方式实现。
[0031]参照图5和图6，材料或结构以超晶格25的形式存在，其结构在原子或分子水平被控制，而且可以通过现有的原子层或分子层沉积技术形成。超晶格25包含以堆叠关系排列的多个层组45a-45n，详情参见图5所示的横截面示意图。
[0032]超晶格25中的每个层组45a-45n示意地包含多个堆叠的基础半导体单层46，它限定了基础半导体部分46a-46n及其上面的能带修改层50。图5中，为了图示的清晰，能带修改层50用加点的区域来表示。
[0033]能带修改层50示意地包含一个非半导体单层，它被约束在相邻的基础半导体部分的晶格中。在其它的实施方案中，这样的非半导体单层可以不止一个。应该说明的是，此处的非半导体或半导体单层是指，用于做单层的材料当其以体形式存在时为非半导体或半导体。也就是说，本领域技术人员会理解，某种材料、诸如半导体材料的单独的单层所表现出的性质不一定和当它以体或相对较厚的层的形式形成时所表现的性质相同。
[0034]申请人系统阐述了能带修改层50和相邻的基础半导体部分46a-46n使得超晶格25在平行于层的方向上具有比现有结构更小的传导率有效质量，但本发明并不限于此。也就是说，这个平行的方向垂直于堆叠方向。能带修改层50也使得超晶格25具有共同的能带结构。
[0035]另外，由于具有比现有结构更小的传导率有效质量，半导体器件，如示例中所举的MOSFET 20，具有更高的电荷载流子迁移率。在一些实施方案中，作为本发明所实现的能带工程技术的结果，超晶格25可以进一步具有实质上的直接能带隙，这对于例如光电器件尤其有利。以下将对此进一步详细说明。
[0036]本领域技术人员会理解，MOSFET的源/漏区22、23和栅35可以被视为引起电荷载流子沿平行于堆叠的层组45a-45n的方向传输通过超晶格的区域。其它这样的区域也被包括在本发明中。
[0037]超晶格25在上部的层组45n之上还示意地包含帽层52。该帽层52可包含多个基础半导体单层46。帽层52可包含2至100个基础半导体单层46，优选为10至50个单层。
[0038]每个基础半导体部分46a-46n可以从包含IV族半导体、III-V族半导体、和II-VI族半导体的组中选择。当然，本领域技术人员会理解，上述IV族半导体也包括IV-IV半导体。具体地例如，基础半导体可至少包含硅和锗之一。
[0039]每个能带修改层50例如可以包含从包括氧、氮、氟和碳-氧的组中选择的非半导体。同时，为了更容易制造，这种非半导体还通过下一层的沉积而优选地具有热稳定性。本领域技术人员会理解，在其它实施方案中，非半导体还可以是与半导体工艺兼容的其它无机或有机元素或化合物。具体地例如，基础半导体可至少包含硅和锗之一。
[0040]应该指出的是，文中所说的单层包括单原子层和单分子层。同时还应指出，由一个单层提供的能带修改层50同样也包含并非所有可能位置均被占满的单层。例如，具体参照图6的原子结构图，4/1重复结构以硅为基础半导体材料，以氧为能带修改层材料。其中，对于氧的可能的位置只有一半被占据。
[0041]本领域技术人员会意识到，在其他实施方案中，和/或使用其它材料，不必一定是这种半占满位的情况。实际上，对于原子沉积领域的技术人员，即使从这张示意图也可以看出，给定的单层中的单个氧原子并不是精确地排列在同一平面内的。例如，对于氧的可能的位置来说，虽然1/8至1/2的位置被占据是优选的，但其它的占位比例也可用于某些实施方案中。
[0042]目前硅和氧被广泛应用于传统的半导体工艺中，所以，制造商可以方便地使用本专利中所述的材料。原子或单层沉积技术如今也被广泛的应用。因此，本领域技术人员会意识到，结合本发明的超晶格25的半导体器件易于被采用和实现。
[0043]申请人系统阐述了对于超晶格，例如Si/O超晶格，硅单层的数量优选为7个或更少，以使得超晶格的能带是共同的或是整体相对均匀的，这样才能达到所需的优点，但本发明并不限于此。图5和6中所示的对于Si/O的4/1重复结构被作为模型说明了在X方向上电子和空穴迁移率的提高。例如，计算出的电子的传导率有效质量(对于体硅呈各向同性)为0.26，而对于4/1氧化硅超晶格在X方向上电子的传导率有效质量为0.12，其比例为0.46。同样地，计算得到的空穴的传导率有效质量为0.36，而对于4/1氧化硅超晶格在X方向上该值为0.16，其比例为0.44。
[0044]对于某些半导体器，具备上述的方向特异性特征是有利的；然而其它器件可能得益于迁移率在平行于层组的任意方向上更均匀的提高。本领域技术人员会理解，电子和空穴迁移率均有所提高、或者二者中仅有一种的迁移率有所提高可能也会是有利的。
[0045]对于超晶格25的4/1 Si/O的实施例，无论对于电子还是空穴，较低的传导率有效质量均可达到小于现有结构的2/3。当然，本领域技术人员会理解，超晶格25中还可以含有至少一种导电类型的掺杂剂。
[0046]参照图7，说明了本发明的另一个实施方式的具有不同性质的超晶格25’。在该实施方案中，超晶格的重复模式为3/1/5/1。更具体而言，最底层的基础半导体部分46a’具有3个单层，次底层的基础半导体部分46b’具有5个单层。这种模式在整个超晶格25’重复进行。每个能带修改层50’可以包含一个单层。对于包含Si/O的这种超晶格25’，其电荷载流子迁移率的提高不依赖于层所在平面的取向。图7中其它未特别指出的要素与图5中所述要素相似，这里不再做进一步说明。
[0047]在一些器件的实施方案中，超晶格中的所有基础半导体部分可以具有相同单层数目的厚度。在其他方案中，至少某些部分的基础半导体部分具有不同单层数目的厚度。另外还有一些方案中，所有基础半导体部分可以具有不同的单层数目的厚度。
[0048]在图8A-8C中，表示了利用密度函数理论(DFT)计算出的能带结构。本领域内众所周知，DFT低估了能带隙的绝对值。因此，可以通过适当的“剪裁修正”来对带隙之上的所有能带进行移动。但是，能带的形状已知是更加可靠的。垂直方向的能量轴应该据此解释。
[0049]图8A给出了对于体硅(以连续曲线表示)和图5、6所示的4/1 Si/O超晶格25(以点划线表示)，从伽马(gamma)点(G)计算得出的能带结构。方向指的是4/1 Si/O结构的晶胞，而不是传统的Si晶胞，虽然在图中(001)方向确实对应传统的Si晶胞的(001)方向。这样，示出了Si的导带最小值(conduction band minimum)。图中的方向(100)和(010)分别对应传统的Si晶胞的(110)和(-110)方向。本领域技术人员会理解，图中的Si的能带被交叠起来是为了表示它们处于4/1 Si/O结构的倒易晶格(reciprocal lattice)方向上。
[0050]可以看出，和体硅(Si)对比，4/1 Si/O结构的导带最小值位于伽马点，而价带最小值出现在(001)方向上的布里渊区的边缘处，称之为Z点。还可以发现，与Si的导带最小值的曲率相比，4/1 Si/O的导带最小值的曲率更大，这是因为附加的氧层引起的扰动造成了能带分裂。
[0051]图8B给出了体硅(以连续的线表示)和图5、6所示的4/1Si/O超晶格25(以点划线表示)的从Z点计算得出的能带结构。该图反映了(100)方向上价带曲率的增加。
[0052]图8C给出了体硅(以连续的线表示)和图7所示的5/1/3/1Si/O超晶格25’(以点划线表示)从伽马点和Z点计算得出的能带结构。由于5/1/3/1 Si/O结构的对称性，在(100)和(010)方向上计算得出的能带结构相同。因此在平行于层的平面内，即垂直于(001)堆叠方向上，传导率有效质量被认为是各向同性的。应该注意到，在5/1/3/1Si/O结构的例子中，导带最小值和价带最大值均在Z点或接近于Z点。
[0053]虽然曲率的增加反映了有效质量的减小，但通过计算传导率有效质量张量倒数可以进行适当的比较和辨别。这使得申请人进一步系统阐述了5/1/3/1超晶格25’应该具有实质上的直接能带隙。本领域的技术人员会意识到，光跃迁的适当的矩阵元素是区别直接能带隙与间接能带隙另一个指标。
[0054]本发明的方法方面是为了制造半导体器件20，可以包括形成含有多个堆叠层组45的超晶格25。超晶格25的每一个层组45包含多个堆叠的基础半导体单层46，它限定了基础半导体部分46a及其上面的能带修改层50。能带修改层50可以包含被约束在相邻的基础半导体部分46的晶格中的至少一个非半导体单层。该方法还可以包括在超晶格25内形成限定了至少一个半导体结23的至少一对相反掺杂的区域21、22。
[0055]本发明另外一个相关方法可以包括形成与超晶格25”相邻的半导体层24”，该半导体层中至少包含具有第一导电性的掺杂剂(在图3中为N型掺杂剂)的第一区。可以在超晶格中形成至少一个具有第二导电性的掺杂剂(示例中为P型掺杂剂)的第二区，它与上述的第一区一起限定至少一个半导体结。
[0056]本发明的其它特点可以查询相关的申请，它们是：METHOD FOR MAKING A SEMICONDUCTOR DEVICEINCLUDING A SUPERLATTICE WITH REGIONS DEFINING ASEMICONDUCTOR JUNCTION，代理人案件号为62683；SEMIC ONDUCTOR DEVICE INCLUDING A SUPERLATTICEAND ADJACENT SEMICONDUCTOR LAYER WITH DOPEDREGIONS DEFINING A SEMICONDUCTOR JUNCTION，代理人案件号为62693；METHOD FOR MAKING A SEMICONDUCTORDEVICE INCLUDING A SUPERLATTICE AND ADJACENTSEMICONDUCTOR LAYER WITH DOPED REGIONS DEFININGA SEMICONDUCTOR JUNCTION，代理人案件号62694。在此通过引用将其全部内容包含在本说明书中。
[0057]本领域的技术人员根据上述说明及其相关附图的教导可以获得本发明的修改和其它实施方案。因此，应当理解的是，本发明不仅限于所公开的具体实施方案，其相关的修改和其它实施方案也在所附的权利要求的范围之内。

Claims (20)

1.一种半导体器件，包括：
含有多个堆叠层组的超晶格；
所述超晶格的每个层组包含多个堆叠的基础硅单层，这些单层限定了基础硅部分及其上面的能带修改层；
所述能带修改层包含被约束在相邻的基础硅部分的晶格中的至少一个非半导体单层；和
在所述超晶格中包括限定至少一个半导体结的至少一对相反掺杂的区域。
2.权利要求1中的半导体器件，其中，所述至少一对相反掺杂的区域包括彼此直接接触的第一区和第二区。
3.权利要求1中的半导体器件，其中，所述至少一对相反掺杂的区域包括彼此相互隔开的第一区和第二区。
4.权利要求1中的半导体器件，其中，所述至少一对相反掺杂的区域沿垂直方向排列，使得所述至少一个半导体结在横向延伸。
5.权利要求1中的半导体器件，其中，所述至少一对相反掺杂的区域沿水平方向排列，使得所述至少一个半导体结在垂直方向延伸。
6.权利要求1中的半导体器件，其中，每个能带修改层含有氧元素。
7.权利要求1中的半导体器件，其中，每个能带修改层包含从包括氧、氮、氟、和碳-氧的组中选择的非半导体。
8.权利要求1中的半导体器件，其中，每个能带修改层为一个单层的厚度。
9.权利要求1中的半导体器件，其中，每个基础硅部分小于八个单层的厚度。
10.权利要求1中的半导体器件，其中，所述超晶格还包括在最上面的层组上的基础半导体帽层。
11.权利要求1中的半导体器件，其中，所有的基础硅部分具有相同数目的单层的厚度。
12.权利要求1中的半导体器件，其中，至少某些基础硅部分具有不同数目的单层的厚度。
13.一种半导体器件，包括：
含有多个堆叠层组的超晶格；
所述晶格的每个层组包含多个堆叠的基础硅单层，这些单层限定了基础硅部分及其上面的能带修改层；
所述能带修改层包含被约束在相邻的基础硅部分的晶格中的至少一个氧单层；和
在所述超晶格中包括限定至少一个半导体结的至少一对相反掺杂的区域。
14.权利要求13中的半导体器件，其中，所述至少一对相反掺杂的区域沿垂直方向排列，使得所述至少一个半导体结在横向延伸。
15.权利要求13中的半导体器件，其中，所述至少一对相反掺杂的区域沿水平方向排列，使得实施至少一个半导体结在垂直方向延伸。
16.权利要求13中的半导体器件，其中，每个能带修改层的厚度为一个单层。
17.权利要求13中的半导体器件，其中，每个基础硅部分的厚度小于八个单层。
18.权利要求13中的半导体器件，其中，所述超晶格还包括在最上面的层组上的基础半导体帽层。
19.权利要求13中的半导体器件，其中，所有的基础硅部分具有相同数目的单层的厚度。
20.权利要求13中的半导体器件，其中，至少某些基础硅部分具有不同数目的单层的厚度。
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Publication number Priority date Publication date Assignee Title
US7294848B2 (en) * 2005-05-26 2007-11-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Light-emitting Group IV semiconductor devices
KR101855023B1 (ko) 2013-11-22 2018-05-04 아토메라 인코포레이티드 정지층을 통한 초격자 펀치를 포함하는 수직 반도체 디바이스 및 관련된 방법
CN105900241B (zh) 2013-11-22 2020-07-24 阿托梅拉公司 包括超晶格耗尽层堆叠的半导体装置和相关方法
WO2015191561A1 (en) 2014-06-09 2015-12-17 Mears Technologies, Inc. Semiconductor devices with enhanced deterministic doping and related methods
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US9899479B2 (en) 2015-05-15 2018-02-20 Atomera Incorporated Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
WO2016196600A1 (en) 2015-06-02 2016-12-08 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9558939B1 (en) 2016-01-15 2017-01-31 Atomera Incorporated Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source
WO2017197108A1 (en) 2016-05-11 2017-11-16 Atomera Incorporated Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods
US10249745B2 (en) 2016-08-08 2019-04-02 Atomera Incorporated Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice
US10107854B2 (en) 2016-08-17 2018-10-23 Atomera Incorporated Semiconductor device including threshold voltage measurement circuitry
US10410880B2 (en) 2017-05-16 2019-09-10 Atomera Incorporated Semiconductor device including a superlattice as a gettering layer
US10056477B1 (en) * 2017-05-24 2018-08-21 Palo Alto Research Center Incorporated Nitride heterojunction bipolar transistor with polarization-assisted alloy hole-doped short-period superlattice emitter or collector layers
US10636879B2 (en) 2017-06-13 2020-04-28 Atomera Incorporated Method for making DRAM with recessed channel array transistor (RCAT) including a superlattice
US10109479B1 (en) 2017-07-31 2018-10-23 Atomera Incorporated Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice
EP3669401B1 (en) 2017-08-18 2023-08-02 Atomera Incorporated Manufacturing method for a semiconductor device including the removal of non-monocrystalline stringer adjacent a superlattice-sti interface
US10608043B2 (en) 2017-12-15 2020-03-31 Atomera Incorporation Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
US10367028B2 (en) 2017-12-15 2019-07-30 Atomera Incorporated CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
US10361243B2 (en) 2017-12-15 2019-07-23 Atomera Incorporated Method for making CMOS image sensor including superlattice to enhance infrared light absorption
US10355151B2 (en) 2017-12-15 2019-07-16 Atomera Incorporated CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
US10529757B2 (en) 2017-12-15 2020-01-07 Atomera Incorporated CMOS image sensor including pixels with read circuitry having a superlattice
US10529768B2 (en) 2017-12-15 2020-01-07 Atomera Incorporated Method for making CMOS image sensor including pixels with read circuitry having a superlattice
US10615209B2 (en) 2017-12-15 2020-04-07 Atomera Incorporated CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
US10396223B2 (en) 2017-12-15 2019-08-27 Atomera Incorporated Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk
US10608027B2 (en) 2017-12-15 2020-03-31 Atomera Incorporated Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
US10304881B1 (en) 2017-12-15 2019-05-28 Atomera Incorporated CMOS image sensor with buried superlattice layer to reduce crosstalk
US10276625B1 (en) 2017-12-15 2019-04-30 Atomera Incorporated CMOS image sensor including superlattice to enhance infrared light absorption
US10461118B2 (en) 2017-12-15 2019-10-29 Atomera Incorporated Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
US10777451B2 (en) 2018-03-08 2020-09-15 Atomera Incorporated Semiconductor device including enhanced contact structures having a superlattice
US10727049B2 (en) 2018-03-09 2020-07-28 Atomera Incorporated Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
US10468245B2 (en) 2018-03-09 2019-11-05 Atomera Incorporated Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
EP3776073A1 (en) 2018-04-12 2021-02-17 Atomera Incorporated Semiconductor device and method including vertically integrated optical and electronic devices and comprising a superlattice
WO2019199926A1 (en) 2018-04-12 2019-10-17 Atomera Incorporated Device and method for making an inverted t channel field effect transistor (itfet) including a superlattice
US10566191B1 (en) 2018-08-30 2020-02-18 Atomera Incorporated Semiconductor device including superlattice structures with reduced defect densities
US10811498B2 (en) 2018-08-30 2020-10-20 Atomera Incorporated Method for making superlattice structures with reduced defect densities
US20200135489A1 (en) * 2018-10-31 2020-04-30 Atomera Incorporated Method for making a semiconductor device including a superlattice having nitrogen diffused therein
US10580866B1 (en) 2018-11-16 2020-03-03 Atomera Incorporated Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
US10580867B1 (en) 2018-11-16 2020-03-03 Atomera Incorporated FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance
US10818755B2 (en) 2018-11-16 2020-10-27 Atomera Incorporated Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
US10840335B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance
US10847618B2 (en) 2018-11-16 2020-11-24 Atomera Incorporated Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance
US10593761B1 (en) 2018-11-16 2020-03-17 Atomera Incorporated Method for making a semiconductor device having reduced contact resistance
US10840337B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Method for making a FINFET having reduced contact resistance
US10854717B2 (en) 2018-11-16 2020-12-01 Atomera Incorporated Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance
US10840336B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods
US11329154B2 (en) 2019-04-23 2022-05-10 Atomera Incorporated Semiconductor device including a superlattice and an asymmetric channel and related methods
US10879357B1 (en) 2019-07-17 2020-12-29 Atomera Incorporated Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice
US10825902B1 (en) 2019-07-17 2020-11-03 Atomera Incorporated Varactor with hyper-abrupt junction region including spaced-apart superlattices
US10868120B1 (en) 2019-07-17 2020-12-15 Atomera Incorporated Method for making a varactor with hyper-abrupt junction region including a superlattice
US10840388B1 (en) 2019-07-17 2020-11-17 Atomera Incorporated Varactor with hyper-abrupt junction region including a superlattice
US10937868B2 (en) 2019-07-17 2021-03-02 Atomera Incorporated Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices
US11183565B2 (en) 2019-07-17 2021-11-23 Atomera Incorporated Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods
US10937888B2 (en) 2019-07-17 2021-03-02 Atomera Incorporated Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices
US10825901B1 (en) 2019-07-17 2020-11-03 Atomera Incorporated Semiconductor devices including hyper-abrupt junction region including a superlattice
US11437486B2 (en) 2020-01-14 2022-09-06 Atomera Incorporated Methods for making bipolar junction transistors including emitter-base and base-collector superlattices
US11177351B2 (en) 2020-02-26 2021-11-16 Atomera Incorporated Semiconductor device including a superlattice with different non-semiconductor material monolayers
US11302823B2 (en) 2020-02-26 2022-04-12 Atomera Incorporated Method for making semiconductor device including a superlattice with different non-semiconductor material monolayers
US11075078B1 (en) 2020-03-06 2021-07-27 Atomera Incorporated Method for making a semiconductor device including a superlattice within a recessed etch
US11469302B2 (en) 2020-06-11 2022-10-11 Atomera Incorporated Semiconductor device including a superlattice and providing reduced gate leakage
US11569368B2 (en) 2020-06-11 2023-01-31 Atomera Incorporated Method for making semiconductor device including a superlattice and providing reduced gate leakage
US11837634B2 (en) 2020-07-02 2023-12-05 Atomera Incorporated Semiconductor device including superlattice with oxygen and carbon monolayers
EP4295409A1 (en) 2021-03-03 2023-12-27 Atomera Incorporated Radio frequency (rf) semiconductor devices including a ground plane layer having a superlattice and associated methods
US11810784B2 (en) 2021-04-21 2023-11-07 Atomera Incorporated Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US11923418B2 (en) 2021-04-21 2024-03-05 Atomera Incorporated Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US11682712B2 (en) 2021-05-26 2023-06-20 Atomera Incorporated Method for making semiconductor device including superlattice with O18 enriched monolayers
US11728385B2 (en) 2021-05-26 2023-08-15 Atomera Incorporated Semiconductor device including superlattice with O18 enriched monolayers
US11631584B1 (en) 2021-10-28 2023-04-18 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to define etch stop layer
US11721546B2 (en) 2021-10-28 2023-08-08 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485128A (en) 1981-11-20 1984-11-27 Chronar Corporation Bandgap control in amorphous semiconductors
JPH0656887B2 (ja) 1982-02-03 1994-07-27 株式会社日立製作所 半導体装置およびその製法
US4594603A (en) 1982-04-22 1986-06-10 Board Of Trustees Of The University Of Illinois Semiconductor device with disordered active region
JPS6127681A (ja) 1984-07-17 1986-02-07 Res Dev Corp Of Japan 超格子構造のチヤネル部をもつ電界効果トランジスタ
US4882609A (en) 1984-11-19 1989-11-21 Max-Planck Gesellschaft Zur Forderung Der Wissenschafter E.V. Semiconductor devices with at least one monoatomic layer of doping atoms
JPS61145820A (ja) 1984-12-20 1986-07-03 Seiko Epson Corp 半導体薄膜材料
JPS61210679A (ja) 1985-03-15 1986-09-18 Sony Corp 半導体装置
JPS61220339A (ja) 1985-03-26 1986-09-30 Nippon Telegr & Teleph Corp <Ntt> 半導体材料特性の制御方法
JPS62219665A (ja) 1986-03-20 1987-09-26 Fujitsu Ltd 超格子薄膜トランジスタ
US4908678A (en) 1986-10-08 1990-03-13 Semiconductor Energy Laboratory Co., Ltd. FET with a super lattice channel
US4926226A (en) * 1988-09-06 1990-05-15 General Motors Corporation Magnetic field sensors
GB2223351A (en) * 1988-09-28 1990-04-04 Philips Electronic Associated A method of manufacturing a semiconductor device having waveguide structure
JPH0480713A (ja) * 1990-07-23 1992-03-13 Nippon Telegr & Teleph Corp <Ntt> 超格子光スイッチ
US5081513A (en) 1991-02-28 1992-01-14 Xerox Corporation Electronic device with recovery layer proximate to active layer
US5216262A (en) 1992-03-02 1993-06-01 Raphael Tsu Quantum well structures useful for semiconductor devices
JPH0643482A (ja) 1992-07-24 1994-02-18 Matsushita Electric Ind Co Ltd 空間光変調素子およびその製造方法
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
US5606177A (en) 1993-10-29 1997-02-25 Texas Instruments Incorporated Silicon oxide resonant tunneling diode structure
US5466949A (en) 1994-08-04 1995-11-14 Texas Instruments Incorporated Silicon oxide germanium resonant tunneling
US5627386A (en) 1994-08-11 1997-05-06 The United States Of America As Represented By The Secretary Of The Army Silicon nanostructure light-emitting diode
US5561302A (en) 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5577061A (en) 1994-12-16 1996-11-19 Hughes Aircraft Company Superlattice cladding layers for mid-infrared lasers
FR2734097B1 (fr) 1995-05-12 1997-06-06 Thomson Csf Laser a semiconducteurs
US6326650B1 (en) 1995-08-03 2001-12-04 Jeremy Allam Method of forming a semiconductor structure
US6344271B1 (en) 1998-11-06 2002-02-05 Nanoenergy Corporation Materials and products using nanostructured non-stoichiometric substances
EP0843361A1 (en) 1996-11-15 1998-05-20 Hitachi Europe Limited Memory device
JPH10173177A (ja) * 1996-12-10 1998-06-26 Mitsubishi Electric Corp Ｍｉｓトランジスタの製造方法
WO1998026316A1 (en) 1996-12-13 1998-06-18 Massachusetts Institute Of Technology Tunable microcavity using nonlinear materials in a photonic crystal
US5994164A (en) 1997-03-18 1999-11-30 The Penn State Research Foundation Nanostructure tailoring of material properties using controlled crystallization
US6255150B1 (en) 1997-10-23 2001-07-03 Texas Instruments Incorporated Use of crystalline SiOx barriers for Si-based resonant tunneling diodes
US6376337B1 (en) 1997-11-10 2002-04-23 Nanodynamics, Inc. Epitaxial SiOx barrier/insulation layer
JP3443343B2 (ja) 1997-12-03 2003-09-02 松下電器産業株式会社 半導体装置
JP3547037B2 (ja) 1997-12-04 2004-07-28 株式会社リコー 半導体積層構造及び半導体発光素子
US6608327B1 (en) 1998-02-27 2003-08-19 North Carolina State University Gallium nitride semiconductor structure including laterally offset patterned layers
JP3854731B2 (ja) 1998-03-30 2006-12-06 シャープ株式会社 微細構造の製造方法
US6888175B1 (en) 1998-05-29 2005-05-03 Massachusetts Institute Of Technology Compound semiconductor structure with lattice and polarity matched heteroepitaxial layers
RU2142665C1 (ru) 1998-08-10 1999-12-10 Швейкин Василий Иванович Инжекционный лазер
US6586835B1 (en) 1998-08-31 2003-07-01 Micron Technology, Inc. Compact system module with built-in thermoelectric cooling
JP3442668B2 (ja) * 1998-10-23 2003-09-02 カナレ電気株式会社 量子波干渉層を有した電界効果トランジスタ
JP3592981B2 (ja) 1999-01-14 2004-11-24 松下電器産業株式会社 半導体装置及びその製造方法
KR100683877B1 (ko) 1999-03-04 2007-02-15 니치아 카가쿠 고교 가부시키가이샤 질화물 반도체 레이저소자
GB9905196D0 (en) 1999-03-05 1999-04-28 Fujitsu Telecommunications Eur Aperiodic gratings
US6350993B1 (en) 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6281532B1 (en) 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
US6570898B2 (en) 1999-09-29 2003-05-27 Xerox Corporation Structure and method for index-guided buried heterostructure AlGalnN laser diodes
US6501092B1 (en) 1999-10-25 2002-12-31 Intel Corporation Integrated semiconductor superlattice optical modulator
RU2173003C2 (ru) 1999-11-25 2001-08-27 Септре Электроникс Лимитед Способ образования кремниевой наноструктуры, решетки кремниевых квантовых проводков и основанных на них устройств
DE10025264A1 (de) 2000-05-22 2001-11-29 Max Planck Gesellschaft Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung
US7301199B2 (en) 2000-08-22 2007-11-27 President And Fellows Of Harvard College Nanoscale wires and related devices
US6521549B1 (en) 2000-11-28 2003-02-18 Lsi Logic Corporation Method of reducing silicon oxynitride gate insulator thickness in some transistors of a hybrid integrated circuit to obtain increased differential in gate insulator thickness with other transistors of the hybrid circuit
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6831292B2 (en) 2001-09-21 2004-12-14 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
AU2003222003A1 (en) 2002-03-14 2003-09-29 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US6853014B2 (en) * 2002-10-25 2005-02-08 The University Of Connecticut Optoelectronic circuit employing a heterojunction thyristor device that performs high speed sampling
US7023010B2 (en) 2003-04-21 2006-04-04 Nanodynamics, Inc. Si/C superlattice useful for semiconductor devices
US6897472B2 (en) * 2003-06-26 2005-05-24 Rj Mears, Llc Semiconductor device including MOSFET having band-engineered superlattice
WO2005018005A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice

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