CN101192165A - Master-slave mode multiprocessor system and software version loading method - Google Patents

Master-slave mode multiprocessor system and software version loading method Download PDF

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Publication number
CN101192165A
CN101192165A CNA2006101606194A CN200610160619A CN101192165A CN 101192165 A CN101192165 A CN 101192165A CN A2006101606194 A CNA2006101606194 A CN A2006101606194A CN 200610160619 A CN200610160619 A CN 200610160619A CN 101192165 A CN101192165 A CN 101192165A
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processor
primary processor
interface
version
master
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CN101192165B (en
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王艳华
钟建兔
陈卫红
黄光霞
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ZTE Corp
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ZTE Corp
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Abstract

The present invention discloses a software version loading method and comprises the following procedures that: the first step: a main processor carries out a bootstrap program of a bootstrap memory to initialize the main processor and the relevant peripheral circuit interface; the second procedure: relevant contents are downloaded from a network management version server by the main processor and stored in a program memory of the main processor; the third procedure: the main processor sends reset control signals to one or a plurality of slave processors and a relevant program version needed by each processor is read to a corresponding bootstrap program memory through a bus-mastering switch; the fourth procedure: the main processor and the slave processors respectively start respective function and task; the fifth procedure: the main procedure and the slave procedures establish a master-slave communication relation in order that the main processor monitors and manages the operating condition of the slave processors. In addition, the present invention also provides a software version loading system, reduces the complexity of the circuit and is convenient to load, upgrade, maintain and manage the software version.

Description

Master-slave mode multiprocessor system and software version loading method
Technical field
The present invention relates to the embedded system field of master-slave mode multiprocessor, and especially, relate to a kind of master-slave mode multiprocessor system and software version loading method.
Background technology
In large-scale communication apparatus of modern times, the embedded system on the veneer in equipment even the equipment often need be designed to master-slave mode multiprocessor system, to finish large-scale calculations or control in real time jointly.Master and slave processor can be made up of processor of the same type or the difference in functionality type, and the communication between the master and slave processor can be undertaken by universal asynchronous receiver (UART), Ethernet, peripheral controller interface (PCI) bus or other bus mode.
As shown in Figure 1, in the prior art, main processor system and often all need to overlap independently peripheral storage separately from processor system, these storeies comprise with the lower part: be used for bootstrap memory that bootstrap processor starts, be used to the SDRAM storer storing the program storage of kernel and application program and be used to carry out this kernel and application program.The software version loading method of master and slave processor is: (1) at first is respectively master and slave processor bootstrap memory sintering boot separately by instruments such as burning the sheet device; (2) by bootstrap memory guide respectively start master and slave processor after, come kernel and application program are loaded in separately the program storage by master and slave processor UART interface or Ethernet interface separately; (3) follow master and slave processor and carry out kernel and application program in the program storage separately more respectively, start master and slave processor function and task separately respectively; (4) simultaneously, primary processor and from setting up master-slave communication relation by UART interface, Ethernet interface, pci bus interface or other bus interface between the processor.This shows that primary processor and a kind of principal and subordinate's correspondence is only just arranged from processor after program run is separately got up is independently in the start-up course of master and slave processor fully.And, in software release upgrade, also need to upgrade respectively primary processor and from processor separately bootstrap memory and the software version the program storage.
The shortcoming of the design of correlation technique is: whole principal and subordinate's multicomputer system not only the circuit complexity, device is many, cost is high, and the upgrading of program version and safeguard much also complicatedly, time that is spent and cost are also high, efficient is low.
Summary of the invention
Consider the problems referred to above and make the present invention that for this reason, fundamental purpose of the present invention is to provide a kind of master-slave mode multiprocessor system and software version loading method.
To achieve these goals, according to the first embodiment of the present invention, provide a kind of master-slave mode multiprocessor system.
This system comprises: primary processor has bootstrap memory, program storage, SDRAM storer by its external bus; One or more from processor, one or more each from processor all have guiding and program storage, SDRAM storer by its external bus; And bus-controlled switching, be used for the external bus of primary processor is connected to each guiding and program storage from processor; Wherein, primary processor and one or more from connecting by communication interface circuit between the processor.
In this system, primary processor can send reseting controling signal from processor to one or more.In addition, communication interface circuit comprises UART interface, Ethernet interface, pci bus interface and other bus interface.
To achieve these goals, according to a second embodiment of the present invention, provide a kind of software version loading method, this method has adopted the master-slave mode multiprocessor system of first embodiment of the invention.
This method may further comprise the steps: first step, primary processor are carried out the boot of its bootstrap memory, with initialization primary processor and related peripheral circuit interface; Second step, primary processor is downloaded related content from the webmaster version server, and is kept in the program storage of primary processor; Third step, primary processor is by sending reseting controling signal to one or more from processor, and relative program version each processor is required by bus-controlled switching writes corresponding guiding and program storage; The 4th step, primary processor and start separately every function and task respectively from processor; And the 5th step, primary processor and set up the master-slave communication relation from processor is so that main processor monitors and management are from the running status of processor.
Wherein, in second step, the related content that primary processor is downloaded comprises: kernel that primary processor uses and application version, the boot version, kernel and the application version that use from processor.
In addition, third step may further comprise the steps: steps A, and primary processor sends reseting controling signal to one or more from processor, so that one or morely be in reset mode from processor; Step B, primary processor is opened bus-controlled switching, so that guiding and program storage from processor are read and write control; Step C, primary processor writes corresponding guiding and program storage with each from processor required boot version, kernel and application version; Step D, primary processor stop to close bus-controlled switching to from the resetting of processor, to close primary processor to from the guiding of processor and the read-write control of program storage.
The 4th step may further comprise the steps: steps A: primary processor operation kernel and application version start its every function and task; And step B: carry out boot separately the bootstrap memory respectively from processor, and operation kernel and application version, start separately function and task.
In addition, in second step, primary processor is downloaded related content by the related peripheral interface, and wherein, the related peripheral interface comprises UART interface and Ethernet interface.
In the 5th step, primary processor and from setting up master-slave communication relation by UART interface, Ethernet interface, pci bus interface or other bus interface between the processor.
By technique scheme, the present invention has reduced the complexity of circuit, and has made things convenient for loading, upgrading and the maintenance management of software version.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the system chart of principal and subordinate processor in the prior art;
Fig. 2 is the system chart according to the principal and subordinate processor of first embodiment of the invention;
Fig. 3 is the block diagram according to the particular instance of the system of the principal and subordinate processor of first embodiment of the invention;
Fig. 4 is the process flow diagram according to the software version loading method of second embodiment of the invention; And
Fig. 5 is the detailed process process flow diagram according to the software version loading method of second embodiment of the invention.
Embodiment
Describe the present invention below with reference to the accompanying drawings in detail.
First embodiment
At first the first embodiment of the present invention is described with reference to Fig. 2 and Fig. 3.Fig. 2 is the block diagram according to the master-slave mode multiprocessor system of first embodiment of the invention, and Fig. 3 is the block diagram of master-slave mode multiprocessor system that adopts the network processing unit APP320E of PowerPC MPC875 microprocessor and Agere company
As shown in Figure 2, master-slave mode multiprocessor system according to first embodiment of the invention comprises: primary processor 202 has bootstrap memory (BOOT storer) 204, program storage (PROGRAM storer) 206, SDRAM storer 208 by its external bus; One or more from processor 210, one or more each from processor 210 all have guiding and program storage (that is BOOT﹠amp, by its external bus; The PROGRAM storer, the guiding and the two-in-one storer of program) 212, SDRAM storer 214; And bus-controlled switching 216, be used for the external bus of primary processor 202 is connected to guiding and program storage 212; Wherein, primary processor 202 and one or morely connect by communication interface circuit between the processor 210.
In this system, primary processor 202 sends reseting controling signal to one or more from processor 210.In addition, communication interface circuit comprises UART interface, Ethernet interface, pci bus interface and other bus interface.
Adopting the system of the PowerPC MPC875 microprocessor of Freescale company with primary processor is example.As shown in Figure 3, primary processor 301 connects Boot Flash storer 303, the SDRAM storer 304 of 16M byte and the Program Flash storer 305 of 4M byte of a 512K byte by its external bus 302; From processor 306 is the built-in ARM microprocessor of the network processing unit APP320E of Agere company, and it connects the Boot﹠amp of a 16M byte by its external bus 307; The DDR2 SDRAM storer 309 of Program Flash storer 308 and 32M byte; Primary processor 301 is connected to from the Boot﹠amp of processor 306 by a cover bus switch 310; On the Program Flash storer 308, can be for downloading from processor 306 or upgrading refresh routine version; In addition, primary processor 301 is controlled from the reset mode of processor 306 by reseting controling signal 311, primary processor 301 and from communicating by Ethernet interface 312 between the processor 306.
Second embodiment
With reference to Fig. 4 and Fig. 5 the second embodiment of the present invention is described below.Fig. 4 is the process flow diagram according to the software version loading method of second embodiment of the invention, and Fig. 5 is the process flow diagram according to the detailed process of the software version loading method of second embodiment of the invention.
As shown in Figure 4, the software version loading method according to second embodiment of the invention may further comprise the steps: step S402, primary processor carry out the boot of its bootstrap memory, with initialization primary processor and related peripheral circuit interface; Step S404, primary processor is downloaded related content from the webmaster version server, and is kept in the program storage of primary processor; Step S406, primary processor is by sending reseting controling signal to one or more from processor, and relative program version each processor is required by bus-controlled switching writes corresponding guiding and program storage; Step S408, primary processor and start separately every function and task respectively from processor; And step S410, primary processor and set up master-slave communication relation from processor is so that main processor monitors and management are from the running status of processor.
Wherein, in step S404, the related content that primary processor is downloaded comprises: kernel that primary processor uses and application version, the boot version, kernel and the application version that use from processor.
In addition, step S406 may further comprise the steps: steps A, and primary processor sends reseting controling signal to one or more from processor, so that one or morely be in reset mode from processor; Step B, primary processor is opened bus-controlled switching, so that guiding and program storage from processor are read and write control; Step C, primary processor writes corresponding guiding and program storage with each from processor required boot version, kernel and application version; Step D, primary processor stop to close bus-controlled switching to from the resetting of processor, to close primary processor to from the guiding of processor and the read-write control of program storage.
In addition, step S408 may further comprise the steps: steps A: primary processor operation kernel and application version start its every function and task; And step B: carry out boot separately the bootstrap memory respectively from processor, and operation kernel and application version, start separately function and task.
In addition, in step S404, primary processor is downloaded related content by the related peripheral interface, and wherein, the related peripheral interface comprises UART interface and Ethernet interface.
In step S410, primary processor and from setting up master-slave communication relation by UART interface, Ethernet interface, pci bus interface or other bus interface between the processor.
The more specifically step of said method specifically describes as follows as shown in Figure 5:
Step 501, flow process begins.
Step 502, the primary processor electrifying startup is carried out the boot of its Boot storer, and initialization primary processor itself and related peripheral interface are as UART interface and Ethernet interface.
Step 503, need do you judge that master and slave processor load or updating software release is denied? when if master and slave processor starts separately Boot program version and kernel and application version has all existed and the renewal of need not upgrading, then skip to execution in step 508, master and slave processor is Bootstrap Commissioning Program and kernel and application program separately, start separately function and task, and the correspondence of setting up between the master and slave processor gets final product; If master and slave processor needs updating software release, then execution in step 504.
Step 504, primary processor is by its UART interface and Ethernet interface, from the webmaster version server download the used kernel of primary processor and application version, from processor used Boot boot version and kernel and application version, all be saved in the Program storer of primary processor.
Step 505, primary processor allows each be in reset mode from processor by reseting controling signal.
Step 506, primary processor are opened bus-controlled switching simultaneously, make primary processor can read and write Boot and the Program two-in-one storer of control from processor; Primary processor writes each corresponding Boot and the two-in-one storer of Program from the required Boot boot version of processor and kernel and application version.
Step 507, primary processor stop to close bus-controlled switching simultaneously to from the resetting of processor, and close primary processor to the read-write control from the Boot and the two-in-one storer of Program of processor.
Step 508, primary processor operation kernel and application version start its every function and task.
Step 509, each carries out Boot boot the Boot storer separately from processor, then moves kernel and application version, starts separately function and task.
Step 510, primary processor and from setting up master-slave communication relation by UART interface, Ethernet interface, pci bus interface or other bus interface between the processor, the running status from processor can be monitored and manage to primary processor constantly.
Comprehensive first and second embodiment, the software version load step of the embedded system of master-slave mode multiprocessor wherein can be to carry out when master and slave processor starts first, also can be to carry out when the normal upgrading update software version in service of master and slave processor.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (9)

1. a master-slave mode multiprocessor system is characterized in that, comprising:
Primary processor has bootstrap memory, program storage, SDRAM storer by its external bus;
One or more from processor, described one or more each from processor all have guiding and program storage, SDRAM storer by its external bus; And
Bus-controlled switching is used for the external bus of described primary processor is connected to described guiding and program storage;
Wherein, described primary processor and described one or more from connecting by communication interface circuit between the processor.
2. master-slave mode multiprocessor system according to claim 1 is characterized in that, described primary processor can be to described one or more from processor transmission reseting controling signal.
3. master-slave mode multiprocessor system according to claim 1 is characterized in that, described communication interface circuit comprises UART interface, Ethernet interface, pci bus interface and other bus interface.
4. a software version loading method uses according to each described master-slave mode multiprocessor system in the claim 1 to 3, it is characterized in that, may further comprise the steps:
First step, primary processor are carried out the boot of its bootstrap memory, with initialization primary processor and related peripheral circuit interface;
Second step, described primary processor is downloaded related content from the webmaster version server, and is kept in the program storage of described primary processor;
Third step, described primary processor is by sending reseting controling signal to one or more from processor, and relative program version each processor is required by bus-controlled switching writes corresponding guiding and program storage;
The 4th step, described primary processor and describedly start separately every function and task respectively from processor; And
The 5th step, described primary processor and describedly set up master-slave communication relation from processor is so that described main processor monitors and the described running status from processor of management.
5. software version loading method according to claim 4, it is characterized in that, in described second step, the described related content that described primary processor is downloaded comprises: kernel that described primary processor uses and application version, described boot version, kernel and the application version that uses from processor.
6. software version loading method according to claim 5 is characterized in that, described third step may further comprise the steps:
Steps A, described primary processor sends reseting controling signal to one or more from processor, so that describedly one or morely be in reset mode from processor;
Step B, described primary processor is opened bus-controlled switching, so that described guiding and program storage from processor read and write control;
Step C, described primary processor writes corresponding guiding and program storage with each from processor required boot version, kernel and application version;
Step D, described primary processor stop to close described bus-controlled switching to described from the resetting of processor, with close described primary processor to described from the described guiding of processor and the read-write control of program storage.
7. software version loading method according to claim 5 is characterized in that, described the 4th step may further comprise the steps:
Steps A: described primary processor operation kernel and application version start its every function and task; And
Step B: describedly carry out boot separately the bootstrap memory respectively from processor, and operation kernel and application version, start separately function and task.
8. software version loading method according to claim 4, it is characterized in that in described second step, described primary processor is downloaded described related content by described related peripheral interface, wherein, described related peripheral interface comprises UART interface and Ethernet interface.
9. software version loading method according to claim 4, it is characterized in that, in described the 5th step, described primary processor and described from setting up the master-slave communication relation by UART interface, Ethernet interface, pci bus interface or other bus interface between the processor.
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