CN101217280B - A successive approximation A/D converter adopting switched-OPAMP - Google Patents

Abstract

The invention relates to a successive approximation analog-to-digital converter adopting switched-opamp and belongs to the analog circuit field. The device consists of a digital-to-analog converter, a comparator, a bumper and a logical control part; wherein, the bumper and the digital-to-analog converter are connected with the two ends of the comparator respectively; the two inputting of the comparator are connected with each other by a switch and the output end is connected with the inputting of the logical control unit which outputs ten digits to be connected with the inputting of the digital-to-analog converter; the input end of the digital-to-analog converter is connected with an input signals (VIN), a reference level (VREF) and a ground potential(GND). The bumper adopts the switched-opamp and the switched-opamp is formed by eight MOS pipes; wherein, the M1, M2, M3 and M4 are NMOS pipes and M5, M6, M7 and M8 are PMOS pipes. The invention adopts the switched-opamp and reduces the whole power consumption of the analog-to-digital converter by reasonable sequential control.

Description

Adopt the gradually-appoximant analog-digital converter of switched-OPAMP

Technical field

The invention belongs to the analog circuit field, particularly adopt the gradually-appoximant analog-digital converter of switched-OPAMP.

Background technology

The application of gradually-appoximant analog-digital converter (Successive Approximation Analog Digital Converter, be called for short successive approximation analog to digital C) very extensively.The main advantage of successive approximation analog to digital C is can realize very low power consumption under the moderate situation of precision and speed, this advantage is fit to the application of portable set and Medical Devices very much, and the successive approximation analog to digital C-structure is simple, and area is little, can with the digital technology compatibility, good integrated level is arranged.Can satisfy the needs of SoC (System On Chip) like this.

Existing successive approximation analog to digital C-structure as shown in Figure 1, mainly by DAC (digital to analog converter), comparator, buffer, and logic control element is formed.The annexation of each device is: buffer and digital to analog converter are connected the two ends of comparator respectively, two inputs of comparator link to each other by a switch, its output connects the input of logic control element, the input of 10 bit data linking number weighted-voltage D/A converters is exported in logic control, the input termination input signal VIN of digital to analog converter, reference level VREF, ground potential GND.

The transfer process of this successive approximation analog to digital C roughly was divided into for three steps: the first step, DAC electric capacity is sampled input voltage.In second step, DAC produces needs voltage relatively, delivers to the input of comparator.In the 3rd step, the result that comparator will compare outputs to logic control element, and the variation of the input voltage of logic control element control DAC setting up the voltage that compares next time, and is exported the result.Wherein comparator is the core of design, also is simultaneously the major part that consumes power consumption.The input of comparator need provide initial level, provides by buffer.The buffer of traditional structure relies on the input of amplifier and output short circuit to realize, as shown in Figure 2, formed by metal-oxide-semiconductor M1～M5, its annexation is: the source electrode of NMOS pipe M1 connects earth potential, grid is connected and fixed level VB, and drain electrode connects the M2 of NMOS pipe, the drain electrode of M3, the grid of M2 connects input signal, and grid and the drain electrode of M3 are connected to output.The drain electrode of M2 connects PMOS pipe M4, the grid of M5 and the drain electrode of M5, and the drain electrode of M4 connects the drain electrode of M2, and M4, the source electrode of M5 connect on the supply voltage VDD, and the substrate of NMOS pipe connects earth potential, and the substrate of PMOS pipe connects on the supply voltage VDD.Realize that easily main shortcoming is that power consumption is too big though this structure is simple, this is the problem that need at first solve in low power dissipation design.

Summary of the invention

The objective of the invention is to propose a kind of gradually-appoximant analog-digital converter that adopts switched-OPAMP for overcoming the deficiency of prior art, the present invention has overcome the excessive shortcoming of buffer power consumption in the existing gradually-appoximant analog-digital converter, utilizes switched-OPAMP to reduce power consumption.

The present invention proposes a kind of gradually-appoximant analog-digital converter that adopts switched-OPAMP, and this transducer comprises: digital to analog converter, comparator, buffer and logic control element; The annexation of each device is: buffer and digital to analog converter are connected the two ends of comparator respectively, two inputs of comparator link to each other by a switch, its output connects the input of logic control element, the input of 10 bit data linking number weighted-voltage D/A converters is exported in logic control, the input termination input signal VIN of digital to analog converter, reference level VREF, ground potential GND; It is characterized in that described buffer adopts switched-OPAMP, this switched-OPAMP is made up of 8 metal-oxide-semiconductors, M1 wherein, and M2, M3, M4 are the NMOS pipe, M5, M6, M7, M8 are that PMOS manages; The annexation of each metal-oxide-semiconductor is: the source ground of NMOS pipe M1, grid links to each other with the fixed level IC of outside, drain electrode is connected with the source electrode of M2, the grid of M2 connects the SWITCH signal, the source electrode of drain electrode and M3 and M4 is connected in node D2, the grid of M4 connects input signal VIN, the drain electrode of M4 and the grid of M5 and drain electrode are connected in node D1, the grid of M3 and drain electrode are connected to become output VOUT, the source electrode of PMOS pipe M5 is connected to supply voltage VDD, the grid connected node D1 of M6, source electrode is connected to supply voltage VDD, and output VOUT is received in drain electrode, M7, the grid connection control signal SWITCH of M8, M7, the M8 drain electrode connects supply voltage VDD, and the source electrode of M7 is received on the node D1, and the source electrode of M8 is connected on the node D2; The substrate ground connection of described each NMOS, the substrate of each PMOS is received on the supply voltage VDD.

Characteristics of the present invention and technique effect:

The present invention adopts switched-OPAMP as gradually-appoximant analog-digital converter, and its characteristics are that the operating state of circuit is controlled by signal SWITCH, and when " SWITCH=1 " circuit operate as normal, when the shutoff of " SWITCH=0 " circuit, circuit does not consume power consumption.

The present invention has reduced the overall power of analog to digital converter effectively by suitable sequencing control, for the successive approximation analog to digital C of a 10bit, adopts switched-OPAMP the power consumption of buffer can be reduced to original 4/14.

Description of drawings

Fig. 1 is a successive approximation analog to digital C overall structure schematic diagram.

The structural representation of existing buffer among Fig. 2 Fig. 1.

The buffer structure schematic diagram that Fig. 3 employing switched-OPAMP of the present invention structure realizes.

Fig. 4 is a working timing figure of the present invention.

Embodiment

The gradually-appoximant analog-digital converter of the employing switched-OPAMP that the present invention proposes is described with reference to the accompanying drawings as follows:

The gradually-appoximant analog-digital converter of the employing switched-OPAMP that the present invention proposes as shown in Figure 1, this transducer comprises: digital to analog converter, comparator, buffer and logic control element; The annexation of each device is: buffer and digital to analog converter are connected the two ends of comparator respectively, two inputs of comparator link to each other by a switch, its output connects the input of logic control element, the input of 10 bit data linking number weighted-voltage D/A converters is exported in logic control, the input termination input signal VIN of digital to analog converter, reference level VREF, ground potential GND.

Buffer of the present invention adopts switched-OPAMP, its structure as shown in Figure 3, this switched-OPAMP is made up of 8 metal-oxide-semiconductors, M1 wherein, M2, M3, M4 are the NMOS pipe, M5, M6, M7, M8 are that PMOS manages; The annexation of each metal-oxide-semiconductor is: the annexation of each metal-oxide-semiconductor is: the source ground of NMOS pipe M1, grid links to each other with the fixed level IC of outside, drain electrode is connected with the source electrode of M2, the grid of M2 connects the SWITCH signal, the source electrode of drain electrode and M3 and M4 is connected in node D2, the grid of M4 connects input signal VIN, the drain electrode of M4 and the grid of M5 and drain electrode are connected in node D1, the grid of M3 and drain electrode are connected to become output VOUT, the source electrode of PMOS pipe M5 is connected to supply voltage VDD, the grid connected node D1 of M6, source electrode is connected to supply voltage VDD, and output VOUT is received in drain electrode, M7, the grid connection control signal SWITCH of M8, M7, the M8 drain electrode connects supply voltage VDD, and the source electrode of M7 is received on the node D1, and the source electrode of M8 is connected on the node D2; M7, the effect of M8 is with D1, the D2 current potential is received on the high potential, prevents that influence of leakage current from arriving output.The substrate ground connection of NMOS, the substrate of PMOS is received on the supply voltage VDD.

Operation principle of the present invention is described as follows in conjunction with Fig. 4: for work schedule such as Fig. 4 of the successive approximation analog to digital C of a 10bit of the present invention, preceding four cycles are that DAC samples to input signal, the common mode electrical level that buffer provides comparator to begin, next ten cycles are that input signal and a series of reference level are compared, with the process of result's output.

As can be seen from Figure 4, beginning four cycles is processes that DAC samples to input signal, and ten cycles of back are processes that ADC compares and judges.The 5th cycle compares input signal VIN and reference level VREF/2 (being produced by DAC), if $\mathrm{VIN}>\frac{\mathrm{<figure-callout\; id="2"\; label="VREF"\; filenames="S200810055878XE00021.png"\; state="\{\{state\}\}">VREF</figure-callout>}}{2}$ , comparator is given the logic control part with comparative result, exports highest order data " 1 " simultaneously, and the 6th cycle, the input signal that DAC is partly controlled in logic control produces reference voltage $\frac{\mathrm{VREF}}{}$ $\frac{}{2}+\frac{\mathrm{<figure-callout\; id="4"\; label="VREF"\; filenames="S200810055878XE00021.png"\; state="\{\{state\}\}">VREF</figure-callout>}}{4}=\frac{3\mathrm{<figure-callout\; id="4"\; label="VREF"\; filenames="S200810055878XE00021.png"\; state="\{\{state\}\}">VREF</figure-callout>}}{4}$ 。If $\mathrm{VIN}<\frac{\mathrm{<figure-callout\; id="2"\; label="VREF"\; filenames="S200810055878XE00021.png"\; state="\{\{state\}\}">VREF</figure-callout>}}{2}$ , comparator is given the logic control part with comparative result, exports highest order data " 0 " simultaneously, and the 6th cycle, the input signal that DAC is partly controlled in logic control produces reference voltage $\frac{\mathrm{VREF}}{2}-\frac{\mathrm{<figure-callout\; id="4"\; label="VREF"\; filenames="S200810055878XE00021.png"\; state="\{\{state\}\}">VREF</figure-callout>}}{4}=\frac{\mathrm{<figure-callout\; id="4"\; label="VREF"\; filenames="S200810055878XE00021.png"\; state="\{\{state\}\}">VREF</figure-callout>}}{4}$ 。The rest may be inferred, till obtaining the lowest order result.

Traditional buffer is in running order always in whole process, so just always at consumed energy.If can when not needing buffer, it be turn-offed, just can save unnecessary energy, thereby reduce power consumption.Based on this thought, the present invention samples to input signal at preceding four cycle DAC, control signal " SWITCH=1 ", buffer work, from the 5th cycle be the process that compares to finishing, at this moment because common mode electrical level and input signal have been stored in above the electric capacity, so the present invention does not just need buffer that common mode electrical level is provided yet, control signal " SWITCH=0 ", buffer turn-offs, ten the cycle internal inner rings in back are idle like this, also just do not consume power consumption.If the power consumption of original buffer is Pd, be reduced to former through the power consumption of improving posterior bumper

Pd * 4/14 of coming, very meaningful for the reduction of overall power.

Claims (1)

1. gradually-appoximant analog-digital converter that adopts switched-OPAMP, this transducer comprises: digital to analog converter, comparator, buffer and logic control element; Wherein, buffer and digital to analog converter are connected the two ends of comparator respectively, two inputs of comparator link to each other by a switch, its output connects the input of logic control element, the input of 10 bit data linking number weighted-voltage D/A converters is exported in logic control, the input termination input signal (VIN) of digital to analog converter, reference level (VREF), earth potential (GND); It is characterized in that described buffer adopts switched-OPAMP, this switched-OPAMP is made up of 8 metal-oxide-semiconductors, M1 wherein, and M2, M3, M4 are the NMOS pipe, M5, M6, M7, M8 are that PMOS manages; The annexation of each metal-oxide-semiconductor is: the source ground of NMOS pipe M1, grid links to each other with the fixed level (IC) of outside, drain electrode is connected with the source electrode of M2, the grid of M2 connects (SWITCH) signal, the source electrode of drain electrode and M3 and M4 is connected in node (D2), the grid of M4 connects input signal (VIN), the drain electrode of M4 and the grid of M5 and drain electrode are connected in node (D1), the grid of M3 and drain electrode are connected to become output (VOUT), the source electrode of PMOS pipe M5 is connected to supply voltage (VDD), the grid connected node (D1) of M6, source electrode is connected to supply voltage (VDD), and output (VOUT) is received in drain electrode, M7, the grid connection control signal (SWITCH) of M8, M7, the M8 drain electrode connects supply voltage (VDD), and the source electrode of M7 is received on the node (D1), and the source electrode of M8 is connected on the node (D2); The substrate ground connection of described each NMOS, the substrate of each PMOS are received on the supply voltage (VDD).

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