CN101242168B - A realization method and device for FIR digital filter direct-connection - Google Patents

Abstract

A FIR digital filer direct accomplishing method and an accomplishing device are provided, belonging to the filed of digital signal processing, comprising the following steps of: initiating the signal, and obtaining different time lag of input signal; converting fixed coefficient product, converting the product of input signal time lag and fixed filter coefficient to co-product or simple product; decomposing the co-product without similar block according to co-product decomposition rule; adding the adjacent two similar co-products according to intermediate product combination rule; adding adjacent two simple products according to intermediate product combination rule, repeating the steps of product decomposition, product combination and simple product combination and accomplishing weighing summation of the filter; obtaining the final output of the filter by regulating gain of the final simple product according to precision and gain requirement. The method and accomplishing device take full advantage of the similar and the same character of the intermediate result (intermediate product), and save quantity and bit wide of the adder for weighing summation operation, and save combined logical resource and register resource in hardware accomplishment.

Description

Direct type implementation method of a kind of Finite Impulse Response filter and implement device

Technical field

The invention belongs to digital signal processing technique field, specially refer to direct type implementation method and the implement device of a kind of Finite Impulse Response filter in programmable logic device, digital signal processor and application-specific integrated circuit (ASIC).

Background technology

In recent years, along with the expansion and the raising of communication and signal processing demand, FIR (Finite Impulse Response) digital filter more and more has been subjected to extensive concern.Finite Impulse Response filter is widely used in audio-video signal processing and multiple occasions such as transmission, base band molding filtration, mirror image filtering and matched filtering.For example in China Digital TV terrestrial transmission national standard, Square-root Raised Cosine FIR filter roll-off coefficient requirement to molding filtration is 0.05, and its transition band is very narrow, and the availability of frequency spectrum is very high, but filter order is very high for hardware is realized, the hardware implementation complexity is very high.Therefore the hard-wired optimization of Finite Impulse Response filter is a very real problem.Finite Impulse Response filter can determine that its system function Z-transformation can be expressed as by system function is unique:

$H\left(z\right)=\underset{n=0}{\overset{N}{\mathrm{\Σ}}}h\left[n\right]\·z^{-n},---\left(1\right)$

H[n wherein] be the filter finite impulse response, i.e. the coefficient of Finite Impulse Response filter.Then the filter input/output relation is

$y\left[n\right]=x\left[n\right]*h\left[n\right]=\underset{m=0}{\overset{N}{\mathrm{\Σ}}}h\left[m\right]\·x[n-m],---\left(2\right)$

Wherein * represents linear convolution, x[n] be input signal, y[n] be output signal.

According to prior art, the basic implementation structure of Finite Impulse Response filter has direct type and transposition type, respectively as illustrated in fig. 1 and 2.Because multiplier resources is limited among FPGA (programmable logic device), DSP (digital signal processor) and the ASIC (application-specific integrated circuit (ASIC)), for the Finite Impulse Response filter of fixed coefficient, the fixed coefficient multiplication is converted to addition usually and realizes.Filter function shown in the formula (2) can be understood as input signal different delayed time x[n-m] weighting h[m] x[n-m] carry out summation operation, therefore hard-wired optimization is exactly optimization to the weighted sum computing to Finite Impulse Response filter.Wherein the weighting of input signal time-delay is exactly the multiplying of input signal time-delay and fixed filters coefficient.Forefathers have carried out a large amount of optimization work.One, propose with the canonical signed number (Canonical Signed-Digital CSD) realizes the fixed coefficient multiplication, promptly by the fixed filters coefficient is expressed as the CSD form,

$h\left[m\right]=\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{a}_{i,m}\×2^i,$ a _i，m∈{0，1，-1}，m∈{0，1，2......N}。(3)

Thus multiplying is converted into displacement and add operation, saved hardware and realized required multiplier resources, and number of adders also is optimized.Its two, realize at above-mentioned CSD utilizing symmetry to be optimized on the basis of fixed coefficient multiplication.Linear phase filter has the symmetry of coefficient, can utilize this symmetry when directly type realizes, reduces hard-wired complexity.As seen from the above, after multiplying is converted into displacement and add operation computing, realize that the needed hardware resource of weighted sum computing depends primarily on the bit wide of adder number and adder.

Yet for direct type structure, the phase Sihe identical characteristics between the FIR filter coefficient still are not utilized fully, and this phase Sihe identical characteristics are fully used in transposition type result.For example, h[1]=7, h[2]=14, h[2 as can be known then]=h[1] * 2, h[1] displacement promptly get h[2], and that their CSD decomposes is different fully, so further utilize this displacement identical characteristics can reduce the adder resource.In like manner, utilize the similar characteristic between the filter coefficient also can reduce the adder resource, as h[1]=7, h[2]=119=7 * 16+7=h[1] * 16+h[1].Sum up existing Finite Impulse Response filter implementation structure and implementation method, there are the following problems as can be known:

1.FIR the CSD method of the direct type of digital filter and symmetry method do not make full use of identical with the similar characteristic of coefficient;

2.FIR digital filter transposition type realizes that though utilized the identical similar characteristic of filter coefficient, the carry that causes owing to the delay accumulation computing makes the bit wide of add operation increase rapidly.

Summary of the invention

The technical issues that need to address of the present invention are to optimize the hard-wired resource occupation of Finite Impulse Response filter.Direct type of traditional Finite Impulse Response filter and transposition type implementation method all exist weak points such as need taking a large amount of combination logic resource and register resources.In order to overcome these deficiencies, just need start a kind of new method, it is on the basis of direct type structure to the purpose of this invention is to provide direct type implementation method of a kind of Finite Impulse Response filter and implement device, make full use of the identical and similar characteristic of filter coefficient, the logical resource of optimizing filter takies.

The objective of the invention is to rely on following technical scheme to realize.The direct type implementation method of a kind of Finite Impulse Response filter is characterized in that, operates by following process step: 101, initialization, and obtain the different delayed time of input signal; 102, fixed coefficient product conversion, with the product of input signal time-delay and fixed filters coefficient by the coefficient of known filter be converted to close long-pending or letter long-pending; 103, will not having similar close to amass decomposes by closing the Integral Solution principle; 104, close long-pending the merging similar, by the addition in twos of partial product combination principle; 105, with the long-pending merging of letter, by the addition in twos of partial product combination principle; 106a, be non-NULL, then return step 103 if close long-pending group; If close long-pending group for empty, then enter next step; 106b, if the long-pending group of letter comprises that a plurality of letters are long-pending, then return step 105; If the long-pending group of letter only comprises that single letter is long-pending, then enter next step; 107, according to precision and gain requirement, the long-pending gain of last letter adjusted the final result that obtains the filter weight summation with the position intercepting,

Wherein, described partial product is defined as hx=B[n] * 2 ^m* A, wherein B[n] be the intermediate object program of filter weight summation, comprise the direct product of input signal time-delay and filter coefficient, also comprise the weighted sum of a plurality of input signals time-delays, m is a nonnegative integer, A is an odd number; When A=1, hx is defined as simple partial product, and it is long-pending that described simple partial product abbreviates letter as, and when A ≠ 1, hx is defined as the built-up section product, and described built-up section product abbreviates as and closes long-pendingly, and odd number A is defined as the radix of partial product hx; If two to close long-pending radix A identical, then be referred to as similar close long-pending;

The described Integral Solution principle of closing is: to there not being the long-pending principle of decomposing of similar close, by the canonical signed number CSD weight of closing long-pending middle radix A

Decompose, wherein, described CSD weight Be meant nonzero value number in the CSD expression formula;

Described partial product combination principle is: the bit wide of addition result increases minimum in twos.

Described direct type implementation method close Integral Solution, close long-pending merge and the long-pending merging of letter can multistage use or iteration use.

Closing the Integral Solution principle described in the described direct type implementation method step 103 is: by the CSD weight of closing long-pending middle radix A

To close Integral Solution is two parts, before the CSD expression formula of the corresponding radix A of first

Individual nonzero value is after the CSD expression formula of the corresponding radix A of second portion

Individual nonzero value, described Floor function representation is not more than the maximum integer of input value, and described Ceil function representation is not less than the smallest positive integral of input value.

The embodiment of the invention further provides based on the direct type implement device of the FIR filter that closes Integral Solution principle and partial product combination principle, and described implement device comprises in integrated circuit and programmable logic device as lower module: input tap time delay module, cascade are decomposed and are merged module and output gain adjustment and position interception module.Wherein importing different delayed time that the tap time delay module obtains input signal gives cascade and decomposes and merge module, cascade decomposition merging module obtains filter weight summation final result and gives an output gain adjustment and a position interception module, and the output gain adjustment obtains filter with an interception module according to required precision and gain and finally exports.

Delay unit number and tap number are identical with filter order in the described input tap time delay module, and the output signal bit wide of tap time delay module is identical with the input signal bit wide.

Described cascade is decomposed the merging module and is comprised that one or more levels decomposes the merging module, each grade decompose to merge module and comprises and close the Integral Solution unit, close long-pending union operation unit and the long-pending union operation unit of letter, and the described Integral Solution unit that closes will not have similar close long-pending (being the intermediate object program of filter weight summation) and be assigned to and describedly close long-pending union operation unit and the union operation unit is amassed in described letter according to closing the Integral Solution principle.

The afterbody decomposition merging module that the merging module is decomposed in described cascade obtains filter weight summation final result, and other grade decomposes the merging module and obtain the intermediate object program that filter weight is sued for peace.

Describedly close long-pending union operation unit and the long-pending union operation unit of letter will import letter according to the partial product combination principle long-pending and close and amass addition in twos.

The beneficial effect of technical scheme provided by the invention is: made full use of the phase Sihe identical characteristics between the Finite Impulse Response filter coefficient, save the adder number and the bit wide that realize the weighted sum computing, save combination logic resource and register resources in the hardware realization.

Description of drawings

Fig. 1 is the direct type structural representation that prior art provides;

Fig. 2 is the transposition type structural representation that prior art provides;

Fig. 3 is a direct type implementation method flow chart provided by the invention;

Fig. 4 is a direct type implement device block diagram provided by the invention;

Fig. 5 is that direct type implement device two-stage provided by the invention is decomposed the merging module diagram.

Embodiment

For making purpose of the present invention, technical method and advantage clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.

Two kinds of implementation methods based on the basic implementation structure of Finite Impulse Response filter that Fig. 1 and Fig. 2 are illustrated in the prior art to be adopted are respectively direct type and transposition type implementation method.

And the invention provides a kind of direct type implementation method of the time domain that is used for fixing the coefficient FIR digital filter that is different from prior art, make full use of the identical similar characteristic between the filter coefficient, make the intermediate object program of filter weight summation transform out identical partial product, wherein the intermediate object program of weighted sum comprises the product of input signal time-delay and fixed coefficient filter.Merge identical partial product and can save the adder resource, the merging of optimizing partial product also can further reduce the bit wide of adder.This method with the weighted sum computing of direct type Finite Impulse Response filter with closing Integral Solution, closing long-pending merge and long-pending merging of letter realizes.This method is applicable to that coefficient complicated and fixing Finite Impulse Response filter realization, especially Large N FIR digital filter realize, is applicable to molding filtration or its related system, also is adapted to fixed coefficient weighted sum computing.

Be that example is set forth technical scheme of the present invention with N rank Finite Impulse Response filter below.For the present invention program there being an overall understanding, the input signal of establishing Finite Impulse Response filter is x[n] (bit wide K bit), output signal is y[n], then the expression formula of its direct type realization is:

$y\left[n\right]=x\left[n\right]*h\left[n\right]=\underset{m=0}{\overset{N}{\mathrm{\Σ}}}h\left[m\right]\·x[n-m]---\left(4\right)$

H[m wherein] be the fixed filters coefficient of N exponent number character filter, x[n-m] be the time-delay of input signal.Earlier the filter implementation method that proposes for the present invention is done necessary description and is prepared, comprise partial product, close long-pending, letter is amassed, radix, similar close long-pending, close Integral Solution principle and partial product combination principle.

Partial product is defined as hx=B[n] * 2 ^m* A, wherein B[n] be the intermediate object program of filter weight summation, comprise the direct product of input signal time-delay and filter coefficient, also comprise the weighted sum of a plurality of input signals time-delays, m is a nonnegative integer, A is an odd number.When A=1, hx is defined as simple partial product (it is long-pending to be called for short letter), to B[n] being shifted to obtain hx.When A ≠ 1, hx is built-up section product (abbreviation closes long-pending), can further decompose.Odd number A is defined as the radix of partial product hx, and obviously the long-pending radix of letter is 1, closes long-pending radix for greater than 1 odd number.To sum up, partial product hx can be by 3 parameter decision (H _Max, m, A), H wherein _Max=B _Max* 2 ^m, B _MaxBe B[n] amplitude peak, the highest significant position of decision hx, the least significant bit of m decision hx.If two to close long-pending radix A identical, then be referred to as similarly to close long-pendingly, can merge.

Closing the Integral Solution principle is exactly to there not being the long-pending principle of decomposing of similar close.For reducing number of adders, close long-pending CSD weight by radix A

Decompose,

${\∂}_1=\mathrm{Floor}(\∂/2)$ ${\∂}_2=\mathrm{Ceil}(\∂/2)---\left(5\right)$

Wherein

For the CSD that closes long-pending radix A decomposes nonzero value number in the expression formula, the Ceil function representation is not less than the smallest positive integral of input value, and the Floor function representation is not more than the maximum integer of input value, therefore

For example

The time,

With

The Integral Solution principle of closing that the present invention proposes is a dichotomy: with the CSD weight of radix A be The Integral Solution of closing become two partial products, before wherein the corresponding CSD of first partial product decomposes in the expression formula

Individual nonzero value is after second corresponding CSD of partial product decomposes in the expression formula Individual nonzero value.Adopt the decomposition principle of dichotomy to make to close that Integral Solution obtains that newly to close long-pending radix A value as far as possible little, help obtaining more similar close long-pending, the minimizing number of adders.

The long-pending merging of letter is exactly with the long-pending addition in twos of letter, and closing long-pending the merging is exactly that similar closing amassed addition in twos, and the two is referred to as partial product and merges.For reducing adder output bit wide, definitional part product combination principle is: increase minimum principle according to bit wide and select two partial products to merge, be explained as follows.Choose two similar close long-pending or two letters long-pending, establish its highest and least significant bit and be respectively msb1, lsb1 and msb2, lsb2, H _MaxParameter respectively is H _Max1And H _Max2, the highest and least significant bit of the partial product after the merging is msb3 and lsb3, H _MaxParameter is H _Max3, adder output bit wide added value is when then carrying out the partial product merging

$\mathrm{\&Delta;W}=(\mathrm{msb}3-\mathrm{lsb}3)-(\frac{\mathrm{msb}2-\mathrm{<figure-callout\; id="2"\; label="lsb"\; filenames="H2008101014487E00012.png"\; state="\{\{state\}\}">lsb</figure-callout>}2}{2}+\frac{\mathrm{msbl}-\mathrm{<figure-callout\; id="1"\; label="lsb"\; filenames="H2008101014487E00012.png"\; state="\{\{state\}\}">lsb</figure-callout>}1}{2}),---\left(6\right)$

Wherein msb3, lsb3 can be by H _Max3=H _Max1+ H _Max2Parameter is tried to achieve,

$\mathrm{<figure-callout\; id="3"\; label="msb"\; filenames="H2008101014487E00012.png"\; state="\{\{state\}\}">msb</figure-callout>}3=\left\{\begin{array}{cc}\max (\mathrm{<figure-callout\; id="1"\; label="msb"\; filenames="H2008101014487E00012.png"\; state="\{\{state\}\}">msb</figure-callout>}1,\mathrm{msb}2),& H_{\max 3}\&le;2^{(\max (\mathrm{<figure-callout\; id="1"\; label="msb"\; filenames="H2008101014487E00012.png"\; state="\{\{state\}\}">msb</figure-callout>}1,\mathrm{msb}2)}\\ \max (\mathrm{<figure-callout\; id="1"\; label="msb"\; filenames="H2008101014487E00012.png"\; state="\{\{state\}\}">msb</figure-callout>}1,\mathrm{msb}2)+1,& H_{\max 3}>2^{\max (\mathrm{<figure-callout\; id="1"\; label="msb"\; filenames="H2008101014487E00012.png"\; state="\{\{state\}\}">msb</figure-callout>}1,\mathrm{msb}2)}\end{array}\right.,---\left(7\right)$

lsb3＝min(lsb1，lsb2)。(8)

Concrete operations according to the partial product combination principle are exactly to select bit wide to increase by two minimum partial products in all possible partial product merges to carry out addition in twos.

Definition based on above-mentioned returns specific embodiment, with reference to Fig. 3, represents direct type implementation method flow chart provided by the invention, and the direct type implementation method of time domain that is used for fixing the coefficient FIR digital filter provided by the invention specifically comprises following operating procedure.

Step 101: initialization is former closes long-pending group, the long-pending group of former letter, newly close long-pending group and the long-pending group of new letter for empty, and obtains the different delayed time x[n-m of input signal], m=0 wherein, 1 ..., N.

Step 102: carry out the conversion of fixed coefficient product by the feature of filter coefficient, be about to input signal time-delay x[n-m] and filter coefficient h[m] product hx=h[m] * x[n-m] be converted to close long-pending or letter long-pending, and transformation result sent into respectively formerly closes long-pending group and former letter and amass and organize.Concrete operations are as follows: each filter coefficient is decomposed into h[n]=A * 2 ^m, A is an odd number, m is a nonnegative integer; If h[n]=2 ^m, then be converted to the long-pending hx=x[n of letter] * h[n]=x[n] * 1 * 2 ^m, by (H _Max, m, A)=(x _Max* 2 ^m, m, 1) and decision, x _MaxBe x[n] amplitude peak, its highest and least significant bit is msb=K+m and lsb=m, wherein K is not less than log ₂(x _Max) smallest positive integral; If h[n]=A * 2 ^m, A ≠ 1 then is converted to and closes long-pending hx=x[n] * h[n]=x[n] * A * 2 ^m, by (H _Max, m, A)=(x _Max* 2 ^m, m, A) decision, its highest and least significant bit is msb=K+m and lsb=m.According to above-mentioned conversion operations, with the product of time-delay of N+1 input signal and filter coefficient be converted to close long-pending or letter long-pending, and transformation result sent into respectively formerly closes long-pending group and former letter and amass and organize.

Step 103: according to closing the Integral Solution principle, close in the long-pending group does not no similar the Integral Solution of closing and amass for letter or close long-pending former, decomposition result is sent into former long-pending group and the long-pending group of former letter of closing respectively, wherein said no similar close that closing of product term is long-pending and comprise before closing of obtaining of step long-pending and the decomposition of this step obtains close long-pending.

Step 104: select formerly to close similar in the long-pending group and close the long-pending addition in twos of carrying out according to the partial product combination principle, addition result is sent into and is newly closed long-pending group, formerly closes long-pending also the sending at last of closing that merges in the long-pending group and newly closes long-pending group.

Step 105: select according to the partial product combination principle that letter in the long-pending group of former letter is long-pending carries out addition in twos, addition result is sent into the long-pending group of new letter, the long-pending long-pending group of new letter of also sending at last of letter that merges in the long-pending group of former letter.

Step 106a:, then return step 103 if close long-pending group for non-NULL; If close long-pending group for empty, then enter next step; Step 106b:, then return step 105 if the long-pending group of letter is long-pending for non-single letter; If the long-pending group of letter only comprises that single letter is long-pending, then enter next step;

Step 107:, the long-pending gain of last letter adjusted the final output that obtains filter with the position intercepting according to precision and gain requirement.

With reference to Fig. 4, the implement device block diagram of the direct type implementation method of Finite Impulse Response filter according to claim 1 that expression the present invention proposes.The direct type implementation method of Finite Impulse Response filter that proposes according to the present invention, the present invention further proposes based on the direct type implement device of the Finite Impulse Response filter that closes Integral Solution principle and partial product combination principle, and described implement device comprises in integrated circuit and programmable logic device as lower module: input tap time delay module, cascade are decomposed and are merged module and output gain adjustment and position interception module.Wherein importing different delayed time that the tap time delay module obtains input signal gives cascade and decomposes and merge module, cascade decomposition merging module obtains filter weight summation final result and gives an output gain adjustment and a position interception module, and the output gain adjustment obtains filter with an interception module according to required precision and gain and finally exports.

Delay unit number and tap number are identical with filter order in the described input tap time delay module, and the output signal bit wide of tap time delay module is identical with the input signal bit wide

With reference to Fig. 5, the two-stage that expression the present invention proposes is decomposed and is merged module diagram.Described cascade is decomposed and is merged module and comprise that one or more levels decomposes and merge module, and each grade decomposes and merge module and comprise and close the Integral Solution unit, close long-pending union operation unit and the long-pending union operation unit of letter.

The described Integral Solution unit that closes will not have and similar close long-pending (being the intermediate object program of filter weight summation) and be assigned to and close long-pending union operation unit and the union operation unit is amassed in letter according to closing the Integral Solution principle.

Describedly close long-pending union operation unit and the long-pending union operation unit of letter will import letter according to the partial product combination principle long-pending and close and amass addition in twos.

The afterbody decomposition merging module that the merging module is decomposed in described cascade obtains filter weight summation final result, and other grade decomposes the merging module and obtain the intermediate object program that filter weight is sued for peace.

Direct type implementation method of a kind of Finite Impulse Response filter proposed by the invention and implement device, do following contrast with prior art, three kinds of implementation methods of reference prior art relatively comprise the transposition type, adopt the direct type of CSD decomposition and utilize symmetric direct type.With reference to table 1, represent the logical resource contrast that four kinds of implementation methods realize at FPGA.The Finite Impulse Response filter that wherein is used for comparison is the Nyquist filter, and its exponent number is 68, and rolloff-factor is 0.45, and filter coefficient adopts 15bits to quantize; Being used for logic analysis and comprehensive platform is Quartus II, and the FPGA type of device is an Altera Stratix II series.The combinational logic and the register logical resource that take when FPGA realizes of the direct type that proposes of the present invention is all minimum as can be seen.

Table 1

The Finite Impulse Response filter implementation method	LC combinationals	LC Register
			The transposition type	2778	1990
CSD decomposes direct type	2982	966
			The direct type of symmetry	2220	966
The direct type that the present invention proposes	1812	966

Only being embodied as example with the Finite Impulse Response filter on 68 rank above compares, the exponent number of the Finite Impulse Response filter that needs in the reality may be higher, for example the digital baseband formed filter in Chinese terrestrial DTV standard needs the hundreds of rank, adopts the implementation method of the embodiment of the invention will save more resources so when realizing.Above analysis result shows, direct type method and transposition type that the present invention proposes, and CSD decomposes direct type and compares with the direct type of symmetry, takies in the hardware realization more to have superiority aspect the resource, and this method has excellent generalization values.

As previously mentioned, the core that the direct type of Finite Impulse Response filter realizes is the weighted sum computing, and therefore technical scheme of the present invention can directly apply to the hardware realization of common weighted sum computing in FPGA, DSP or ASIC.

Above specific embodiments of the invention are had been described in detail, but the present invention is not restricted to the foregoing description.

Claims (8)

1. the direct type implementation method of Finite Impulse Response filter is characterized in that, operates by following process step: 101, initialization, and obtain the different delayed time of input signal; 102, fixed coefficient product conversion, with the product of input signal time-delay and fixed filters coefficient by the coefficient of known filter be converted to close long-pending or letter long-pending; 103, will not having similar close to amass decomposes by closing the Integral Solution principle; 104, close long-pending the merging similar, by the addition in twos of partial product combination principle; 105, with the long-pending merging of letter, by the addition in twos of partial product combination principle; 106a, be non-NULL, then return step 103 if close long-pending group; If close long-pending group for empty, then enter next step; 106b, long-pending for non-single letter if group is amassed in letter then returns step 105; If the long-pending group of letter only comprises that single letter is long-pending, then enter next step; 107, according to precision and gain requirement, the long-pending gain of last letter adjusted the final result that obtains the filter weight summation with the position intercepting,

Wherein, described partial product is defined as hx=B[n] * 2 ^m* A, wherein B[n] be the intermediate object program of filter weight summation, comprise the direct product of input signal time-delay and filter coefficient, also comprise the weighted sum of a plurality of input signals time-delays, m is a nonnegative integer, A is an odd number; When A=1, hx is defined as simple partial product, and it is long-pending that described simple partial product abbreviates letter as, and when A ≠ 1, hx is defined as the built-up section product, and described built-up section product abbreviates as and closes long-pendingly, and odd number A is defined as the radix of partial product hx; If two to close long-pending radix A identical, then be referred to as similar close long-pending;

The described Integral Solution principle of closing is: to there not being the long-pending principle of decomposing of similar close, by the canonical signed number CSD weight of closing long-pending middle radix A Decompose, wherein, described CSD weight Be meant nonzero value number in the CSD expression formula;

Described partial product combination principle is: the bit wide of addition result increases minimum in twos.

2. the direct type implementation method of Finite Impulse Response filter according to claim 1 is characterized in that, described direct type implementation method close Integral Solution, close long-pending merge and the long-pending merging of letter can multistage use or iteration use.

3. the direct type implementation method of Finite Impulse Response filter according to claim 1 is characterized in that, the described Integral Solution principle of closing of described step 103 is: by the CSD weight of closing long-pending middle radix A To close Integral Solution is two parts, before the CSD expression formula of the corresponding radix A of first

Individual nonzero value is after the CSD expression formula of the corresponding radix A of second portion

Individual nonzero value, described Floor function representation is not more than the maximum integer of input value, and described Ceil function representation is not less than the smallest positive integral of input value.

4. implement device according to the direct type implementation method of the described Finite Impulse Response filter of claim 1, it is characterized in that, comprise as lower module in the integrated circuit of this device and programmable logic device: input tap time delay module, cascade are decomposed and are merged module, output gain adjustment and position interception module; Wherein importing different delayed time that the tap time delay module obtains input signal gives cascade and decomposes and merge module, cascade decomposition merging module obtains filter weight summation final result and gives an output gain adjustment and a position interception module, and the output gain adjustment obtains filter with an interception module according to required precision and gain and finally exports.

5. implement device according to claim 4 is characterized in that, delay unit number and tap number are identical with filter order in the described input tap time delay module, and the output signal bit wide of tap time delay module is identical with the input signal bit wide.

6. implement device according to claim 4, it is characterized in that, described cascade is decomposed the merging module and is comprised that one or more levels decomposes the merging module, each grade decompose to merge module and comprises and close the Integral Solution unit, close long-pending union operation unit and the long-pending union operation unit of letter, the described Integral Solution unit that closes will not have similar the integration that closes and be fitted on described long-pending union operation unit and the long-pending union operation unit of described letter of closing according to closing the Integral Solution principle.

7. according to claim 4 or 6 described implement devices, it is characterized in that, described cascade is decomposed the afterbody that merges module and is decomposed the merging module, obtains the final result of filter weight summation, and other grade decomposes and merge the intermediate object program that module obtains the filter weight summation.

8. implement device according to claim 6 is characterized in that, the simple long-pending or similar long-pending addition in twos of closing according to the partial product combination principle, will be imported in described long-pending union operation unit or the long-pending union operation unit of letter of closing.

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