CN101242539B - Frame synchronization device and method for T-DMB system receiver - Google Patents
Frame synchronization device and method for T-DMB system receiver Download PDFInfo
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- CN101242539B CN101242539B CN200710037249XA CN200710037249A CN101242539B CN 101242539 B CN101242539 B CN 101242539B CN 200710037249X A CN200710037249X A CN 200710037249XA CN 200710037249 A CN200710037249 A CN 200710037249A CN 101242539 B CN101242539 B CN 101242539B
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Abstract
The present invention provides a frame synchronizer of T-DMB system receiver and its method, the device includes adder 1, selftimer 1, adder 2, selftimer 2. adder 3, a comparator, a sign counter and a decision control state machine, wherein the adders 1, 2, the selftimers 1, 2 are used for receiving input signal and the sending in the adder 3 after dot difference; the adder 3 sends the processing result to the comparator and then sends to the sign counter, the sign counter sends the enumerated data to the decision control state machine and receives the feedback of the decision control state machine. The frame synchronizer processes counting by receiving the signl of the signal width and the difference of threshold, and judging null interval, the method is quick and high effect, only using some control state machines and simple adding unit can realize because of having no filter, the method reduces the spending of the hardware, effectively overcomes time pulse.
Description
Technical field
The present invention relates to the frame-synchronizing device in a kind of T-DMB Standard Digital Television broadcast receiver system; The invention still further relates to T-DMB system receiver frame synchornization method.
Background technology
T-DMB is the T-DMB standard that Korea S releases, and this standard is based on has made on the European standards for digital broadcasting DAB basis that some modifications form, so that transmit the wireless digital TV-set program to handheld devices such as mobile phone, PDA and mobile televisions.
The transmission frame-form of T-DMB digital television standard as shown in Figure 1, each frame is divided into three parts: synchronizing channel (Synchronization Channel), fast information channel in dab receiver (Fast InformationChannel) and main service channel (Main Service Channel).Wherein synchronizing channel is in the beginning part of each frame, accounts for two symbol lengths, plays the effect of receiving terminal frame synchronization.In two symbols of synchronizing channel, first is null symbol, i.e. null symbol, its symbol lengths is defined as Tnull, under four kinds of different transmission modes, Tnull length is also different, (annotates: T=1/fs in the table as table 1, be the systematic sampling cycle, T=1/2048000 second), in this symbol time, transmitting terminal does not send any signal, so the signal that receiving terminal receives in this symbol time is more much lower than normal signal amplitude, can utilize this characteristic to carry out synchronously; Second is PRS (PhaseReference Symbol) symbol, i.e. phase reference symbol, this symbol be both as the phase reference of DQPSK (difference quadrature phase shift keying modulation), and the correlation properties of PRS sequence also can be used for doing initial synchronisation simultaneously.
| Transmission mode | I | II | III | IV |
| Tnull length | 2656T (1297μs) | 664T (324μs) | 345T (168μs) | 1328T (648μs) |
Tnull length under four kinds of transmission modes of table 1
Therefore, in present T-DMB frame synchronizing, roughly be divided into two kinds, a kind of PRS of utilization symbol carries out synchronously, promptly the signal that receives is slided to be correlated with and asks the method for relevant peaks, and this method advantage is to utilize related gain, can effectively resist signal fadeout, raising is detected as power, but amount of calculation is bigger, and consumption of natural resource is also many.And the simple relatively method of another kind is to detect the null symbol, find the border of null symbol by the threshold value of setting, this method need be carried out low-pass filtering to signal usually, waveform after the detection filter then, but the difficult choosing of suitable threshold value will be changed different threshold values under different channel circumstances, and wants to resist the random fading of signal on the other hand, then improve the exponent number of low pass filter again, therefore the storage resources that consumes also becomes big thereupon.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of T-DMB system receiver frame-synchronizing device, and it is reliable and stable, it is high and save resource to be detected as power; For this reason, the present invention also will provide a kind of T-DMB system receiver frame synchornization method.
For solving the problems of the technologies described above, T-DMB system receiver frame-synchronizing device of the present invention comprises: adder one, delayer one, adder two, delayer two, adder three, one comparator, one symbol counter and a judgement control state machine, wherein: through the two-way input data I (i) after tuner and the AD sampling and Q (i) respectively correspondence be input to described delayer one and delayer two and carry out two and clap and delay time, data I (i-2) after obtaining respectively delaying time and Q (i-2), again two-way is imported after data and the time-delay data respectively correspondence be input to adder one and adder two asks poor, obtain two paths of data I ' (i) and Q ' (i), I ' (i)=I (i)-I (i-2), Q ' (i)=Q (i)-Q (i-2), again to I ' (i) and Q ' (i) ask absolute value; Three couples of I ' of described adder (i) and Q ' absolute value summation (i) obtain signal amplitude y (i); Described comparator compares y (i) and preset threshold, and the result after will comparing sends into symbol counter, if y (i) is greater than preset threshold, the value of then symbol counter adds 1, otherwise just subtracts 1; Symbol counter is sent count value into judgement control state machine and the control state machine of accepting a judgement feedback;
Described judgement control state machine judges that the each count value of symbol counter is whether less than the count value of last time, judge if be not less than then continue to repeat, if less than, then judge less than situation whether pass through continuous constant time, if then get first less than point be the maximum of points of symbol counter; Begin to start accumulator from maximum of points the difference of signal amplitude y (i) and preset threshold is added up,, find the minimum point of symbol counter before reaching the exit point condition when accumulated value reaches the exit point condition greater than zero the time; The maximum of points of described symbol counter and the difference between the minimum point and full-length are compared, determine transmission mode; And with the minimum point of symbol counter starting point, i.e. frame head position as next symbol; Repeat above process, correct synchronously if the unanimity as a result that obtains for twice then illustrates, promptly frame head position and transmission mode are correct, otherwise get the maximum of points of symbol counter and the big correct result of the result who once judges conduct of difference of minimum point.
T-DMB system receiver frame synchornization method of the present invention comprises the steps:
I′(i)＝I(i)-I(i-2)，Q′(i)＝Q(i)-Q(i-2)；
Step 2, by asking described two paths of data I ' (i) and Q ' absolute value (i) and represent signal amplitude, promptly y (i)=| I ' (i) |+| Q ' (i) |;
Step 3, startup symbol counter; Step 2 gained y (i) and preset threshold are compared, and greater than preset threshold, the value of then symbol counter adds 1, otherwise just subtracts 1 as if y (i);
Whether the value of the symbol counter of step 4, determining step three gained is less than the value of the symbol counter of last time, judge if be not less than then continue to repeat, if less than, then judge less than situation whether pass through continuous constant time, if then get first less than point be the maximum of points of symbol counter;
Step 5, begin to start accumulator from described maximum of points the difference of y (i) and preset threshold added up, when accumulated value greater than zero the time, then reach the exit point condition, find the minimum point of symbol counter before reaching the exit point condition simultaneously;
Step 6, with the maximum of points of described symbol counter and the difference of minimum point, compare with full-length, determine transmission mode; And the minimum point of symbol counter is the starting point of next symbol;
Step 7, repeating step one be to step 6, if with last time the result consistently then illustrate correctly synchronously, otherwise the result who gets big frame head position of once judging of the difference of the maximum of points of symbol counter and minimum point and transmission mode is as correct result.
The present invention is owing to utilize the symbol of the difference of acknowledge(ment) signal amplitude and setting threshold to count, and then judges the null interval, on average only needs the time with 1.5 frames lock in time, also can not surpass 3 frames the slowlyest; That is to say, under the situation of transmission mode shown in the table 1 two, on average only need the time about 24ms*1.5=36ms just can determine the frame head position.And in the longest transmission mode one of frame length, also only need about 96ms*1.5=144ms, be no more than 288ms the most slowly; And through field test, signal sensitivity 〉=-situation of 100dbm under, be detected as power and can reach reliable more than 99.99%, be the available machine time that unit calculates with the second for general mobile phone, be quite fast and efficiently.On the other hand, on resource consumption and complexity, owing to do not adopt filter, reduced most storage resources, only just can realize, significantly reduce hardware and realized expense, and can overcome the interference of time domain pulse effectively with some control state machine and simple adder unit.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the transmission frame-form schematic diagram of existing T-DMB digital television standard;
Fig. 2 is that the symbol count value changes schematic diagram in the method for the present invention;
Fig. 3 is a frame-synchronizing device structural representation of the present invention;
Fig. 4 is a judgement control state machine control flow chart in the frame-synchronizing device of the present invention.
Embodiment
For the null symbol of synchronizing channel,,, still there is bigger noise by after the channel disturbance though the transmitting terminal signal is 0; Therefore simple threshold settings usually can lose efficacy in detection, and in order to detect the null symbol, the present invention has introduced a symbol counter.Its basic thought is, ask that signal amplitude M and fixed threshold T's is poor, sign bit S to this difference counts, and in the symbol of non-null, S should major part be 1, in the symbol of null, then S is-1, so the variation tendency (its shape can with reference to figure 2) of similar z font will appear in the count value of this symbol counter, as long as determined two breaks that this count value changes, just find the starting point and the end point of null symbol, thereby also just determined the position of frame head.
The synchronizing process of specific implementation of the present invention is as follows:
1, for through two-way input data I (i) and Q (i) after tuner and the AD sampling, carry out the dot interlace difference respectively, that is: I ' (i)=I (i)-I (i-2) and Q ' (i)=Q (i)-Q (i-2).
2, by asking described two paths of data I ' (i) and Q ' absolute value (i) and represent signal amplitude, promptly y (i)=| I ' (i) |+| Q ' (i) |.
Described dot interlace difference is meant, will import data I (i) and Q (i) carry out two clap time-delay obtain I (i-2 and Q (i-2) ask difference to obtain data I more respectively ' (i) and Q ' (i), be mixed in DC component in the signal with elimination.
3, selected threshold value th_val, y (i) value that each step 2 is obtained compares with it, when this selected threshold value is in a suitable scope, can so that except the value of the most y (i) the data during this section of Tnull all greater than this threshold value.Therefore set a symbol counter again, if the y (i) that accepts greater than threshold value th_val, the value of then symbol counter adds 1, otherwise just subtracts 1.The variation tendency of symbol counter such as Fig. 2.
4, find the symbol counter maximum of points, as Fig. 2, a bit before entering the Tnull interval, the symbol counter value can rise to a maximum of points, here in order to determine that this maximum of points is not because other reasonses such as decline cause, and compares in a segment limit.If this point all is maximum in a segment limit, so just determine because the maximum of points that Tnull causes.
5, find exit point and minimum point.Behind the maximizing point, look for exit point again, need to start an accumulator here, Tnull_acc=∑ (y (i)-th_val).This accumulator begins to add up from maximum of points backward, and in the Tnull interval, the value of this accumulator is all born, and when withdrawing from the Tnull interval, the value of y (i) is far longer than th_val, thus accumulator also can get back to very soon on the occasion of.Accumulator get back on the occasion of point, exit point just.Simultaneously, in this section interval, also can find the minimum point (looking for the peaked while) of symbol counter also in the searching of carrying out minimum value.
6, discriminating transmission mode and definite synchronous points.Found minimum point and maximum of points, can obtain the difference between them, the Tnull length that promptly searches compares with it and standard Tnull length (with reference to subordinate list 1), can determine transmission mode.Here stipulated that is judged a scope Tnull_range, the difference between Tnull length that searches and standard Tnull length judges then that less than this judgement scope current search is correct.And minimum point is the end of Tnull and the starting point of next symbol.
7, repeat once above step 1～6, look for a frame head position again and judge a transmission mode as affirmation, the unanimity as a result that finds for twice illustrates that then frame head and transmission mode are accurate, otherwise get Tnull length big once as correct result.
As shown in Figure 3, frame-synchronizing device of the present invention comprises adder one, delayer one, adder two, delayer two, adder three, one comparator, one symbol counter and a judgement control state machine, wherein: the input data are two paths of data I (i) and the Q (i) after front end process tuner and the AD sampling, pass through delayer one respectively, carry out two bat time-delays after two and obtain I (i-2) and Q (i-2), adder one, two ask poor to both respectively again, obtain sequence I ' (i) and Q ' (i), then adder three ask these two sequence absolute values and, obtain y (i) sequence, y (i) and setting threshold th_val are compared by comparator, the symbol that draws is counted, and can obtain wave mode shown in Figure 2.Symbol counter is sent count value into judgement control state machine and the control state machine of accepting a judgement feedback.
Judgement control state machine internal process such as Fig. 4, after synchronizing process began to start, at first the zero clearing symbol counter allowed it restart counting, judged that then each Counter Value is whether less than the count value of last time; If less than situation, then continue to judge, if through all be for continuous n time less than situation (n can select to dispose, and can be made as constant here), then think first less than point be exactly maximum of points.At this moment start accumulator, to (y (i)-th_val) add up, when the accumulated value of accumulator greater than zero the time, then think the exit point condition that reaches, a subsynchronous process finishes the difference between calculated minimum point and the maximum of points, determining transfer mode.At last, repeat above process as affirmation, through two subsynchronous after, can withdraw from this control state machine.
Claims (3)
1. T-DMB system receiver frame-synchronizing device, it is characterized in that, comprise: adder one, adder two, adder three, delayer one, delayer two, one comparator, one symbol counter and a judgement control state machine, wherein: through the two-way input data I (i) after tuner and the AD sampling and Q (i) respectively correspondence be input to described delayer one and delayer two and carry out two and clap and delay time, data I (i-2) after obtaining respectively delaying time and Q (i-2), again two-way is imported after data and the time-delay data respectively correspondence be input to adder one and adder two asks poor, obtain two paths of data I ' (i) and Q ' (i), I ' (i)=I (i)-I (i-2), Q ' (i)=Q (i)-Q (i-2), again to I ' (i) and Q ' (i) ask absolute value; Three couples of I ' of described adder (i) and Q ' absolute value summation (i) obtain signal amplitude y (i); Described comparator compares y (i) and preset threshold, and the result after will comparing sends into symbol counter counting, if y (i) is greater than preset threshold, the value of then symbol counter adds 1, otherwise just subtracts 1; Described symbol counter is sent count value into described judgement control state machine and the control state machine of accepting a judgement feedback;
Described judgement control state machine judges that the each count value of symbol counter is whether less than the count value of last time, judge if be not less than then continue to repeat, if less than, then judge less than situation whether pass through continuous constant time, if then get first less than point be the maximum of points of symbol counter; Begin to start accumulator from maximum of points the difference of signal amplitude y (i) and preset threshold is added up,, find the minimum point of symbol counter before reaching the exit point condition when accumulated value reaches the exit point condition greater than zero the time; Described symbol counter has been determined maximum of points and minimum point, has just found the starting point and the end point of null symbol, has also just determined the position of frame head; The maximum of points of described symbol counter and the difference between the minimum point and full-length are compared, determine transmission mode, and with the minimum point of the symbol counter starting point as next nul1 symbol; Repeat above process, if the unanimity as a result that obtains for twice then illustrates correct synchronously, be that frame head position and transmission mode are correct, otherwise the result who gets big frame head position of once judging of the difference of the maximum of points of symbol counter and minimum point and transmission mode is as correct result.
2. a T-DMB system receiver frame synchornization method is characterized in that, comprises the steps:
Step 1, for through two-way input data I (i) and Q (i) after tuner and the AD sampling, carry out the dot interlace difference respectively, that is, will import data I (i) and Q (i) and carry out two and clap time-delay and obtain I (i-2) and Q (i-2), and ask respectively again to differ to obtain data I ' (i) and Q ' (i):
I′(i)＝I(i)-I(i-2)，Q′(i)＝Q(i)-Q(i-2)；
Step 2, by asking described two paths of data I ' (i) and Q ' absolute value (i) and represent signal amplitude, promptly y (i)=| I ' (i) |+| Q ' (i) |;
Step 3, startup symbol counter; Step 2 gained y (i) and preset threshold are compared, and greater than preset threshold, the value of then symbol counter adds 1, otherwise just subtracts 1 as if y (i);
Whether the value of the symbol counter of step 4, determining step three gained is less than the value of the symbol counter of last time, judge if be not less than then continue to repeat, if less than, then judge less than situation whether pass through continuous constant time, if then get first less than point be the maximum of points of symbol counter;
Step 5, begin to start accumulator from described maximum of points the difference of y (i) and preset threshold added up, when accumulated value greater than zero the time, then reach the exit point condition, find the minimum point of symbol counter before reaching the exit point condition simultaneously; Described symbol counter has been determined maximum of points and minimum point, has just found the starting point and the end point of null symbol, has also just determined the position of frame head;
Step 6, the maximum of points of described symbol counter and the difference and the full-length of minimum point are compared, determine transmission mode; And the minimum point of symbol counter is the starting point of next null symbol;
Step 7, repeating step one are to step 6, if with consistent then the explanation synchronously correctly of result's last time, be that frame head position and transmission mode are correct, otherwise the result who gets big frame head position of once judging of the difference of the maximum of points of symbol counter and minimum point and transmission mode is as correct result.
3. T-DMB system receiver frame synchornization method according to claim 2, it is characterized in that: in the step 6 when the difference of symbol counter maximum of points and minimum point and the difference between the full-length within the judgement scope of regulation, the difference of then judging the maximum of points that searches and minimum point is for correct.
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| CN105157972B (en) * | 2015-08-31 | 2018-01-05 | 西安交通大学 | A kind of main shaft spacer ring crudy dynamic testing method based on vibration signal |
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| US5646966A (en) * | 1992-06-30 | 1997-07-08 | Sony Corporation | Method and apparatus for detecting synchronizing signals by latching successived count values that represent time between received sync pulses for comparison to a predetermined sync pattern of count values |
| US5956377A (en) * | 1996-05-31 | 1999-09-21 | Vtech Communications, Ltd. | Method and apparatus for synchronizing frames within a continuous stream of digital data |
| CN1564505A (en) * | 2004-04-02 | 2005-01-12 | 清华大学 | Frame synchronous dynamic captive device in orthogonal FDM system |
| CN1719821A (en) * | 2004-07-06 | 2006-01-11 | 三星电子株式会社 | The method for synchronous and the equipment that are used for digital audio frequency/digital multimedia broadcasting receiver |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5646966A (en) * | 1992-06-30 | 1997-07-08 | Sony Corporation | Method and apparatus for detecting synchronizing signals by latching successived count values that represent time between received sync pulses for comparison to a predetermined sync pattern of count values |
| US5956377A (en) * | 1996-05-31 | 1999-09-21 | Vtech Communications, Ltd. | Method and apparatus for synchronizing frames within a continuous stream of digital data |
| CN1564505A (en) * | 2004-04-02 | 2005-01-12 | 清华大学 | Frame synchronous dynamic captive device in orthogonal FDM system |
| CN1719821A (en) * | 2004-07-06 | 2006-01-11 | 三星电子株式会社 | The method for synchronous and the equipment that are used for digital audio frequency/digital multimedia broadcasting receiver |
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