CN101246193B - Method of transferring test trays in a handler - Google Patents
Method of transferring test trays in a handler Download PDFInfo
- Publication number
- CN101246193B CN101246193B CN2007101948092A CN200710194809A CN101246193B CN 101246193 B CN101246193 B CN 101246193B CN 2007101948092 A CN2007101948092 A CN 2007101948092A CN 200710194809 A CN200710194809 A CN 200710194809A CN 101246193 B CN101246193 B CN 101246193B
- Authority
- CN
- China
- Prior art keywords
- room
- test
- pallets
- test pallets
- pallet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2865—Holding devices, e.g. chucks; Handlers or transport devices
- G01R31/2867—Handlers or transport devices, e.g. loaders, carriers, trays
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0433—Sockets for IC's or transistors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2893—Handling, conveying or loading, e.g. belts, boats, vacuum fingers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
The invention discloses a method for transferring test trays in a handler including a second chamber having two test sites arranged in parallel, a first chamber provided over the second chamber, and a third chamber provided under the second chamber, the method including steps of (a) enabling test trays to wait at a waiting location, (b) loading packaged chips onto the test trays, (c) rotating the test trays to be in the upright position, (d) moving upwards the test trays into the first chamber, (e) heating or cooling the test trays while moving the test trays in the first chamber, (f) moving the test trays from the first chamber into the second chamber, (g) moving the test trays toward test boards, (h) moving downwards the test trays from the second chamber into the third chamber while moving forwards the test trays, (i) moving the test trays from the third chamber to the waiting location, (j) rotating the test trays to be in the horizontal position.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
The right of priority of korean patent application 10-2006-0115697 number that the application requires to submit on November 22nd, 2006,10-2006-0115699 number, 10-2006-0115700 and 10-2006-0115701 number, its disclosure integral body is hereby expressly incorporated by reference.
Technical field
The present invention relates to a kind of method that is used for transmitting at processor test pallet, this processor is used to handle packaged chip so that carry out electrical testing.
Background technology
When packaging technology finished, processor made packaged chip stand a series of environment, electricity and reliability testing.According to the consumer and the purposes of packaging, these tests are different on type and specification.These tests can carried out on all packaging parts or carry out on selected sample in bulk mode.
Processor is put into packaged chip in the test pallet and with test pallet and is supplied to tester.Tester comprises the test board with a plurality of slots, is used for carrying out on packaged chip electrical testing.Packaged chip is inserted in the slot of test board so that carry out electrical testing.Processor is put into packaged chip in the test pallet (that is, anchor clamps), and the packaged chip that will be contained in the test pallet is inserted in the slot of test board.Processor is classified to packaged chip according to test result.Packaged chip processor removes packaged chip and will remove from user tray after is put in the slot of test pallet.Processor is sent to tester (this is called " loading operation ") with test pallet.Packaged chip after packaged chip after processor will be tested removes from the slot of test pallet and will test is put into (this is called " unloading operation ") on the user tray.
Processor comprises: load stacker, pile up has user tray herein; The unloading stacker, pile up has user tray herein, and each user tray waits to hold packaged chip after the test according to test result; Board accommodates the test pallet that is sent to tester packaged chip to be tested before and rests on herein; Load pick-up, be used for packaged chip to be tested is sent to test pallet from loading stacker; And the unloading pick-up, be used for the packaged chip after the test is sent to the unloading stacker from test pallet.
Load pick-up and pick up packaged chip to be tested, packaged chip to be tested is placed into the test pallet that rests on the board place from loading stacker.The test pallet that accommodates packaged chip to be tested is sent to tester.After packaged chip is tested, test pallet is sent to unloading unit.The unloading pick-up picks up packaged chip after the test from test pallet, is sent to the unloading stacker with the packaged chip after will testing.At this moment, according to test result, the packaged chip after the test is put in the corresponding user tray.
Processor comprises test cell 150, and this test cell is under extremely low and high temperature and at room temperature packaged chip is carried out electrical testing.Test cell comprises heating (or cooling) chamber, test cabinet and cooling (or heating) chamber.
The test pallet that accommodates packaged chip is sent to heating chamber or cooling chamber from board.In heating chamber or cooling chamber, packaged chip is heated to high temperature or is cooled to extremely low temperature.Then, accommodate very high temperature heating test pallet back or cooled packaged chip and be sent to test cabinet.In test cabinet, the test pallet that accommodates very high temperature heating back or cooled packaged chip contacts with test board in the tester (it is oppositely arranged with processor), thereby very high temperature heating back or cooled packaged chip are tested.Afterwards, test pallet is sent to cooling chamber or heating chamber, so that very high temperature heating back or cooled packaged chip are cooled to or are heated to room temperature.
But in traditional processor, the single test pallet that accommodates packaged chip is sequentially through heating (or cooling) chamber, test cabinet and cooling (heating) chamber.The quantity of the packaged chip that this has just limited once and has tested in preset time.
Summary of the invention
Therefore, the objective of the invention is in processor, transmit test pallet, to increase once and in the quantity of packaged chip of build-in test preset time.
According to an aspect of the present invention, provide a kind of method that is used for transmitting at processor test pallet, this processor comprises: second Room, this second Room have two test boards that are arranged in parallel; First Room, this first Room has a plurality of passages, and a plurality of test pallets move along described channel water level land, and this first Room is arranged on top, second Room; And the 3rd Room, the 3rd Room has a plurality of passages, a plurality of test pallets move along described channel water level land, the 3rd Room is arranged on below, second Room, and this method may further comprise the steps: (a) make two test pallets to wait for abreast at horizontal level in the wait place that is arranged at the processor front portion; (b) packaged chip is loaded on described two test pallets; (c) described two test pallets are turned to be in vertical position; (d) described two test pallets are moved upwards up in first Room; (e) level moves forward in two test pallets in first Room, heats or cools off described two test pallets; (f) described two test pallets are moved down into second Room from first Room; (g) two test boards in being arranged on second Room flatly move described two test pallets, described two test boards are relative with processor, therefore described two test pallets are contacted with described two test boards, so that test is contained in two packaged chips in the test pallet; (h) described two test pallets are moved down into the 3rd Room from second Room, and in the 3rd Room, move forward in described two test pallets, described two test pallets are cooled or are heated to room temperature; (i) described two test pallets are moved upwards up to the wait place from the 3rd Room; (j) described two test pallets are turned to be horizontal; And (k) unloading packaged chips from described two test pallets.
According to a further aspect in the invention, provide a kind of method that is used for transmitting at processor test pallet, this processor comprises: second Room, this second Room have two test boards that are arranged in parallel; First Room, this first Room has a plurality of passages, and a plurality of test pallets move along described channel water level land, and this first Room is arranged on below, second Room; And the 3rd Room, the 3rd Room has a plurality of passages, a plurality of test pallets move along described channel water level land, the 3rd Room is arranged on top, second Room, and this method may further comprise the steps: (a) make two test pallets flatly to wait at horizontal level in the wait place that is arranged at the processor front portion; (b) packaged chip is loaded on described two test pallets; (c) described two test pallets are turned to be in vertical position; (d) described two test pallets are moved down in first Room; (e) level moves forward in described two test pallets in first Room, heats or cools off described two test pallets; (f) described two test pallets are moved upwards up to second Room from first Room; (g) two test boards in being arranged on second Room flatly move described two test pallets, described two test boards are relative with processor, therefore described two test pallets are contacted with described two test boards, so that test is contained in two packaged chips in the test pallet; (h) described two test pallets are moved upwards up to the 3rd Room from second Room, and in the 3rd Room, move forward in described two test pallets, described two test pallets are cooled or are heated to room temperature; (i) described two test pallets are moved down into the wait place from the 3rd Room; (j) described two test pallets are turned to be horizontal; And (k) unloading packaged chips from described two test pallets.
According to a further aspect in the invention, provide a kind of method that is used for transmitting at processor test pallet, this processor comprises: second Room, this second Room have into four test boards that two row, two row are arranged; First Room, this first Room has a plurality of passages, and a plurality of test pallets move along described channel water level land, and this first Room is arranged on top, second Room; And the 3rd Room, the 3rd Room has a plurality of passages, a plurality of test pallets move along described channel water level land, the 3rd Room is arranged on below, second Room, and this method may further comprise the steps: (a) make two test pallets flatly to wait at horizontal level in the wait place that is arranged at the processor front portion; (b) packaged chip is loaded on described two test pallets; (c) described two test pallets are turned to be in vertical position; (d) described two test pallets are moved upwards up in first Room; (e) level moves forward in described two test pallets in first Room, heats or cools off described two test pallets; (f) two test pallets are moved down from first Room, and described two test pallets are placed on two following test station of second Room; (g) next group test pallet is moved down from first Room, and these two pallets are placed on two last test station of second Room; (h) four test boards in being arranged at second Room flatly move described four test pallets, described four test boards are relative with processor, therefore described four test pallets are contacted with described four test boards, so that test is contained in four packaged chips in the test pallet; (i) two test pallets are moved down into the 3rd Room from second Room, and in the 3rd Room, move forward in described two test pallets, described two test pallets are cooled or are heated to room temperature; (j) described two test pallets are moved upwards up to the wait place from the 3rd Room; (k) described two test pallets are turned to be horizontal; And (l) unloading packaged chips from described two test pallets.
According to a further aspect in the invention, provide a kind of method that is used for transmitting at processor test pallet, this processor comprises: second Room, this second Room have four test boards of embarking on journey and arranging; First Room, this first Room has a plurality of passages, and a plurality of test pallets move along described channel water level land, and this first Room is arranged on top, second Room; And the 3rd Room, the 3rd Room has a plurality of passages, a plurality of test pallets move along described channel water level land, the 3rd Room is arranged on below, second Room, and this method may further comprise the steps: (a) make two test pallets to wait for abreast at horizontal level in the wait place that is arranged at the processor front portion; (b) packaged chip is loaded on described two test pallets; (c) described two test pallets are turned to be in vertical position; (d) described two test pallets are moved upwards up in first Room; (e) flatly move two test pallets, and two test pallets of next group are moved upwards up in first Room, make four test pallets layout of embarking on journey; (f) level moves forward in described four test pallets in first Room, heats or cools off described four test pallets; (g) four test pallets are moved down into the test cabinet from first Room; (h) four test boards in being arranged at second Room flatly move described four test pallets, described four test boards are relative with processor, therefore described four test pallets are contacted with described four test boards, so that test is contained in four packaged chips in the test pallet; (i) four test pallets are moved down into the 3rd Room from second Room, and in the 3rd Room, move forward in described four test pallets, described four test pallets are cooled or are heated to room temperature; (j) two test pallets among described four test pallets are moved upwards up to the wait place from the 3rd Room; (k) described two test pallets are turned to be horizontal; (l) unloading packaged chips from described two test pallets; (m) in the 3rd Room, move horizontally remaining two test pallet, described remaining two test pallet are moved upwards up to from the 3rd Room wait for the place, and remaining two test pallet turns to and is horizontal with this; And (n) remaining two test pallet turns to and is horizontal with this.
According to a further aspect in the invention, provide a kind of method that is used for transmitting at processor test pallet, this processor comprises: second Room, this second Room have into four test boards that two row, two row are arranged; Two first Room; And two the 3rd Room, wherein, one side of contiguous second Room in one first Room and one the 3rd Room and arranging, and another first Room and another the 3rd Room are close to the opposite side of second Room and arrange that this method may further comprise the steps: (a) make two test pallets to wait for abreast at horizontal level in the wait place that is arranged at the processor front portion; (b) packaged chip is loaded on described two test pallets; (c) described two test pallets are turned to be in vertical position; (d) respectively described two test pallets are flatly moved to first Room from the wait place; (e) respectively in first Room level move forward described two test pallets; (f) four test pallets are moved to second Room of four test boards with two row, two row layouts from first Room in couples; (g) flatly move four test pallets that are positioned at four test station towards four test boards relative with processor; (h) four test pallets are moved to the 3rd Room from second Room, and in the 3rd Room, flatly move in four test pallets, will described four test pallets cool off or be heated to room temperature; (i) two test pallets (one of them is from each the 3rd Room) are moved to the wait place from the 3rd Room; (j) described two test pallets are in vertical position waiting for that the place turns to; And (k) unloading packaged chips from described two test pallets.
Description of drawings
Accompanying drawing is included to provide further understanding of the present invention and combinedly to come in and constitute this instructions part, and accompanying drawing shows embodiments of the invention, and is used for explaining principle of the present invention with explanation.
In the accompanying drawing:
Fig. 1 shows the vertical view of processor, and this processor uses the method that is used to transmit test pallet according to first embodiment of the invention;
Fig. 2 shows the rear view of test cell shown in Fig. 1;
Fig. 3 shows the skeleton view of the test cell of Fig. 2, and this figure helps to explain passage, when use according to first embodiment of the invention be used to transmit the method for test pallet the time, test pallet moves along this passage;
Fig. 4 shows the rear view of another test cell shown in Fig. 1;
Fig. 5 shows the skeleton view of the test cell of Fig. 4, and this figure helps to explain passage, when use according to second embodiment of the invention be used to transmit the method for test pallet the time, test pallet moves along this passage;
Fig. 6 shows the rear view of another test cell shown in Fig. 1;
Fig. 7 shows the skeleton view of the test cell of Fig. 6, and this figure helps to explain passage, when use according to third embodiment of the invention be used to transmit the method for test pallet the time, test pallet moves along this passage;
Fig. 8 shows the rear view of another test cell shown in Fig. 1;
Fig. 9 shows the skeleton view of the test cell of Fig. 8, and this figure helps to explain passage, when use according to fourth embodiment of the invention be used to transmit the method for test pallet the time, test pallet moves along this passage;
Figure 10 shows the skeleton view of the test cell of Fig. 8, and this figure helps to explain the path, when use according to fifth embodiment of the invention be used to transmit the method for test pallet the time, test pallet is along this path movement;
Figure 11 shows the rear view of another test cell shown in Fig. 1;
Figure 12 shows the skeleton view of the test cell of Figure 11, and this figure helps to explain passage, when use according to sixth embodiment of the invention be used to transmit the method for test pallet the time, test pallet moves along this passage;
Figure 13 shows the rear view of another test cell shown in Fig. 1;
Figure 14 shows the skeleton view of the test cell of Figure 13, and this figure helps to explain passage, when use according to seventh embodiment of the invention be used to transmit the method for test pallet the time, test pallet moves along this passage.
Embodiment
To introduce the preferred embodiments of the present invention in detail now, example of the present invention be shown in the accompanying drawing.
＜the first embodiment 〉
Fig. 1 shows the vertical view of processor, and this processor uses the method that is used to transmit test pallet according to first embodiment of the invention.
As shown in Figure 1, processor 100 comprises: load stacker 110, pile up has user tray herein; Unloading stacker 120, pile up has user tray herein, and each user tray holds packaged chip after the test according to test result; Board 130, the test pallet that accommodates packaged chip to be tested rested on before being sent to tester herein; Load pick-up, be used for packaged chip to be tested is sent to test pallet from loading stacker; And the unloading pick-up, be used for the packaged chip after the test is sent to the unloading stacker from test pallet.
Loading stacker 110 is arranged on the front portion of processor 100.Each user tray that all is used for holding packaged chip to be tested is stacked on and loads in the stacker 110.Unloading stacker 120 and loading stacker 110 be arranged in parallel adjacent to each other.User tray is put in the unloading stacker 120.The identification marking of expression packaged chip grade is assigned to each user tray.After test, the packaged chip after the test is classified and is contained in according to grade in the corresponding user tray.
As shown in Figure 1, board 130 is arranged on the rear portion of loading stacker 110 and unloading stacker 120.According to the first embodiment of the present invention, test pallet T is placed in the board 130 in couples.
In board 130, packaged chip to be tested is loaded onto on the test pallet T,, the packaged chip after the test is unloaded from test pallet T.Packaged chip to be tested is sent to test pallet T by loading pick-up from loading stacker 110.Packaged chip after the test is sent to unloading stacker 120 by the unloading pick-up from test pallet T.
The driver element that is used for moving forward and backward test pallet T can be arranged on board 130.The temporary transient buffer cell 136 that stops of packaged chip can be respectively adjacent to two transverse sides of board and be provided with.
Pick-up 140 goes in ring between loading stacker 110, buffer cell 136, board 130 and unloading stacker 120, so that transmit packaged chip.Pick-up 140 picks up packaged chip and packaged chip is placed on the test pallet T from test pallet T.
As shown in Figure 2, test cell 150 comprises first Room 151, second Room 152 and the 3rd Room 154, so that test on packaged chip.
In first Room 151, the packaged chip that is contained in from the test pallet T that board 130 transmits is heated to high temperature or is cooled to extremely low temperature.In second Room 152, be contained in very high temperature heating back among the test pallet T or the packaged chip after the utmost point sub-cooled and test by the external test (not shown).In the 3rd Room 154, be contained in packaged chip after the test among the test pallet T and be cooled or be heated to room temperature.
In first embodiment, two test boards 153 are arranged in second Room 152.Each test board 170 of external test contacts with each test board 153.Each test board 170 has a plurality of slots.These slots are electrically connected on external test.
Test board 170 is placed in vertical position, so that contact is arranged on the test board 153 at processor rear portion.
Be used for being arranged at second Room 152 towards the pushing unit 165 of test board push to test pallet T.Pushing unit 165 is exerted pressure to test pallet T, and T makes it against test board 153 with the push to test pallet, thereby respectively packaged chip is inserted in the slot of test board.Pushing unit 165 can move forward and backward test pallet T.
Two rots 160 are arranged on the place ahead of test cell 150.In board 130, rot 160 rotates the test pallet T of horizontal positioned, so that test pallet is placed vertical position.Rot 160 rotates from the test pallet T of the vertical placement of test cell 150 transmission, so that test pallet is placed horizontal level.
Be arranged at board 130 under the situation in 152 the place aheads, second Room, the first driver element (not shown) is arranged at test cell 150.The test pallet T that first driver element will vertically be placed moves up in couples, so that test pallet T is sent in first Room 151.And the second driver element (not shown) is arranged at test cell 150.The test cell that second driver element will vertically be placed moves forward in first Room 151 in couples, and the test pallet T that vertically places last to and the back keep given distance between a pair of.
The 3rd driver element is arranged at test cell 150.The test pallet T that the 3rd driver element will vertically be placed is moved down into the 3rd Room 154 from first Room 151 in couples through second Room 152.The 4 wheel driven moving cell is arranged at test cell 150.The test pallet T that the 4 wheel driven moving cell will vertically be placed moves forward in the 3rd Room 154 in couples, and the test pallet T that vertically places last to and the back keep given distance between a pair of.The 5th driver element is arranged at test cell 150.The test pallet T that the 5th driver element will vertically be placed moves up in couples from the 3rd Room 154, so that test pallet T is sent back board 130.
Describe the method that is used to transmit test pallet now, suppose that the processor of above-mentioned structure has the test cell 150 of structure as shown in Figure 2 according to first embodiment of the invention.
As shown in Figure 3, the test pallet T that each is all accommodated packaged chip to be tested is placed on 131 places, wait place of the front of second Room 152 in couples.Wait for that place 131 can be corresponding to board 130.Test pallet T waits in couples and is waiting for 131 places, place that each test pallet all is horizontal.
Each test pallet is turned to be in vertical position after, test pallet T is sent in first Room 151 in couples.
Be divided under the situation of two parts in first Room 151, two test pallet T be sent to respectively in two parts of first Room 151.Afterwards, the test pallet T of next group is placed in couples waits for 131 places, place, and be sent to respectively in two parts of first Room 151.
All these make test pallet T to be sent to continuously in couples in first Room 151.Compare with the transmission one by one of test pallet T, being transmitted in continuously when testing in pairs of test pallet T is more effective.
Two pallet T are turned to be in vertical position before, two test pallet T can flatly move given distance from waiting for place 131 towards second Room 152.
A certain position in as close as possible wait place 131, test pallet T can turn to and be in vertical position, with the transmission of accelerated test pallet T.Test pallet T is turned to be in vertical position after, test pallet T can move up, to send it in first Room 151.
After the test pallet T that vertically places was incorporated in first Room 151, it moved forward in first Room 151 in couples.At this moment, the test pallet T that vertically places last to and the back keep given distance between a pair of.
After a certain position above the test pallet T that vertically places arrives the test board 153 shown in Fig. 2, they are moved down in second Room 152 in couples.That is, vertically the test pallet T that places moves down in couples towards test board 153 (with reference to Fig. 2), and this test board just in time is positioned at the below of the test pallet T of vertical placement in couples, so that test pallet T is placed on the test board respectively.Then, be inserted in couples in the slot of two test boards 153 respectively being contained in two packaged chips among the test pallet T that vertically places.Afterwards, by external test packaged chip is tested.
Therefore this makes it possible to test simultaneously all packaged chips that are contained among two test pallet T, has increased the quantity of packaged chip at build-in test preset time.
The time that is used to transmit test pallet T in the process that test pallet T is sent in second Room 152 is shortened in expectation.This can be moved down into second Room 152 from first Room 151 by the test pallet T that lingeringly will vertically not place and realize.Therefore, place the test pallet T that vertically places near each test board 153.
After in second Room 152, packaged chip being tested, the test pallet T that vertically places is sent to the 3rd Room 154.Vertically the test pallet T that places lingeringly is not moved down into the 3rd Room 154, the time that is used to transmit test pallet with shortening from second Room 152.
First Room, second Room and the 3rd Room can be arranged on the vertical curve, so that vertically the test pallet T that places is free to drop down to second Room 152 and is free to drop down to the 3rd Room 154 from second Room 152 from first Room 151.
After the test pallet T that vertically places was incorporated in the 3rd Room 154, it moved forward in the 3rd Room 154 in couples.At this moment, test pallet T last to and the back keep given distance between a pair of.
When the test pallet T that vertically places arrived a certain position of waiting for below the place 131, they are moved upwards up in couples waited for place 131.The test pallet T that vertically places turned to be horizontal, waiting for that 131 places, place wait for then.
In fact, the test pallet T that vertically places is moved upwards up to after through the 3rd Room and waits for place 131.If be in horizontal level being rotated, and then be moved upwards up to and wait for place 131, then need the 5th structurally more complicated driver element, with the test pallet T of the horizontal positioned that moves up through test pallet T after the 3rd Room.But, in fact, when the test pallet T of vertical placement makes progress, can simplify the structure that is used for test pallet T is moved upwards up to from the 3rd Room 154 the 5th driver element of waiting for place 131, and accelerated test pallet T from the 3rd Room 154 to the transmission of waiting for place 131.
After test pallet T being sent back wait place 131, the packaged chip that is contained among the test pallet T is sent to unloading stacker 120 by the unloading pick-up.Each user tray that all has an identification marking (grade of the packaged chip that expression is to be received) is placed in the unloading stacker 120, correspondingly to hold the packaged chip after the test of classifying according to grade.
Packaged chip after will testing all after test pallet T unloading, is loaded into new packaged chip on the test pallet T by loading pick-up.That is, the packaged chip that simultaneously packaged chip to be tested is loaded into after test pallet T goes up and will test unloads from test pallet T.After holding new packaged chip, transmit test pallet T as described above.
Compare with the transmission one by one of test pallet T, the paired transmission of test pallet T has increased once and the quantity of the packaged chip tested in preset time.This is because test being contained in two packaged chips among the test pallet T simultaneously.
＜the second embodiment 〉
Fig. 4 shows the rear view of another test cell shown in Fig. 1.As shown in Figure 4, four test boards are arranged at second Room 252, and this second Room is arranged at test cell 250.These four test boards 253 are arranged in two row and two row.
A plurality of test pallet T are placed in the wait place 231.As shown in Figure 5, test pallet T is placed in couples wait 231 places, place.Packaged chip to be tested is loaded on the test pallet T by loading pick-up.Each test pallet T that all accommodates packaged chip to be tested is turned in couples by rot and is in vertical position.Then, the test pallet T that vertically places is sent in first Room 251 in couples, and in first Room 251, moves forward in couples.
When each test pallet T that vertically places arrived a certain position of test board 253 tops, vertically the test pallet T that places was moved down in second Room 252 in couples.At this moment, four test pallet T that vertically place move down in couples, it is placed into four test board 253 places as shown in Figure 4 respectively.
Then, be inserted into respectively in the slot of four test boards that butt up against (docked) four test boards 253 being contained in four packaged chips among the test pallet T that vertically places, and test by external test.
Like this, can be used for being furnished with the test cell of four test boards according to the method that is used to transmit test pallet of second embodiment of the invention.Test being contained in four packaged chips among the test pallet T simultaneously.Therefore, compare, increased once and in the quantity of packaged chip of build-in test preset time with first embodiment.
After in second Room, packaged chip being tested, the test pallet T that vertically places is sent in the 3rd Room 254 in couples.Vertically the test pallet T that places moves forward in the 3rd Room 254 in couples.
After a certain position below the test pallet T that vertically places arrives wait place 231, vertically the test pallet T that places moves up in couples.Waiting for 231 places, place, the test pallet T that vertically places is turned to be horizontal.
＜the three embodiment 〉
Fig. 6 shows the rear view of another test cell shown in Fig. 1.As shown in Figure 6, four test boards 353 are arranged at second Room 352.These four test boards become two row, two row to arrange.
The 3rd Room 354 is arranged in the below of first Room 351.The 3rd Room 354 comprises a left side the 3rd Room 354a and right the 3rd Room 354b.A left side the 3rd Room 354a is arranged in the below of the left first Room 351a, and right the 3rd Room 354b is arranged in the below of the right first Room 351b.With reference to Fig. 7, the method that is used to transmit test pallet according to third embodiment of the invention is described now.The difference of the 3rd embodiment and first embodiment is described, to remove the description of repetition from.
As shown in Figure 7, waiting for 331 places, place, each test pallet T that accommodates packaged chip to be tested is turned in couples be in vertical position.A test pallet T who vertically places is sent among the left first Room 351a, and another test pallet T that vertically places is sent among the right first Room 351b.These two the test pallet T that vertically place move forward in left first Room 351a and the right first Room 351b respectively.
These two the test pallet T that vertically place pass through left first Room 351a and the right first Room 351b respectively.Then, with these two the test pallet T that vertically place from the left first Room 351a and the right first Room 351b in couples horizontal transmission to second Room 352.After the test pallet that these two are vertically placed was incorporated in second Room 352, these two the test pallet T that vertically place moved down in couples.Then, two test pallet T that vertically place with another group are sent to second Room 352 from left first Room 351a and the right first Room 351b.After finishing all these, four test pallet T that vertically place that become two row, two row are placed into into four test station of two row, two row respectively.
Then, the pushing unit in second Room 352 is pushed into the test pallet T of the vertical placement of two row two row towards external test, so that packaged chip in rows and columns is inserted in the slot of test board, so that carry out electrical testing.
Like this, can be used for being furnished with the test cell of four test boards according to the method that is used to transmit test pallet of third embodiment of the invention.Simultaneously the packaged chip among four test pallet T that are contained in vertical placement is tested.Therefore, compare, increased once and the quantity of the packaged chip in preset time, tested with first embodiment.
After test, the test pallet T of a pair of vertical placement of bottom is moved horizontally to respectively among a left side the 3rd Room 354a and right the 3rd Room 354b.And the test pallet T of a pair of vertical placement on top is moved down into respectively among a left side the 3rd Room 354a and right the 3rd Room 354b.
When the test pallet T that vertically places moves forward in a left side the 3rd Room 354a and right the 3rd Room 354b respectively, with the packaged chip cooling after the test that is contained among the test pallet T of vertical placement or be heated to room temperature.
After each all arrived the end of a left side the 3rd Room 354a and right the 3rd Room 354b, vertically the test pallet T that places turned to right side and left side respectively, to move ahead towards the below of waiting for place 331.When being positioned at the below of waiting for place 331, vertically the test pallet T that places moves up, and waits for place 331 to turn back to.
Waiting for 331 places, place, the test pallet T that vertically places is turned to be horizontal.Waiting for 331 places, place, vertically the test pallet T that places can turn in couples and be horizontal.
A left side the 3rd Room 354a and right the 3rd Room 354b can be arranged at the top (not shown) of left first Room 351a and the right first Room 351b.
＜the four embodiment 〉
Fig. 8 shows the rear view of another test cell shown in Fig. 1.As shown in Figure 8, four test boards 453 are arranged at test cell 450.These four test boards are arranged in two row and two row.
First Room 451 comprises left first Room 451a and the right first Room 451b.A left side first Room 451a and the right first Room 451b arrange relative to each other diagonally, and second Room 452 is therebetween.The 3rd Room 454 comprises a left side the 3rd Room 454a and right the 3rd Room 454b.A left side the 3rd Room 454a and right the 3rd Room 454b arrange relative to each other diagonally, and second Room 452 is therebetween.
The method that is used to transmit test pallet according to fourth embodiment of the invention is described now.When the left first Room 451a is arranged at the below of the 3rd Room 454a, a left side and the right first Room 451b when being arranged at the top of right the 3rd Room 454b, adopt the method that is used to transmit test pallet according to fourth embodiment of the invention.The difference of the 4th embodiment and first embodiment is described, to remove the description of repetition from.
As shown in Figure 9, two test pallet T that each all accommodated packaged chip to be tested are placed on to horizontal parallel in couples and each other and wait for 431 places, place.These two test pallet T are turned in couples be in vertical position.
Left side test pallet T and right side test pallet T are sent to respectively among left first Room 451a and the right first Room 451b.
That is, be rotated be in vertical position after, left side test pallet T moves down, and then flatly moves among the left first Room 451a.Right side test pallet T flatly moves among the right first Room 451b.
The right first Room 451b is identical with the height of waiting for place 431 with the height of a left side the 3rd Room 454a, to shorten the distance that test pallet T must move.
After in being introduced in left first Room 451a and the right first Room 451b, vertically the test pallet T that places is moved horizontally to respectively among left first Room 451a and the right first Room 451b.After the end that arrives left first Room 451a and the right first Room 451b respectively, vertically the test pallet T that places moves towards second Room 452 respectively.
The treatment in accordance with the present invention machine comprises into the test board 453 that two row, two row are arranged.Four test pallet T are sent to test cell, so that be matched with four test boards 453.Promptly, at the test pallet T that is vertically placed after the left first Room 451a is incorporated into the test cabinet 452, a test pallet T who vertically places is placed on the test station of upper left side, and the test pallet T that the next one is vertically placed is placed on the test station of lower-left side.
With another test pallet T that vertically places after the right first Room 451b is incorporated into the test cabinet 452, another test pallet T that vertically places is placed on the test station of lower right side, and the test pallet T that the next one is vertically placed is placed on the test station of upper right side.Like this, just four test pallet T that vertically place are placed in the test cabinet 452.
Then, four test pallet T that vertically place are promoted towards test cell by the pushing unit (not shown) simultaneously, to carry out electrical testing on packaged chip.
After test, four test pallet T move to the 3rd Room 454 from test cabinet 452.
A fourth embodiment in accordance with the invention, a test pallet T who vertically places in the test cabinet 452 that will be provided with near a left side the 3rd Room 454a moves among the 3rd Room 454a of a left side.Another test pallet T that vertically places in the test cabinet 452 that will be provided with near right the 3rd Room 454b moves among right the 3rd Room 454b.
As shown in Figure 9, the test pallet T that is placed on the vertical placement at upper left test board 453 places is moved horizontally among the 3rd Room 454a of a left side.The next test pallet T that vertically places that is placed on lower-left test board 453 places is moved upwards up to upper left test board and is moved horizontally among the 3rd Room 454a of a left side.
The test pallet T that is placed on the vertical placement at bottom right test board 453 places is moved horizontally among right the 3rd Room 454b.The next test pallet T that vertically places that is placed on upper right test board 453 places is moved down into bottom right test board 453 and is moved horizontally among right the 3rd Room 454b.
When the test pallet T that vertically places moves forward in a left side the 3rd Room 454a and right the 3rd Room 454b respectively, with the test pallet T cooling of vertically placing or be heated to room temperature.After the end that arrives a left side the 3rd Room 454a and right the 3rd Room 454b respectively, vertically the test pallet T that places turns back to and waits for place 431.
That is, the test pallet T with the vertical placement among the 3rd Room 454a of a left side is moved horizontally to wait place 431.And the test pallet T of the vertical placement among right the 3rd Room 454b moved horizontally and then be moved upwards up to wait for place 431.
Waiting for 431 places, place, the test pallet T of the vertical placement that will return from a left side the 3rd Room 454a and right the 3rd Room 454b turns to and is horizontal.
When test pallet T was horizontal, the unloading pick-up was classified to the packaged chip after testing according to grade.
Waiting for 431 places, place, the packaged chip after the test is unloaded from test pallet T, and packaged chip to be tested is loaded on the test pallet T.The test pallet T that accommodates packaged chip to be tested is through aforesaid first Room 451, second Room 452 and the 3rd Room 454, to test on packaged chip to be tested.
A fourth embodiment in accordance with the invention, first Room and the 3rd Room are adjacent to the left side of second Room and right side and are provided with.This makes the left part of processor or right side part to operate independently of one another.Under the situation of a small amount of packaged chip of test (such as test again), to compare with the operation of entire process machine, the operation of a part of processor is more economical.
Left part or right side part that rotating unit in the wait place and the pushing unit in the test cabinet are suitable for the operational processes machine respectively.
＜the five embodiment 〉
The method that is used to transmit test pallet according to fifth embodiment of the invention is described now.When test cell is constructed as shown in Figure 8, use the method that is used to transmit test pallet according to fifth embodiment of the invention.The difference of the 5th embodiment and the 4th embodiment is described, to remove the description of repetition from.
As shown in figure 10, each loads pick-up packaged chip to be tested is loaded on each test pallet T, and test pallet is arranged on holding fix 431 places in pairs and abreast.Subsequently test pallet is turned to and be in vertical position.
Vertically the test pallet T that places is moved horizontally in second Room 452 after the end that arrives left first Room 451a and the right first Room 451b respectively.Vertically the test pallet T that places flatly moves to test board from left first Room 451a and the right first Room 451b respectively.
In the 5th embodiment, because vertically the test pallet T that places only flatly moves, so the driver element of the test pallet T that vertically places of not needing to move up from second Room 452.
Four test pallet T that vertically place that become two row, two row are placed on in couples four test station of two row, two row respectively.Four one of test pallet T that vertically place or promoted towards external test by the pushing unit (not shown) separately are in the slot with four test boards packaged chip being inserted into into two row, two row respectively, so that carry out electrical testing on packaged chip.
After packaged chip was tested, vertically the test pallet T that places moved in the 3rd Room.
In the 5th embodiment, the test pallet T that is positioned over down the vertical placement at test board 453 places moves among right the 3rd Room 454b, and the test pallet T that is positioned over the vertical placement at test board 453 places moves among the 3rd Room 454a of a left side.
When the test pallet T that vertically places moves horizontally in respectively at a left side the 3rd Room 454a and right the 3rd Room 454b, with the test pallet T cooling of vertically placing or be heated to room temperature.
Then, after each test pallet T that vertically places all arrived the end of a left side the 3rd Room 454a and right the 3rd Room 454b, vertically the test pallet T that places turned back to and waits for place 431.
As shown in Figure 10, be positioned at test pallet T on the left side of waiting for place 431 after, turn back to the right side of waiting for place 431 through second Room 452.Be positioned at vertical placement test pallet T on the right side of waiting for place 431 after, turn back to the left side of waiting for place 431 through second Room 452.Then, turn to and be horizontal being positioned over the left side of waiting for place 431 and the vertical placement test pallet T on the right side respectively.Waiting for 431 places, place, new packaged chip is loaded on the test pallet T by loading pick-up.And the packaged chip after the test is unloaded from test pallet T by the unloading pick-up.According to grade the packaged chip after testing is classified, and they are contained on the corresponding user tray.
That is, an assembling is carried that pick-up and unloading pick-up will new packaged chip be loaded into that the test pallet T that turns back to the right side of waiting for place 431 goes up and is unloaded packaged chip after testing from this test pallet T.Another assembling is carried that pick-up and unloading pick-up will new packaged chip be loaded into that the test pallet T that turns back to the left side of waiting for place 431 goes up and is unloaded packaged chip after testing from this test pallet T.
In the transport process of test pallet, carry with unloading operation more effective at an enterprising luggage of test pallet T simultaneously.
Infeasiblely be, new packaged chip is loaded on the test pallet T that is positioned at the place, left side that waits for place 431, and unload packaged chip after testing from the test pallet T that is positioned at the right side of waiting for place 431 simultaneously.This is because the test pallet T that begins from the right side of waiting for place 431 turns back to the left side of waiting for place 431.Therefore, must new packaged chip must be loaded on the same test pallet T simultaneously from the packaged chip after the test pallet T unloading test.
＜the six embodiment 〉
The method that is used to transmit test pallet according to sixth embodiment of the invention is described now.When test board as Figure 11 when becoming two row two row to be provided with as shown in 12, use the method that is used to transmit test pallet according to sixth embodiment of the invention.The difference of the 6th embodiment and the 4th embodiment is described, to remove the description of repetition from.
First Room comprises the first Room 551a and the last first Room 551b down.The 3rd Room comprises the 3rd Room 554a and last the 3rd Room 554b down.
According to a sixth embodiment of the invention, will descend the first Room 551a and the last first Room 551b to be arranged on the left side of processor.And will descend the 3rd Room 554a and last the 3rd Room 554b to be arranged on the right side of processor.
Can will descend the first Room 551a and the last first Room 551b to be combined into the first single Room 551, this first Room provides two passages, and two test pallet T move independently of one another along these two passages.Can provide two passages with descending the 3rd Room 554a and last the 3rd Room 554b to be combined into single Room 554, the three, the 3rd Room, two test pallet T move independently of one another along these two passages.
As shown in Figure 10, each loading pick-up is loaded into packaged chip to be tested in pairs and is set in parallel on each test pallet T at holding fix 531 places.Loading after pick-up is loaded into packaged chip to be tested on the test pallet T, test pallet T is turned in couples be in vertical position.
As shown in Figure 12, the test pallet T that will be arranged in the vertical placement in holding fix 531 left sides is moved horizontally to the first Room 551b.And the test pallet T that will be arranged in the vertical placement on holding fix 531 right sides moves down and flatly moves to the following first Room 551a that is arranged at first Room 551b below.
When the test pallet T of vertical placement respectively the first Room 551a down and on move forward among the first Room 551b in, with the test pallet T cooling of vertically placing or be heated to room temperature.After each test pallet T that vertically places arrived the end of second Room 552, vertically the test pallet T that places was respectively from the first Room 551a and the last first Room 551b move horizontally towards second Room down.That is, the test pallet T of the vertical placement among the last first Room 551b moves to test board, and the test pallet T of the vertical placement among the following first Room 551a moves to down test board.Like this, four test pallet T that become two row, two row vertically to place are positioned over into four test station of two row, two row respectively.
In the foregoing description, packaged chip is tested.
After packaged chip all tested, vertically the test pallet T that places flatly moved to respectively among following the 3rd Room 554a and last the 3rd Room 554b that is arranged on the processor right side.
Then, vertically the test pallet T that places moves forward, and arrives the end of following the 3rd Room 554a and last the 3rd Room 554b respectively.
Under each test pallet T that vertically places all arrives the 3rd Room 554a and on after the end of the 3rd Room 554b, vertically the test pallet T that places turns back to and waits for place 531.That is, the test pallet T of the vertical placement among last the 3rd Room 554b flatly moves, and turns back to the left side of waiting for place 531.The test pallet T of the vertical placement among the 3rd Room 554a flatly moves, moves up and turns back to the right side of waiting for place 531 down.At holding fix 531 places, the test pallet T that vertically places turned to be horizontal.
In the 6th embodiment, test pallet T flatly moves in second Room 552, and therefore, the driver element that is used for mobile test pallet T has structurally just been simplified.
＜the seven embodiment 〉
Figure 13 shows the rear view of another test cell shown in Fig. 1.As shown in Figure 13, four test boards 653 are arranged at second Room 652, and second Room is arranged at test cell 650.These four test boards are arranged in the delegation.
First Room 651 comprises left first Room 651a and the right first Room 651b.The 3rd Room 654 comprises a left side the 3rd Room 654a and right the 3rd Room 654b.A left side first Room 651a and the right first Room 651b are arranged at the top of second Room 652.A left side the 3rd Room 654a and right the 3rd Room 654b are arranged at the below of second Room 652.
Be provided with a plurality of passages in each of left first Room 651a and the right first Room 651b, a pair of test pallet T moves along described channel water level land.Be provided with a plurality of passages in each of a left side the 3rd Room 654a and right the 3rd Room 654b, a pair of test pallet T moves along described channel water level land.
A left side first Room 651a and the right first Room 651b can be combined into the first single Room 651, and this first Room utilizes dividing plate to be separated into two parts.
The method that is used to transmit test pallet according to seventh embodiment of the invention is described now.The difference of the 7th embodiment and the foregoing description is described, to remove the description of repetition from.
As shown in Figure 14, each loading pick-up is loaded into packaged chip to be tested in pairs and is arranged in abreast on each the test pallet T that waits for 631 places, place.Loading after pick-up is loaded into packaged chip to be tested on the test pallet T, test pallet T is turned in couples be in vertical position.Subsequently, the test pallet T that vertically places is moved upwards up to respectively among left first Room 651a and the right first Room 651b.
A left side first Room 651a and the right first Room 651b have slit separately.By these slits, vertically the test pallet T that places is from waiting for that place 631 moves to respectively left first Room 651a and the right first Room 651b.
The test pallet T that is introduced in the vertical placement among the left first Room 651a flatly moves.The test pallet T that the next one is vertically placed is incorporated among the left first Room 651a.Therefore, the test pallet T of a pair of vertical placement is positioned among the left first Room 651a in parallel with each other.In an identical manner, the test pallet T with a pair of vertical placement is positioned among the right first Room 651b in parallel with each other.
Vertically the test pallet of placing is moved horizontally to respectively among left first Room 651a and the right first Room 651b T.Therefore, the test pallet T with four vertical placements altogether are placed among left first Room 651a and the right first Room 651b simultaneously.
After the end that arrives left first Room 651a and the right first Room 651b respectively, this test pallet of vertically placing is moved down in second Room 652 T.
Therefore, four test pallet T that vertically place are placed in second Room 652 with embarking on journey.Four test pallet T that vertically place that embark on journey are promoted towards external test by pushing unit, are contained in four packaged chips among the test pallet T that vertically places with test.
After packaged chip tested, this test pallet of vertically placing was moved down into respectively among a left side the 3rd Room 654a and right the 3rd Room 654b T.
When this test pallet of vertically placing moves forward in respectively at a left side the 3rd Room 654a and right the 3rd Room 654b T, with this test pallet of vertically placing to the T cooling or be heated to room temperature.
After each test pallet T that vertically places all arrived the end of a left side the 3rd Room 654a and right the 3rd Room 654b, vertically the test pallet T that places was towards waiting for that place 631 moves up.Waiting for 631 places, place, the test pallet T that vertically places is turned to be horizontal.
A left side the 3rd Room 654a and right the 3rd Room 654b have slit respectively.By described slit, vertically the test pallet T that places is moved upwards up to right the 3rd Room 654b from a left side the 3rd Room 654a respectively one by one and waits for place 631.
A slit is only arranged for each first Room and the 3rd Room so that each chamber keeps sealing as far as possible.This feasible temperature that is easy to control in first Room and the 3rd Room.
When the test pallet T of vertical placement turns back to when waiting for place 631, the test pallet T that vertically places is turned to be horizontal.Packaged chip after the unloading pick-up is tested from test pallet T unloading, and the loading pick-up installs to new packaged chip on this test pallet T.According to grade, the packaged chip after the test is classified and is contained in the corresponding user tray.
Because the present invention can realize under the prerequisite that does not deviate from spirit of the present invention or essential characteristic in a variety of forms, so should be appreciated that, the foregoing description is not subjected to the restriction of any details in the foregoing description, except as otherwise noted, on the contrary, should in the spirit and scope of the invention that claims limit, explain the present invention widely, therefore, fall in claim border and the scope or fall into all changes in the equivalent of described border and scope and change and to be overwritten by the appended claims.
Claims (17)
1. method that is used for transmitting test pallet at processor, described processor comprises: second Room, described second Room have two test boards that are arranged in parallel; First Room, described first Room has a plurality of passages, and a plurality of test pallets move along described channel water level land, and described first Room is arranged on top, described second Room; And the 3rd Room, described the 3rd Room has a plurality of passages, and a plurality of test pallets move along described channel water level land, and described the 3rd Room is arranged on below, described second Room, said method comprising the steps of:
(a) make two test pallets to wait for abreast at horizontal level in the wait place that is arranged at described processor front portion;
(b) packaged chip is loaded on described two test pallets;
(c) described two test pallets are turned to be in vertical position;
(d) described two test pallets are moved upwards up in described first Room;
(e) in described first Room, flatly move forward in described two test pallets, heat or cool off described two test pallets;
(f) described two test pallets are moved down into described second Room from described first Room;
(g) flatly move described two test pallets towards two test boards that are connected in described second Room, described two test boards are relative with described processor, therefore described two test pallets are contacted with described two test boards, so that test is contained in the described packaged chip in described two test pallets;
(h) described two test pallets are moved down into described the 3rd Room from described second Room, and in described the 3rd Room, move forward in described two test pallets, described two test pallets are cooled or are heated to room temperature;
(i) described two test pallets are moved upwards up to described wait place from described the 3rd Room;
(j) described two test pallets are turned to be horizontal; And
(k) from the described packaged chip of described two test pallets unloading.
2. method according to claim 1, wherein, described two test pallets move in couples simultaneously.
3. method according to claim 1 further comprises: described two test pallets are turned to be in vertical position before, make described two test pallets move horizontally given distance towards described second Room from described wait place.
4. method according to claim 1 wherein, in step (k), from the described packaged chip of described two test pallets unloading, is loaded into new packaged chip on described two test pallets simultaneously.
5. method that is used for transmitting test pallet at processor, described processor comprises: second Room, described second Room have two test boards that are arranged in parallel; First Room, described first Room has a plurality of passages, and a plurality of test pallets move along described channel water level land, and described first Room is arranged on below, described second Room; And the 3rd Room, described the 3rd Room has a plurality of passages, and a plurality of test pallets move along described channel water level land, and described the 3rd Room is arranged on top, described second Room, said method comprising the steps of:
(a) make two test pallets to wait for abreast at horizontal level in the wait place that is arranged at described processor front portion;
(b) packaged chip is loaded on described two test pallets;
(c) described two test pallets are turned to be in vertical position;
(d) described two test pallets are moved down in described first Room;
(e) in described first Room, flatly move forward in described two test pallets, heat or cool off described two test pallets;
(f) described two test pallets are moved upwards up to described second Room from described first Room;
(g) two test boards in being arranged at described second Room flatly move described two test pallets, described two test boards are relative with described processor, therefore described two test pallets are contacted with described two test boards, so that test is contained in the described packaged chip in described two test pallets;
(h) described two test pallets are moved upwards up to described the 3rd Room from described second Room, and in described the 3rd Room, move forward in described two test pallets, make described two test pallets cooling or be heated to room temperature;
(i) described two test pallets are moved down into described wait place from described the 3rd Room;
(j) described two test pallets are turned to be horizontal; And
(k) from the described packaged chip of described two test pallets unloading.
6. method that is used for transmitting test pallet at processor, described processor comprises: second Room, described second Room have into four test boards that two row, two row are arranged; First Room, described first Room has a plurality of passages, and a plurality of test pallets move along described channel water level land, and described first Room is arranged on top, described second Room; And the 3rd Room, described the 3rd Room has a plurality of passages, and a plurality of test pallets move along described channel water level land, and described the 3rd Room is arranged on below, described second Room, said method comprising the steps of:
(a) make two test pallets to wait for abreast at horizontal level in the wait place that is arranged at described processor front portion;
(b) packaged chip is loaded on described two test pallets;
(c) described two test pallets are turned to be in vertical position;
(d) described two test pallets are moved upwards up in described first Room;
(e) in described first Room, flatly move forward in described two test pallets, heat or cool off described two test pallets;
(f) described two test pallets are moved down from described first Room, and described two test pallets are placed on two following test station of described second Room;
(g) next group test pallet is moved down from described first Room, and described two pallets are placed on last two test station of described second Room;
(h) four test boards in being arranged at described second Room flatly move described four test pallets, described four test boards are relative with described processor, therefore described four test pallets are contacted with described four test boards, so that test is contained in the described packaged chip in described four test pallets;
(i) described two test pallets are moved down into described the 3rd Room from described second Room, and in described the 3rd Room, move forward in described two test pallets, make described two test pallets cooling or be heated to room temperature;
(j) described two test pallets are moved upwards up to described wait place from described the 3rd Room;
(k) described two test pallets are turned to be horizontal; And
(l) from the described packaged chip of described two test pallets unloading.
7. method that is used for transmitting test pallet at processor, described processor comprises: second Room, described second Room have four test boards of embarking on journey and arranging; First Room, described first Room has a plurality of passages, and a plurality of test pallets move along described channel water level land, and described first Room is arranged on top, described second Room; And the 3rd Room, described the 3rd Room has a plurality of passages, and described a plurality of test pallets move along described channel water level land, and described the 3rd Room is arranged on below, described second Room, said method comprising the steps of:
(a) make two test pallets to wait for abreast at horizontal level in the wait place that is arranged at described processor front portion;
(b) packaged chip is loaded on described two test pallets;
(c) described two test pallets are turned to be in vertical position;
(d) described two test pallets are moved upwards up in described first Room;
(e) flatly move described two test pallets, and two test pallets of next group are moved upwards up in described first Room, make described four test pallets layout of embarking on journey;
(f) in described first Room, flatly move forward in described four test pallets, heat or cool off described four test pallets;
(g) described four test pallets are moved down into the described test cabinet from described first Room;
(h) four test boards in being arranged at described second Room flatly move described four test pallets, described four test boards are relative with described processor, therefore described four test pallets are contacted with described four test boards, so that test is contained in the described packaged chip in four test pallets;
(i) described four test pallets are moved down into described the 3rd Room from described second Room, and in described the 3rd Room, move forward in described four test pallets, make described four test pallets cooling or be heated to room temperature;
(j) two test pallets among described four test pallets are moved upwards up to described wait place from described the 3rd Room;
(k) described two test pallets are turned to be horizontal;
(l) from the described packaged chip of described two test pallets unloading;
(m) in described the 3rd Room, move horizontally remaining two test pallet, described remaining two test pallet are moved upwards up to described wait place from described the 3rd Room, and described remaining two test pallet are turned to be horizontal; And
(n) described remaining two test pallet are turned to be horizontal.
8. method that is used for transmitting test pallet at processor, described processor comprises: second Room, described second Room have into four test boards that two row, two row are arranged; Two first Room; And two the 3rd Room, wherein, a side of contiguous described second Room in one first Room and one the 3rd Room and arranging, and the opposite side of contiguous described second Room in another first Room and another the 3rd Room and arranging said method comprising the steps of:
(a) make two test pallets to wait for abreast at horizontal level in the wait place that is arranged at described processor front portion;
(b) packaged chip is loaded on described two test pallets;
(c) described two test pallets are turned to be in vertical position;
(d) respectively described two test pallets are moved to described first Room from described wait place;
(e) respectively in described first Room level move forward described two test pallets;
(f) described four test pallets are moved to described second Room of four test boards with two row, two row layouts from described first Room in couples;
(g) flatly move four test pallets that are positioned at four test station towards four test boards relative with described processor;
(h) described four test pallets are moved to described the 3rd Room from described second Room, and in described the 3rd Room, flatly move forward in described four test pallets, with described four test pallets cooling or be heated to room temperature;
(i) described two test pallets are moved to described wait place from described the 3rd Room, described two test pallets are respectively from described two the 3rd Room;
(j), described two test pallets are turned to be in vertical position in described wait place; And
(k) from the described packaged chip of described two test pallets unloading.
9. method according to claim 8, wherein, described two first Room comprise first Room, a left side that is arranged at left side, described second Room and first Room, the right side that is arranged at right side, described second Room, and described two the 3rd Room comprise the 3rd Room, a left side that is arranged at below, described left first Room and the 3rd Room, the right side that is arranged at below, described right first Room.
10. method according to claim 9, wherein, in step (f), described two test pallets flatly move to described second Room from described left first Room and described right first Room respectively, and move down to be placed on described test station down, and two test pallets of next group flatly move to described second Room from described left chamber and described right ventricle, and move to be placed on the described test station that goes up.
11. method according to claim 9, wherein, in step (i), described two test pallets flatly move from described left the 3rd Room and described right the 3rd Room respectively, and are moved upwards up to described wait place.
12. method according to claim 8, wherein, described first Room comprises the left side of contiguous described second Room and the right side of first Room, a left side that is provided with and contiguous described second Room and first Room, the right side that is provided with, and described the 3rd Room comprises the 3rd Room, a left side that is arranged at top, described left first Room and the 3rd Room, the right side that is arranged at below, described right first Room.
13. method according to claim 12, wherein, step (f) comprises following each step:
Described two test pallets are moved horizontally, one of them test pallet is from described left first Room, and another test pallet is from described right first Room, and will move up from the test pallet of described left first Room, will move down from the test pallet of described right first Room; And
Described two test pallets are moved horizontally in described second Room, and one of them test pallet is from described left first Room, and another test pallet is from described right first Room.
14. method according to claim 12, wherein, step (f) may further comprise the steps: described two test pallets are moved horizontally in described second Room, one of them test pallet is from described left first Room, and another test pallet is from described right first Room, and described two test pallets are moved horizontally from described left first Room and described right first Room.
15. a method that is used for transmitting at processor test pallet, described processor comprises: second Room, described second Room have into four test boards that two row, two row are arranged; Following first Room and last first Room, each all is close to a side of described second Room and is provided with; And following the 3rd Room and last the 3rd Room, each all is close to the opposite side of described second Room and is provided with, and said method comprising the steps of:
(a) make two test pallets flatly to wait at horizontal level in the wait place that is arranged at described processor front portion;
(b) packaged chip is loaded on described two test pallets;
(c) described two test pallets are turned to be in vertical position;
(d) respectively described two test pallets are moved horizontally, and described two test pallets are moved to respectively described first Room down and described last first Room from described wait place;
(e) respectively described down first Room and described in first Room, move forward described two test pallets;
(f) described four test pallets are moved to described second Room in pairs and continuously from described first Room down and described last first Room, described second Room has into four test boards that two row, two row are arranged;
(g) move described four test pallets that are positioned at described four test station towards four test boards relative with described processor;
(h) described four test pallets are moved to described the 3rd Room down and described last the 3rd Room from described second Room, and described down the 3rd Room and described on when level moves forward described four test pallets respectively in the 3rd Room, will described four test pallets cool off or be heated to room temperature;
(i) described two test pallets are moved to described wait place, one of them test pallet is from described the 3rd Room down, and another test pallet is from described last the 3rd Room;
(j), described two test pallets are turned to be in vertical position at described wait place place; And
(k) from the described packaged chip of described two test pallets unloading.
16. method according to claim 15, wherein, in step (d), a test pallet flatly moves, and another test pallet moves down and then moves horizontally.
17. method according to claim 15, wherein, in step (i), a test pallet flatly moves to described wait place from described the 3rd Room down, and another test pallet flatly moves from described last the 3rd Room and then moves up.
Applications Claiming Priority (12)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060115697A KR20080046356A (en) | 2006-11-22 | 2006-11-22 | Method for transferring test tray of handler |
| KR10-2006-0115701 | 2006-11-22 | ||
| KR10-2006-0115700 | 2006-11-22 | ||
| KR10-2006-0115697 | 2006-11-22 | ||
| KR10-2006-0115699 | 2006-11-22 | ||
| KR1020060115699 | 2006-11-22 | ||
| KR1020060115701 | 2006-11-22 | ||
| KR1020060115700 | 2006-11-22 | ||
| KR1020060115701A KR100765463B1 (en) | 2006-11-22 | 2006-11-22 | Method for transferring test tray of handler |
| KR1020060115697 | 2006-11-22 | ||
| KR1020060115700A KR100765462B1 (en) | 2006-11-22 | 2006-11-22 | Method for transferring test tray of handler |
| KR1020060115699A KR100765461B1 (en) | 2006-11-22 | 2006-11-22 | Method for transferring test tray of handler |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101246193A CN101246193A (en) | 2008-08-20 |
| CN101246193B true CN101246193B (en) | 2011-01-12 |
Family
ID=39663302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101948092A Active CN101246193B (en) | 2006-11-22 | 2007-11-22 | Method of transferring test trays in a handler |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR20080046356A (en) |
| CN (1) | CN101246193B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101334765B1 (en) * | 2012-04-18 | 2013-11-29 | 미래산업 주식회사 | Handling System for Semiconductor device |
| KR101373489B1 (en) * | 2012-09-25 | 2014-03-12 | 세메스 주식회사 | Test handler |
| CN105309177B (en) * | 2015-01-22 | 2018-11-06 | 侯小八 | The method of leaf vegetables Smartsize seeding and seedling raising and direct-seeding planting |
| KR102390564B1 (en) * | 2015-08-04 | 2022-04-27 | (주)테크윙 | Rotateor for test handler and test handler |
| CN109709463A (en) * | 2017-10-25 | 2019-05-03 | 泰克元有限公司 | Manipulator |
| KR20200038040A (en) * | 2018-10-02 | 2020-04-10 | (주)테크윙 | Handler for testing electronic component |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5290134A (en) * | 1991-12-03 | 1994-03-01 | Advantest Corporation | Pick and place for automatic test handler |
| US5650732A (en) * | 1993-07-02 | 1997-07-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device test system |
| US5805472A (en) * | 1996-02-27 | 1998-09-08 | Kabushiki Kaisha Toshiba | Test handler for semiconductor devices |
| US6104183A (en) * | 1995-07-26 | 2000-08-15 | Advantest Corporation | Semiconductor device testing apparatus |
| US6498472B1 (en) * | 1998-11-30 | 2002-12-24 | Mirae Corporation | Method for handling a module IC and a carrier of a module IC handler |
| CN1226635C (en) * | 1997-07-02 | 2005-11-09 | 株式会社爱德万测试 | Tester for semiconductor devices and test tray used for the same |
-
2006
- 2006-11-22 KR KR1020060115697A patent/KR20080046356A/en not_active Application Discontinuation
-
2007
- 2007-11-22 CN CN2007101948092A patent/CN101246193B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5290134A (en) * | 1991-12-03 | 1994-03-01 | Advantest Corporation | Pick and place for automatic test handler |
| US5650732A (en) * | 1993-07-02 | 1997-07-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device test system |
| US6104183A (en) * | 1995-07-26 | 2000-08-15 | Advantest Corporation | Semiconductor device testing apparatus |
| US5805472A (en) * | 1996-02-27 | 1998-09-08 | Kabushiki Kaisha Toshiba | Test handler for semiconductor devices |
| CN1226635C (en) * | 1997-07-02 | 2005-11-09 | 株式会社爱德万测试 | Tester for semiconductor devices and test tray used for the same |
| US6498472B1 (en) * | 1998-11-30 | 2002-12-24 | Mirae Corporation | Method for handling a module IC and a carrier of a module IC handler |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20080046356A (en) | 2008-05-27 |
| CN101246193A (en) | 2008-08-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101246193B (en) | Method of transferring test trays in a handler | |
| US7876089B2 (en) | Test handler, method for loading and manufacturing packaged chips, and method for transferring test trays | |
| US7495463B2 (en) | System and method for transferring trays within a test handler | |
| CN103369941B (en) | Apparatus and method for manufacturing substrate | |
| KR100312093B1 (en) | Tester for semiconductor devices and test tray used for the same | |
| KR100301750B1 (en) | Apparatus for removing and storing semiconductor device trays | |
| KR100938466B1 (en) | Handler, Method of Unloading Semiconductor, Method of Transferring Test-tray, and Method of Manufacturing Semiconductor | |
| CN101191809B (en) | Apparatus for rotating a test tray in a handler | |
| CN101234382A (en) | System for sorting packaged chips and method for sorting packaged chips | |
| US20070018673A1 (en) | Electronic component testing apparatus | |
| KR101158064B1 (en) | Electronic component testing equipment and method of testing electronic component | |
| CN106885982A (en) | Carrier for processing component, component and method | |
| US20050162151A1 (en) | Device transfer mechanism for a test handler | |
| WO2009144790A1 (en) | Electronic component handling apparatus, electronic component test apparatus and electronic component holding tray | |
| CN101231324B (en) | Test tray and handler using the test tray | |
| CN101334446B (en) | Device and method for transferring test trays and a handler having same, process for manufacturing semiconductor device | |
| US20080145203A1 (en) | Method of transferring test trays in a handler | |
| CN101211808B (en) | Picker for use in a handler and method for enabling the picker to place packaged chips | |
| US10120016B2 (en) | Semiconductor test apparatus | |
| KR101042652B1 (en) | Electronic Component Testing Apparatus | |
| KR19990082894A (en) | Integrated circuit testing apparatus | |
| KR100714752B1 (en) | Electronic component test apparatus | |
| US7501809B2 (en) | Electronic component handling and testing apparatus and method for electronic component handling and testing | |
| TWI385750B (en) | An electronic component shifting device and an electronic component testing device having the same | |
| KR20040111541A (en) | Electronic component test apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |