CN101256536B - Flash memory address translation layer system - Google Patents
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- CN101256536B CN101256536B CN200710079570A CN200710079570A CN101256536B CN 101256536 B CN101256536 B CN 101256536B CN 200710079570 A CN200710079570 A CN 200710079570A CN 200710079570 A CN200710079570 A CN 200710079570A CN 101256536 B CN101256536 B CN 101256536B
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Abstract
A flash memory address translation layer system connected with a flash memory and an EMS read/write controller comprises: an instruction buffer for connecting with the EMS memory read/wrote controller; a logical address buffer for connecting the EMS memory read/wrote controller; a data buffer for connecting with the EMS memory and the EMS memory read/wrote controller; a pair of assistant controller for providing an instruction assistant function for controlling data's read/write; a microprocessor for connecting the instruction buffer and two assistant controllers; an address translation unit for connecting the microprocessor; a flash memory address buffer for connecting with the assistant controller, address translation unit and the flash; a adjustable address translation layer unit for connecting with an assistant controller; a quick fetch instruction and data buffer for connecting with the adjustable address translation unit. The invention can greatly reduce the number of invalid data collection and occupy capacity of the flash memory, and has a quick mechanism with space efficiency to improve and quicken the efficiency which the logical address corresponds to the real flash address.
Description
Technical field
The present invention relates to a kind of flash memory address translation layer system, relate in particular to a kind of data reading and writing that are applied to flash memory, and have thick draw, the thin address translation the adjusted layer unit of adjusting of drawing change the location operated system to provide.
Background technology
Flash memory is widely used in main frame or the consumption electronic products, for example: existing carry-on dish, flash memory in the MP3 player, be modal flash memory application example, yet, NAND type flash memory (NAND flash memory) is widely used in embedded storage system at present, flash memory is made up of a lot of paging (Page), each paging size is (for example 512 bytes) of fixing, the continuous paging (for example 32 pagings) of some of them can be formed a block (Block), because the flash memory characteristic is not allow action that same identical paging done to write, unless the action of the block at that Block Paging place being elimination (erase) is arranged in advance, because this access features has also caused the difficulty on the management flash memory.
Usually for flash memory can be operated under original system, for example at original archives economy and form (FAT16/32, NTFS, EXT2...) running down, wherein the most normal adopted method is to safeguard the method for an address translation table (Address Translation Table), the method is by the address that logical address is corresponded to real flash memory, causing us to become flash memory emulation is a continuous memory headroom, therefore we just can not change under original setting, it similarly is a hard disk unit (Hard Disk) that flash memory is regarded, we claim this method the flash memory address conversion layer (NAND Flash Translation Layer, NFTL).
As shown in Figure 1, it is the way of an existing typical flash memory address conversion layer, wherein, one flash memory X forms with a lot of blocks (block), and this flash memory address conversion layer is exactly with base unit and the conversion regime of block grade (block-level) as addressing, include two kinds of different addressing blocks, one is main blocks (primary block) X1, another is replacement block (replacement block) X2, a main blocks X1 has the replacement block X2 of a correspondence, this main blocks X1 has 8 memory page X10～X17, this replacement block X2 has 8 memory page X20～X27, this replacement block X2 is used for storing the data that cannot write main blocks X1, as a logical block addresses LBA=n (logical block addresses quantity) when being written into, can calculate two values, be respectively that a virtual area block address (virtual block address) VBA is with a block displacement (block offset) BO, virtual area block address VBA is logical block addresses quantity n/ block number of pages b (supposing that a block has b pages), block displacement BO=n%b, it is the remainder of n/b, by virtual area block address VBA, can find an address that writes the pairing main blocks X1 of record with replacement block X2 by above-mentioned existing flash memory address conversion layer.
By above-mentioned block displacement BO value, which data are write in the memory page of block displacement BO of main blocks X1, if that memory page was write, then we just write data first blank memory page (free page) of replacement block X2, suppose to begin to write last memory page X27 from first memory page X20 of replacement block X2, at last when memory page X20～X27 of replacement block X2 has been write, existing flash memory address conversion layer method is not have main blocks X1 out-of-date data to write another new main blocks X1 with in the replacement block X2, and, existing flash memory address conversion layer upgrades the thick table of comparisons (coarse-grained table) CGT (as shown in Figure 2) of drawing of inside, makes this virtual thick table of comparisons CGT of drawing can correspond to this new main blocks X1 later.
Fig. 1 enumerates the example that a logical block addresses LBA=1011 writes, the operator scheme of this existing flash memory address conversion layer method is described, virtual area block address VBA=1011/8=126, this block displacement BO is 1101%8, being 1101-8*126=3, is (9 as the contents value of this virtual area block address VBA=126.23), it is 9 main blocks X1 that i.e. expression writes recording address, write and be recorded as 23 replacement block X2, and be 3 according to block displacement BO, data are write among the memory page X13 of main blocks X1, suppose that this memory page X13 is used, then data are write first blank memory page of replacement block X2, memory page X22 as shown in Figure 1, and finish the existing flash memory address conversion layer method of operating that this logical block addresses LBA=1011 data write.
Please cooperate shown in Figure 2; and then illustrate existing flash memory address translation layer system and how to finish invalid data collection (garbage collection) operation; as shown in Figure 2; suppose to have five logical block addresses a1; b1; c1; five different logical block addresses LBA of d1 and e1; their DATA DISTRIBUTION as shown in Figure 2; this replacement block X2 is write to be over; so have the demand action generation that invalid data is collected; invalid data is collected the action meeting main blocks address PPBA=1 among the main blocks X1 is copied to another new main blocks address PPBA=3 with all legal memory pages of replacement block address RPBA=2 the inside; these two main blocks address PPBA=1 can erase then with replacement block address RPBA=2; originally in thick address of drawing also essential this new main blocks address PPBA=3 of record of the corresponding write activity in table of comparisons CGT the inside; and this replacement block address RPBA can be set as empty; promptly this replacement block address RPBA value is made as-1; its operational motion is shown in each direction of arrow among Fig. 2; but the existing flash memory address translation layer system of this kind can limit the number of replacement block X2 usually; when replacement block X2 quantity is too much; the action that will carry out the invalid data collection reduces the number of replacement block, makes existing flash memory change the action that layer system need spend more memory capacity and carry out the invalid data collection of more number of times.
Above-mentioned existing flash memory address translation layer system, when flash capacity is increasing, the flash memory address conversion layer goes to safeguard its address translation table in order to save the random access memory space, and take the response mechanism of block level, but the response mechanism of this block level can cause the process of " address that logical address corresponds to real flash memory " to lack efficient, because flash memory is being read, all be to be the unit of reading when writing with paging, but under the block level, spend when obtaining up-to-date branch page address a period of time to search paging in the block possibly, this flash memory is read, efficient and speed when writing are affected.
In addition, before relevant patent aspect the case document, as I253564 number " flash memory data access management system and method thereof " patent of invention case of TaiWan, China patent announcement and I249670 number " system and the method thereof of the data that can write in proper order to the flash memory " patent of invention case, then disclose the commentaries on classics location technology of typical existing flash data read-write respectively, the management method of good bad block and virtual block write method and the technology of data to the flash memory in proper order, lack efficient in the process that also needs logical address to correspond to the address of real flash memory aspect reading and writing data and the commentaries on classics location, and make the speed of reading and writing data also be subjected to related harmful effect.
Summary of the invention
Technical problem underlying to be solved by this invention is, overcome the above-mentioned defective that prior art exists, and provide a kind of flash memory address translation layer system, it proposes the address translation adjusted a layer unit with thick division and thin division and adjusts and provide flash memory physical address and logical place to change the location data, to reduce capacity and the number of times that invalid data is collected, and the mechanism of getting soon with space efficiency promotes and accelerates the efficient that logical address corresponds to the address of real flash memory, can significantly reduce the number of times that the invalid data of flash memory collects and take capacity, the mechanism of getting soon with space efficiency promotes and accelerates the efficient that logical address corresponds to the address of real flash memory.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of flash memory address translation layer system, it is characterized in that be connected between a flash memory and the memory read-write controller, its structure comprises: an Instruction Register, connect this memory read-write controller, with the instruction that receives the flash data read-write that this memory read-write controller sends and buffer memory it; One logical address cache device connects the memory read-write controller, with receive from the logical address data of the reading and writing data of this memory read-write controller and buffer memory it; One data buffer is connected between flash memory and memory read-write controller, with as the buffer that reads and writes data between flash memory and memory read-write controller; One first subcontrol and one second subcontrol, the instruction subsidiary function of data read-write control is provided, wherein this first subcontrol connects logical address cache device, data buffer, so that the auxiliary control of this logical address cache device, data buffer to be provided; One microprocessor, link order buffer, two subcontrols, this microprocessor are flash data read-write control and change the location and get the maincenter that control is carried out soon; One address conversioning unit connects microprocessor, and the logical address and the physical address that store the flash data read-write in this address conversioning unit in advance change the location data, changes the location data with logical address and the physical address that the required flash data read-write of microprocessor is provided; One flash memory address buffer connects between this second subcontrol, address conversioning unit and flash memory, with the physical address data of this flash memory of buffer memory when the reading and writing data; One can adjust address translation layer unit, connect this second subcontrol, thin contrast and thick two kinds of address translation features of contrast of drawing drawn are provided, carry out the instruction of address translation layer operation result, the reading and writing data of this flash memory mechanism of getting soon and data are sent in the microprocessor by this second subcontrol; One fast instruction fetch and data buffer connects this and can adjust address translation layer unit, can adjust instruction and the metadata cache of address translation layer unit as the reading and writing data of the flash memory mechanism of getting soon so that this to be provided.
Aforesaid flash memory address translation layer system, wherein address conversioning unit is a random access memory.
Aforesaid flash memory address translation layer system, wherein can adjust address translation layer unit comprises: a thin address translation table of drawing, with the memory page grade of flash memory as the address translation corresponding unit, connect this second subcontrol, to send the instruction of address translation layer to microprocessor by this second subcontrol; The one thick address translation table of drawing, connect and carefully to draw address translation table, should thick draw address translation table with the block grade of flash memory unit as the address translation addressing, data at flash memory write a logical block addresses, can find a main blocks and replacement block by a virtual area block address, and a calculating corresponding virtual block address and a block shift value, it is out-of-date that block displacement paging in main blocks has been write, data are write first blank paging of replacement block, all write fullly when the blank paging of replacement block, slightly draw address translation table and promptly the content of the address logical block addresses pairing with it of legal paging in the replacement block is at that time write carefully in stroke address translation table; One invalid data collector unit connects the thin address translation table of drawing, and collects to provide a thin stroke address translation table to be used for invalid data; One system's initial cell connects this second subcontrol, to obtain original state by this second subcontrol from microprocessor, so that the initial setting that can adjust address translation layer unit to be provided.
Aforesaid flash memory address translation layer system, the virtual area block address value of wherein slightly drawing address translation table is the number of pages of logical block addresses divided by flash memory block.
Aforesaid flash memory address translation layer system, the block shift value of wherein slightly drawing address translation table are the remainder of logical block addresses divided by the number of pages of flash memory block.
Aforesaid flash memory address translation layer system, wherein fast instruction fetch and data buffer are a random access memory.
The invention has the beneficial effects as follows, it proposes the address translation adjusted a layer unit with thick division and thin division and adjusts and provide flash memory physical address and logical place to change the location data, to reduce capacity and the number of times that invalid data is collected, and the mechanism of getting soon with space efficiency promotes and accelerates the efficient that logical address corresponds to the address of real flash memory, can significantly reduce the number of times that the invalid data of flash memory collects and take capacity, the mechanism of getting soon with space efficiency promotes and accelerates the efficient that logical address corresponds to the address of real flash memory.
Description of drawings
The present invention is further described below in conjunction with drawings and Examples.
Fig. 1 is existing flash memory address translation layer system Organization Chart.
Fig. 2 is that existing flash memory address translation layer system is finished the synoptic diagram that invalid data is collected operation.
Fig. 3 is the square circuit diagram of flash memory address translation layer system of the present invention.
Fig. 4 is the detailed block diagram of the address translation the adjusted layer unit in the flash memory address translation layer system of the present invention.
Fig. 5 is the first action synoptic diagram of the address translation the adjusted layer unit operations in the flash memory address translation layer system of the present invention.
Fig. 6 is the second action synoptic diagram of the address translation the adjusted layer unit operations in the flash memory address translation layer system of the present invention.
Fig. 7 is that flash memory address of the present invention changes the operational instances figure in the layer system.
The number in the figure explanation:
100 flash memory address translation layer systems, 10 Instruction Registers
20 logical address cache devices, 30 data buffers
40 subcontrols, 50 subcontrols
60 microprocessors, 70 address conversioning units
80 flash memory address buffers 90 can be adjusted address translation layer unit
The 91 thin address translation table 92 thick address translation tables of drawing of drawing
921 main blocks, 922 replacement blocks
93 invalid data collector units, 94 system's initial cell
95 fast instruction fetch and data buffer 200 flash memories
210 memory block
300 memory read-write controller LBA logical block addresses
N number of pages VBA virtual area block address
BO block displacement A stores paging
B storage paging C storage paging
D storage paging E storage paging
RPBA replacement block address X flash memory
X1 main blocks X2 replacement block
X10～X17 memory page X20～X27 memory page
N logical block addresses quantity b block number of pages
A1 logical block addresses b1 logical block addresses
C1 logical block addresses d1 logical block addresses
E1 logical block addresses PPBA main blocks address
CGT slightly draws the table of comparisons
Embodiment
At first see also shown in Figure 3, flash memory address translation layer system 100 of the present invention, be 300 of connection one flash memory 200 and memory read-write controllers, this memory read-write controller 300 is existing flash memory card reader or personal computer card reading interface, wherein, this flash memory address translation layer system 100 comprises an Instruction Register 10, logical address cache device 20, data buffer 30, a pair of subcontrol 40 and 50, microprocessor 60, address conversioning unit 70, flash memory address buffer 80, can adjust address translation layer unit 90 and fast instruction fetch and data buffer 95, this Instruction Register 10 connects these memory read-write controllers 300, with the instruction that receives flash memory 200 reading and writing datas that this memory read-write controller 300 sends and buffer memory it.
Above-mentioned logical address cache device 20 connects memory read-write controllers 300, with receive from the logical address data of the reading and writing data of this memory read-write controller 300 and buffer memory it.
Above-mentioned data buffer 30 is connected in 300 of flash memory 200 and memory read-write controllers, with as flash memory 200 and 300 buffers that read and write data of memory read-write controller.
Above-mentioned a pair of subcontrol 40 and 50 provides the instruction subsidiary function of data read-write control, wherein a subcontrol 40 connects logical address cache device 20, data buffer 30, so that this logical address cache device 20, data buffer 30 are assisted control.
Above-mentioned microprocessor 60 link order buffers 10, subcontrol 40 and subcontrol 50, this microprocessor 60 is for flash memory 200 data read-write control and change the maincenter that the location is got the control execution soon.
Above-mentioned address conversioning unit 70 connects microprocessor 60, the logical address and the physical address that store flash memory 200 reading and writing datas in this address conversioning unit 70 in advance change the location data, change the location data with logical address and the physical address that required flash memory 200 reading and writing datas of microprocessor 60 are provided, the form of this address conversioning unit 70 is not limit, and is to be example with random access memory (RAM) in the present invention.
Above-mentioned flash memory address buffer 80 connects 200 of these subcontrols 50, address conversioning unit 70 and flash memories, with the physical address data of this flash memory 200 of buffer memory when the reading and writing data.
Please again three read shown in Figure 4, the above-mentioned address translation layer unit 90 of adjusting connects a subcontrol 50, by this subcontrol 50 instruction and the data of address translation layer operation result, the reading and writing data of this flash memory 200 mechanism of getting are soon sent into execution in the microprocessor 60.
This form that can adjust address translation layer unit 90 is not limit, be Figure 2 shows that example in the present invention, wherein, this can be adjusted address translation layer unit 90 and comprise at least one thin stroke of address translation table (Fine-Grained AddrTM) 91, the thick address translation table (Coarse-GrainedAddrTM) 92 of drawing, invalid data collector unit (Garbage Collection Unit) 93 and system's initial cell (System Initialization Unit) 94, should carefully draw address translation table 91 and connect subcontrol 50, to send the instruction of address translation layer to microprocessor 60 by subcontrol 50, should thin draw address translation table 91 and be a memory page grade (page-level) with flash memory 200 as the address translation corresponding unit, because be the response mechanism of memory page level, so efficient and space utilization rate in address translation can be relatively good, and when doing the invalid data collection, can select the mode of less capacity and number of times to reclaim data not.
Above-mentioned thick stroke address translation table 92 connects should carefully draw address translation table 91, should thick draw address translation table 92 and be one with the block grade (block-level) of flash memory 200 unit as the address translation addressing, because be the response mechanism of block grade, so the use capacity of flash memory 200 can lack than the thin address translation table 91 of drawing.
Please cooperate above-mentioned thick stroke address translation table 92 shown in Figure 5 to find the logical block addresses LBA of a correspondence by a virtual area block address again, and the real block address of the flash memory that can correspond to 200, as Figure 1 and Figure 2, the calculating of this virtual area block address VBA is the number of pages N with logical block addresses LBA/ flash memory 200 blocks, so find a main blocks 921 and replacement block 922 two flash memory blocks such as (as shown in Figure 5) by virtual area block address VBA, when a logical block addresses LBA is written into, can calculate corresponding virtual block address VBA earlier with a block displacement BO, the calculating of block displacement BO value is logical block addresses LBA% number of pages N, it is the remainder of logical block addresses LBA/ number of pages N, the paging of which block displacement BO in the main blocks 921 that is found by virtual area block address VBA, it is out-of-date which block displacement BO paging in main blocks 921 has been write, then data just are written to first blank paging of replacement block 922, all write when full when the blank paging of replacement block 922, slightly draw address translation table 92 and just thin 91 li of the address translation tables of drawing are write with the content of he pairing logical block addresses LBA in the address of 922 li legal pagings of replacement block at that time.
Therefore, through above-mentioned thin address translation table 91 and thick address translation table 92 operation instructionss of drawing of drawing, these two kinds of thicknesses are divided under the different address translation layer response mechanisms find an equilibrium point, make that thin stroke address translation table 91 and thick advantage of drawing 92 two tables of comparisons of address translation table are brought into play, and shortcoming can reduce.
Above-mentioned invalid data collector unit 93 connects the thin address translation table 91 of drawing, so that carefully draw the collection that address translation table 91 is used for invalid data.
Above-mentioned system's initial cell 94 connects subcontrols 50, to obtain original state by subcontrol 50 from microprocessor, so that the initial setting that can adjust address translation layer unit 90 to be provided.
Above-mentioned fast instruction fetch is connected system's initial cell 94 that this can adjust address translation layer unit 90 with data buffer 95, so that can adjusting address translation layer unit 90, this uses as the instruction and the metadata cache of the reading and writing data of flash memory 200 mechanism of getting soon, the form of this fast instruction fetch and data buffer 95 is not limit, and is to be example with the random access memory in the present invention.
Please consult shown in Figure 6 again, the example of operating for the address translation the adjusted layer unit 90 of flash memory address translation layer system 100 of the present invention, wherein, cooperate shown in Figure 5, at first the storage paged data (A of flash memory 200, RPBA+5), (B, RPBA+7) information is write thin 91 li of the address translation tables of drawing, the storage paging A in main blocks 921 and the replacement block 922 wherein, storage paging B, storage paging C, storage paging D and storage paging E are logical block addresses LBA, this storage paging A, storage paging B is then making-1 at thick that address value of drawing address translation table 92 the insides record replacement block address RPBA originally, representing this block has not been replacement block 922, but become thin partition piece, represent him carefully to be drawn 91 records of address translation table in the reference address information of the inside, when the thin memory headroom of drawing address translation table 91 the insides uses up, can be transformed into thick address translation table 92 the insides, its operational motion such as Fig. 5 of drawing to the thin address translation table 91 the insides address corresponding data useless of a specified duration of drawing, shown in the arrow and dotted line of Fig. 6.
Please cooperate shown in Figure 7 again, operational instances for flash memory address translation layer system 100 of the present invention, wherein, the memory capacity of supposing flash memory 200 is 1GB, each memory block 210 is 32 memory pages, the memory capacity of each memory page is 1KB, so the flash memory 200 of 1GB memory capacity has 32,768 memory block 210, with Fig. 7 is example, when the blank memory page of replacement block address RPBA=2 runs out, at that time this as Fig. 5, the table of comparisons information of the memory page that replacement block 922 the insides shown in Fig. 6 are legal records thin 91 li of the address translation tables of drawing, so storage paged data (A, 2*32+30), storage paged data (B, 2*32+31) just be recorded in thin 91 li of the address translation tables of drawing, and originally thick draw address translation table 92 write data (VBA, PPBA=1, RPBA=2) promptly be revised as (VBA, PPBA=1, RPBA=-1), the role of this original replacement block address RPBA=2 just becomes thin memory block of drawing address translation table 91, and later on as storage paging A, the data of storage paging B are exactly to be placed in the thin memory block of drawing under the address translation table 91, and storage paging A, the table of comparisons information of storage paging B just is responsible for by the thin address translation table 91 of drawing, unless storage paging A, the mode of answering of storage paging B is displaced to thick drawing in the address translation table 92, and relevant operating process is all shown in the direction of arrow among Fig. 7.
The above-mentioned Fig. 3 extremely advantage of flash memory address translation layer system 100 of the present invention shown in Figure 7 can be summarized as follows:
1, when the blank memory page of replacement block 922 the insides has all been write, can't do main blocks 921 with replacement block 922 action of recovery at once, be earlier the information of effective memory page address translation of replacement block 922 the insides to be write thin 91 li of the address translation tables of drawing on the contrary, therefore can reduce the number of times of the memory block 210 that reclaims flash memory 200 and reduce the capacity of invalid data collection.
2, because can not reclaim main blocks 921 at once with replacement block 922, thus may also have blank memory page to be used in main blocks 921 the insides, and improve the utilization rate of flash memory 200 memory headrooms.
3, because the address translation of effective memory page of 922 li of replacement blocks and table of comparisons information are write thin 91 li of the address translation tables of drawing, when these effective memory pages need be read, can be very fast find their address corresponding informances at the thin address translation table 91 of drawing, therefore can accelerate the efficient of address translation.
4, when the information of the address translation of effective memory page of 922 li of replacement blocks and the table of comparisons being write thin 91 li of the address translation tables of drawing, for the storage paging of the flash memory 200 that will look for if when main blocks 921 the insides, then the efficient of address translation also can increase, for example, the value of replacement block address RPBA as shown in Figure 7 is-1 o'clock, seeks in the replacement block 922 of then need not taking time.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, every foundation technical spirit of the present invention all still belongs in the scope of technical solution of the present invention any simple modification, equivalent variations and modification that above embodiment did.
Claims (6)
1. a flash memory address translation layer system is characterized in that, is connected between a flash memory and the memory read-write controller, and its structure comprises:
One Instruction Register connects this memory read-write controller, with the instruction that receives the flash data read-write that this memory read-write controller sends and buffer memory it;
One logical address cache device connects the memory read-write controller, with receive from the logical address data of the reading and writing data of this memory read-write controller and buffer memory it;
One data buffer is connected between flash memory and memory read-write controller, with as the buffer that reads and writes data between flash memory and memory read-write controller;
One first subcontrol and one second subcontrol, the instruction subsidiary function of data read-write control is provided, wherein this first subcontrol connects logical address cache device, data buffer, so that the auxiliary control of this logical address cache device, data buffer to be provided;
One microprocessor, link order buffer, two subcontrols, this microprocessor are flash data read-write control and change the location and get the maincenter that control is carried out soon;
One address conversioning unit connects microprocessor, and the logical address and the physical address that store the flash data read-write in this address conversioning unit in advance change the location data, changes the location data with logical address and the physical address that the required flash data read-write of microprocessor is provided;
One flash memory address buffer connects between this second subcontrol, address conversioning unit and flash memory, with the physical address data of this flash memory of buffer memory when the reading and writing data;
One can adjust address translation layer unit, connect this second subcontrol, thin contrast and thick two kinds of address translation features of contrast of drawing drawn are provided, carry out the instruction of address translation layer operation result, the reading and writing data of this flash memory mechanism of getting soon and data are sent in the microprocessor by this second subcontrol;
One fast instruction fetch and data buffer connects this and can adjust address translation layer unit, can adjust instruction and the metadata cache of address translation layer unit as the reading and writing data of the flash memory mechanism of getting soon so that this to be provided.
2. flash memory address translation layer system according to claim 1 is characterized in that described address conversioning unit is a random access memory.
3. flash memory address translation layer system according to claim 1 is characterized in that the described address translation layer unit of adjusting comprises:
The one thin address translation table of drawing as the address translation corresponding unit, connects this second subcontrol, to send the instruction of address translation layer to microprocessor by this second subcontrol with the memory page grade of flash memory;
The one thick address translation table of drawing, connect and carefully to draw address translation table, should thick draw address translation table with the block grade of flash memory unit as the address translation addressing, data at flash memory write a logical block addresses, can find a main blocks and replacement block by a virtual area block address, and a calculating corresponding virtual block address and a block shift value, it is out-of-date that block displacement paging in main blocks has been write, data are write first blank paging of replacement block, all write fullly when the blank paging of replacement block, slightly draw address translation table and promptly the content of the address logical block addresses pairing with it of legal paging in the replacement block is at that time write carefully in stroke address translation table;
One invalid data collector unit connects the thin address translation table of drawing, and collects to provide a thin stroke address translation table to be used for invalid data;
One system's initial cell connects this second subcontrol, to obtain original state by this second subcontrol from microprocessor, so that the initial setting that can adjust address translation layer unit to be provided.
4. flash memory address translation layer system according to claim 3, the virtual area block address value that it is characterized in that described thick stroke of address translation table is the number of pages of logical block addresses divided by flash memory block.
5. flash memory address translation layer system according to claim 3, the block shift value that it is characterized in that described thick stroke of address translation table are the remainder of logical block addresses divided by the number of pages of flash memory block.
6. flash memory address translation layer system according to claim 1 is characterized in that described fast instruction fetch and data buffer are a random access memory.
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| CN101751338B (en) * | 2008-12-15 | 2012-03-07 | 中芯国际集成电路制造(上海)有限公司 | Data access control device and data access method |
| CN104156178A (en) * | 2014-08-11 | 2014-11-19 | 四川九成信息技术有限公司 | Data access method for embedded terminal |
| CN104636285B (en) * | 2015-02-03 | 2016-03-23 | 北京麓柏科技有限公司 | A kind of flash-memory storage system and read-write thereof, delet method |
| US20220004856A1 (en) * | 2018-11-06 | 2022-01-06 | Genesys Logic, Inc. | Multichip system and data processing method adapted to the same for implementing neural network application |
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| CN1180349C (en) * | 1999-10-14 | 2004-12-15 | 三星电子株式会社 | Quick flashing decument system |
| US20040186946A1 (en) * | 2003-03-19 | 2004-09-23 | Jinaeon Lee | Flash file system |
| CN2676291Y (en) * | 2004-01-02 | 2005-02-02 | 创惟科技股份有限公司 | Device for increasing access efficiency of flash memory |
| US20060112215A1 (en) * | 2004-11-19 | 2006-05-25 | Samsung Electronics Co., Ltd. | Apparatus and method for processing data of flash memory |
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