CN101290879B - Manufacturing method of gate - Google Patents
Manufacturing method of gate Download PDFInfo
- Publication number
- CN101290879B CN101290879B CN 200710039561 CN200710039561A CN101290879B CN 101290879 B CN101290879 B CN 101290879B CN 200710039561 CN200710039561 CN 200710039561 CN 200710039561 A CN200710039561 A CN 200710039561A CN 101290879 B CN101290879 B CN 101290879B
- Authority
- CN
- China
- Prior art keywords
- layer
- grid
- metal level
- pattern
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
A method for making a grid electrode comprises the following steps that: a semiconductor substrate is provided with a multicrystal silicon layer; a metal layer is formed on the multicrystal silicon layer; visualization of the metal layer is carried out, and a grid electrode pattern is formed inside the metal layer; the multicrystal silicon layer uncovered by the grid electrode pattern is etched; during the etching process, a polymer layer is formed on the sidewall of the multicrystal silicon layer covered by the grid electrode pattern; and the polymer layer is removed to carry out the annealing process of the semiconductor substrate. The sidewall of the grid electrode formed by the method has less surface roughness.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacturing approach of grid.
Background technology
Along with the continuous development of semiconductor fabrication, also more and more littler as the live width of the grid of weighing the semiconductor fabrication technological level; At present, the live width of grid can be accomplished 65nm even littler.The driving voltage of the semiconductor device that little grid live width can reduce to form, and then reduce power consumption; In addition, little grid live width also can make the dimensions of semiconductor devices of formation reduce, and improves integrated level, increases the quantity of unit are semiconductor-on-insulator device, reduces cost.
Fig. 1 to 3 is the generalized section of each step corresponding construction of manufacturing approach of existing a kind of grid.As shown in Figure 1; On Semiconductor substrate 10, form oxide layer 12, on said oxide layer 12, form polysilicon layer 14, on said polysilicon layer 14, form hard mask layer 16; Said hard mask layer 16 is a silicon nitride, on said hard mask layer 16, forms the photoresist pattern 18 of grid.
As shown in Figure 2, etching by the hard mask layer 16 of photoresist pattern 18 protections of said grid, is not transferred to the photoresist pattern 18 of said grid on the said hard mask layer 16, forms the hard mask pattern 16a of grid.
As shown in Figure 3, remove said photoresist pattern 18, be the mask protection layer with said hard mask pattern 16a, the said polysilicon layer 14 of etching forms grid 14a, and further etching is removed the grid oxic horizon 12 that is not covered by said grid 14a.
In the manufacturing approach of above-mentioned grid; General using plasma dry etching in the step of the said polysilicon layer 14 formation grid 14a of etching; Said dry etching can cause gate lateral wall surface comparatively coarse (roughness); This coarse surface can cause that the semiconductor device creepage of formation increases stability decreases.
Publication number is the manufacturing approach that the one Chinese patent application file of CN1632921A discloses other a kind of grid, and this method forms the less grid of live width through subduing technology.Fig. 4 to 7 is the generalized section of said each step corresponding construction of one Chinese patent application file disclosed method.
As shown in Figure 4, Semiconductor substrate 7 is provided, on said Semiconductor substrate 7, form gate oxide 6, on said gate oxide 6, form grid layer 5, said grid layer 5 can be a polysilicon; Deposition hard mask layer 4 on said grid layer 5, said hard mask layer 4 is a kind of in silicon nitride or the silica.Spin coating anti-reflecting layer and photoresist layer on said hard mask layer 4, and through the exposure and the formation mask 1 (being the photoresist pattern of grid) that develops; Make the live width of said mask 1 reduce through isotropic etching, form mask 2a.
As shown in Figure 5, through anisotropic etching with the design transfer of said mask 2a to said hard mask layer 4, form hard mask pattern 4b.
As shown in Figure 6, make hard mask pattern 4b live width reduce through isotropic etching, form hard mask pattern 4a.
As shown in Figure 7, remove said mask 2a, be the mask barrier layer with said hard mask pattern 4a, the said grid layer 5 of etching forms grid 5a, removes said hard mask pattern 4a then.
In the manufacturing approach of the grid of said one Chinese patent application file; Can form the less grid of live width through subduing technology; Yet the said grid layer of etching 5 forms that the technology of grid 5a is general to adopt anisotropic plasma dry etching, so that the grid 5a side wall profile that forms is as much as possible perpendicular to the surface of said Semiconductor substrate 7; But said plasma dry etching makes that also said gate lateral wall surface is comparatively coarse, and coarse surface can cause that the semiconductor device creepage of formation increases; Particularly for the less semiconductor device of grid live width, its leakage current is more responsive to the degree of roughness of gate surface.Thereby in the manufacturing process of grid in less live width (for example 65nm even lower) development, also need the degree of roughness of suppressor grid sidewall surfaces.
Summary of the invention
The present invention provides a kind of manufacturing approach of grid, and the sidewall surfaces degree of roughness of the grid that this method forms is less.
The manufacturing approach of a kind of grid provided by the invention comprises:
Semiconductor substrate is provided, on said Semiconductor substrate, has polysilicon layer;
On said polysilicon layer, form metal level;
Graphical said metal level forms gate pattern in said metal level;
The polysilicon layer that etching is not covered by said gate pattern, in said etching process, the polysilicon layer sidewall that covers at said gate pattern forms polymeric layer;
Remove said polymeric layer, said Semiconductor substrate is carried out annealing process.
Optional, said metal level material comprises a kind of in aluminium, tantalum, molybdenum, zirconium, hafnium, titanium, vanadium, cobalt, palladium, nickel, rhenium, ruthenium, the platinum at least.
Optional, the method that forms said metal level is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), sputter, the plating.
Optional, graphical said metal level, the step that in said metal level, forms gate pattern comprises:
Spin coating photoresist layer on said metal level;
Graphical said photoresist layer forms the photoresist pattern of grid;
Etching is removed not by the metal level of said photoresist pattern covers, and said photoresist design transfer in said metal level, is formed gate pattern;
Remove said photoresist pattern.
Optional, this method further comprises: before the spin coating photoresist layer, on said metal level, form anti-reflecting layer earlier, and after removing said photoresist pattern, remove said anti-reflecting layer.
Optional, graphical said metal level, the step that in said metal level, forms gate pattern comprises:
Spin coating photoresist layer on said metal level;
Graphical said photoresist layer forms the first photoresist pattern;
The said first photoresist pattern of etching reduces its live width, forms the second photoresist pattern;
Etching is removed not by the metal level of the said second photoresist pattern covers, and the said second photoresist design transfer in said metal level, is formed the first metal mask pattern;
The said first metal mask pattern of etching reduces its live width, forms gate pattern;
Remove the said second photoresist pattern.
Optional, this method further comprises: before the said photoresist layer of spin coating, on said metal level, form anti-reflecting layer earlier, and after removing the said second photoresist pattern, remove said anti-reflecting layer.
Optional, said etching is the plasma dry etching, the gas that produces said plasma comprises fluorine-containing G&O.
Optional, the method for removing said polymeric layer is a wet etching.
Optional, the said rapid thermal annealing that is annealed into.
The present invention also provides a kind of manufacturing approach of grid, comprising:
Semiconductor substrate with first area and second area is provided, and said first area is used to form nmos device, and said second area is used to form the PMOS device; On said Semiconductor substrate, has polysilicon layer;
On the polysilicon layer of said first area, form the first metal layer, on the polysilicon layer of said second area, form second metal level;
Graphical said the first metal layer forms the first grid pattern in said the first metal layer; Graphical said second metal level forms the second grid pattern in said second metal level;
Etching in said etching process, forms polymeric layer at the polysilicon layer sidewall of said first grid pattern covers and the polysilicon layer sidewall of second grid pattern covers not by the polysilicon layer of said first grid pattern and second grid pattern covers;
Remove said polymeric layer, said Semiconductor substrate is carried out annealing process.
Optional, the said the first metal layer and the second metal level material are identical or different.
Optional, the material of said the first metal layer comprises a kind of in aluminium, tantalum, molybdenum, zirconium, hafnium, the titanium at least; The said second metal level material comprises a kind of in vanadium, cobalt, palladium, nickel, rhenium, ruthenium, the platinum at least.
Optional, said etching is the plasma dry etching, the gas that produces plasma comprises fluorine-containing G&O.
Compared with prior art, the present invention has the following advantages:
Through on polysilicon layer, forming metal level as hard mask layer; And in etching process, forming polymeric layer at the polysilicon gate sidewall that forms, the sidewall of protection polysilicon gate is unaffected, makes that the sidewall of polysilicon gate is comparatively smooth; Degree of roughness reduces; Help to strengthen the sensitivity that grid opens and closes conducting channel, the leakage current of the semiconductor device that reduces to form, the stability of raising semiconductor device.
In addition; Said metal level is also as the material that forms metal silicide; After forming polysilicon gate, form metal silicide layer through annealing, this metal silicide layer and polysilicon gate form the lower grid of resistivity jointly, can reduce the power consumption of the semiconductor device of formation; And simplified technology, reduced cost.
Through the hard mask of the formation the first metal layer and second metal level conduct on polysilicon layer, and when etching forms grid, form polymeric layer, the NMOS of formation and the gate lateral wall surface roughness of PMOS are reduced at sidewall, comparatively level and smooth; On the other hand, the said the first metal layer and second metal level also are respectively applied for the metal silicide that forms NMOS and PMOS grid, reduce the resistivity of grid.
In addition, the first metal layer can be different with the second metal level material, thereby can form the work function grid different with threshold voltage simultaneously, simplified processing step, reduced cost.
Description of drawings
Fig. 1 to Fig. 3 is the generalized section of each step corresponding construction of the manufacturing approach of a kind of grid in the prior art;
Fig. 4 to Fig. 7 is the generalized section of each step corresponding construction of the manufacturing approach of other a kind of grid in the prior art;
Fig. 8 is the flow chart of first embodiment of the manufacturing approach of grid of the present invention;
Fig. 9 to Figure 20 is the generalized section of each step corresponding construction of first embodiment of the manufacturing approach of grid of the present invention;
Figure 21 is the flow chart of second embodiment of the manufacturing approach of grid of the present invention;
Figure 22 to Figure 29 is the generalized section of each step corresponding construction of second embodiment of the manufacturing approach of grid of the present invention.
Embodiment
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Fig. 8 is the flow chart of first embodiment of the manufacturing approach of grid of the present invention.
Flow chart as shown in Figure 8, step S100 provides Semiconductor substrate, on said Semiconductor substrate, has polysilicon layer.
Generalized section as shown in Figure 9; Semiconductor substrate 20 is provided; Said Semiconductor substrate 20 materials can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon; The material of said Semiconductor substrate 20 also can be a silicon Germanium compound, and said Semiconductor substrate 20 can also be (Silicon On Insulator, SOI) epitaxial layer structure on structure or the silicon of silicon on the insulating barrier.In said Semiconductor substrate 20, can mix N type impurity or p type impurity and form N trap or P trap.
Generalized section shown in figure 10 forms gate dielectric layer 22 on said Semiconductor substrate 20.Said gate dielectric layer 22 is a kind of or combination in silica, the silicon oxynitride.The method that forms silica is that high temperature furnace pipe oxidation, rapid thermal annealing oxidation or original position steam produce oxidation (In-Situ Stream Generation; ISSG) a kind of in; Silica is carried out nitrogen treatment can form silicon oxynitride, said nitrogenize can be a kind of in high temperature furnace pipe nitrogenize, rapid thermal annealing nitrogenize or the pecvd nitride.
On said gate dielectric layer 22, form polysilicon layer 24.The method that forms said polysilicon layer 24 is physical vapour deposition (PVD) or chemical vapour deposition (CVD).In said polysilicon layer 24, can be mixed with impurity, with the resistivity of the grid that reduces to form.For example, can mix phosphorus or arsenic, in being used as the polysilicon layer of P-type mos transistor gate, can mix the compound of boron or boron as in the polysilicon layer of N type metal oxide semiconductor transistor gate.
Step S110, flow chart as shown in Figure 8 forms metal level on said polysilicon layer.
Generalized section shown in figure 11 forms metal level 26 on said polysilicon layer 24.The method that forms said metal level 26 is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), sputter, the plating.Said metal level 26 materials comprise a kind of in aluminium, tantalum, molybdenum, zirconium, hafnium, titanium, vanadium, cobalt, palladium, nickel, rhenium, ruthenium, the platinum at least.Said metal level 26 is used to form the hard mask layer of the said polysilicon layer 24 of subsequent etching, reduces the degree of roughness of the gate lateral wall of follow-up formation.In addition, this metal level 26 also is used for and polysilicon reaction formation metal silicide, reduces the resistivity of the grid that forms.
Step S120, flow chart as shown in Figure 8, graphical said metal level forms gate pattern in said metal level.
Among the embodiment therein, the step that forms said gate pattern is following:
Generalized section shown in figure 12, spin coating photoresist layer on said metal level 26 is through the photoresist pattern 27 of the graphical said photoresist layer formation grid of exposure imaging technology;
Then, shown in figure 13, remove the metal level 26 that is not covered through etching by said photoresist pattern 27, said photoresist pattern 27 is transferred in the said metal level 26, form gate pattern 26a;
Then remove said photoresist pattern 27.Among the embodiment therein, the method for removing said photoresist pattern 27 is the oxygen gas plasma etching.
In a further embodiment, before the said photoresist layer of spin coating, on said metal level 26, form the anti-reflecting layer (not shown) earlier, said anti-reflecting layer is an organic substance, and its formation method is a spin-coating method; And then on said anti-reflecting layer the spin coating photoresist layer; And after removing said photoresist pattern 27, remove said anti-reflecting layer.Said anti-reflecting layer is used to eliminate or reduces in the influence to said photoresist pattern 27 side wall profile of the reverberation on 26 surfaces of metal level described in the exposure technology.
Among the embodiment therein, the step that forms said gate pattern is following:
Generalized section shown in figure 14, spin coating photoresist layer on said metal level 26 forms the first photoresist pattern 27a through the graphical said photoresist layer of exposure imaging technology;
Then, shown in figure 15, through wet etching the said first photoresist pattern 27a live width is reduced, form the second photoresist pattern 27b;
Then, shown in figure 16, remove the metal level 26 that is not covered through etching by the said second photoresist pattern 27b, the said second photoresist pattern 27b is transferred in the said metal level 26, form the first metal mask pattern 26b;
Shown in figure 17, through the said first metal mask pattern 26b of wet etching, its live width is reduced, form gate pattern 26c.
Then remove the said second photoresist pattern 27b, the method for removing the said second photoresist pattern 27b among the embodiment therein is the oxygen gas plasma etching;
Form the less gate pattern 26c of live width through two step wet etchings; Broken through the restriction of photoetching process intermediate-resolution, can form live width, therefore less than photoetching resolution; Gate pattern 26c with this metal material is the mask barrier layer, and etch polysilicon layer 24 can form the less grid of live width.
In a further embodiment, before the said photoresist layer of spin coating, on said metal level 26, form the anti-reflecting layer (not shown) earlier, said anti-reflecting layer is an organic substance, and its formation method is a spin-coating method; And then on said anti-reflecting layer the spin coating photoresist layer; And after removing the said second photoresist pattern 27b, remove said anti-reflecting layer.Said anti-reflecting layer is used to eliminate or reduces in the influence to the said first photoresist pattern 27a side wall profile of the reverberation on 26 surfaces of metal level described in the exposure technology.
Step S130, flow chart as shown in Figure 8, the polysilicon layer that etching is not covered by said gate pattern, in said etching process, the polysilicon layer sidewall that covers at said gate pattern forms polymeric layer.
Among the embodiment therein, generalized section shown in figure 18, with the mask barrier layer of said gate pattern 26a as etching, etching is removed the polysilicon layer 24 that is not covered by said gate pattern 26a, forms polysilicon gate 24a; And further the said gate dielectric layer 22 of etching when expose on the surface of said Semiconductor substrate 20 till.
Among the embodiment therein, said etching is a dry plasma etch, and the etching gas of said plasma dry etching is the G&O that contains fluorine gas.Said fluorine-containing gas can be CF
4, SF
6, C
2F
6Or NF
3
In the said polysilicon layer 24 of etching, the polymer that produces in the plasma etch process forms polymeric layer 23 attached to the sidewall of polysilicon gate 24a; Said polymer 23 parts are that oxygen and said metal level 26 materials in the plasma are reacted the oxide that generates, and part is that the substance reaction of fluorine and carbon containing generates compound.The sidewall surfaces of the said polysilicon gate 24a of these polymeric layer 23 protections is avoided the etching or the corrosion of plasma in etching process; Reduce the damage of plasma etching to said sidewall lattice; Help to make the surface roughness of said sidewall to reduce, also promptly help to make said sidewall more smooth.
Step S140, flow chart as shown in Figure 8 is removed said polymeric layer, and said Semiconductor substrate is carried out annealing process.
Generalized section shown in figure 19 is removed said polymer 23, forms the polysilicon gate 24a that the top has gate pattern 26a.
Among the embodiment therein, the method for removing said polymer 23 is a wet etching, and the etchant solution of said wet etching is phosphoric acid or hydrofluoric acid.
Generalized section shown in figure 20 after the technology of said polymeric layer 23 is removed in completion, is carried out annealing processs to said Semiconductor substrate 20 with polysilicon gate 24a; Make the polysilicon reaction at part metals and said polysilicon gate 24a top among the said gate pattern 26a generate metal silicide layer 24b through annealing process; This metal silicide layer 24b and said polysilicon gate 24a form the grid of semiconductor device jointly, can reduce resistivity.The remaining metal material of said gate pattern 26a can be removed through the method for wet etching.
Among the embodiment therein, the said rapid thermal annealing that is annealed into; The temperature of said annealing can be to be 600 to 1200 degree.
Through on said polysilicon layer 24, forming metal level 26 as hard mask layer; And the sidewall at said polysilicon gate 24a forms polymeric layer 23 in etching process, protects the sidewall of said polysilicon gate 24a unaffected, makes that the sidewall of said polysilicon gate is comparatively smooth; Degree of roughness reduces; Help to strengthen the sensitivity that grid opens and closes conducting channel, the leakage current of the semiconductor device that reduces to form, the stability of raising device.
In addition; Said metal level 26 is also as the material that forms metal silicide; After forming polysilicon gate 24a, form metal silicide layer 24b through annealing; This metal silicide layer 24b and polysilicon gate 24a form the lower grid of resistivity jointly, can reduce the power consumption of the semiconductor device of formation; And simplified technology, reduced cost.
Figure 21 is the flow chart of second embodiment of the manufacturing approach of grid of the present invention.
Shown in figure 21, step S200 provides the Semiconductor substrate with first area and second area, and said first area is used to form nmos device, and said second area is used to form the PMOS device; On said Semiconductor substrate, has polysilicon layer.
Generalized section shown in figure 22 provides Semiconductor substrate 40, and said Semiconductor substrate 40 has first area 40a and second area 40b, and said first area 40a is used to form nmos device, and said second area 40b is used to form the PMOS device.
Said Semiconductor substrate 40 materials can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon; The material of said Semiconductor substrate 40 also can be a silicon Germanium compound; Said Semiconductor substrate 40 can also be (Silicon On Insulator, SOI) epitaxial layer structure on structure or the silicon of silicon on the insulating barrier.
On said Semiconductor substrate 40, be formed with gate dielectric layer 42.Said gate dielectric layer 42 is a kind of or combination in silica, the silicon oxynitride.The method that forms silica is that high temperature furnace pipe oxidation, rapid thermal annealing oxidation or original position steam produce oxidation (In-Situ Stream Generation, a kind of in ISSG); Silica is carried out nitrogen treatment can form silicon oxynitride; Said nitrogenize can be a kind of in high temperature furnace pipe nitrogenize, rapid thermal annealing nitrogenize and the pecvd nitride.
On said gate dielectric layer 42, be formed with polysilicon layer 44, said polysilicon layer 44 covers said first area 40a and second area 40b at least.The method that forms said polysilicon layer 44 is physical vapour deposition (PVD) or chemical vapour deposition (CVD).
Step S210 forms the first metal layer on the polysilicon layer of said first area, on the polysilicon layer of said second area, form second metal level.
The material of the said the first metal layer and second metal level can be identical or different.
Generalized section shown in figure 23 forms metal level 46a on said polysilicon layer 44, the method that forms said metal level 46a is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), sputter, the plating.Said metal level 46a is used to form the hard mask layer of NMOS grid on the one hand; Be used on the other hand and polysilicon reaction generates metal silicide, this metal silicide can be as the part of NMOS grid, reducing the resistivity of grid, and reduces the work function of grid; Said metal level 46a should select the material of the work function that can reduce the NMOS grid for use; Among the embodiment therein, the material of said metal level 46a comprises a kind of in aluminium, tantalum, molybdenum, zirconium, hafnium, the titanium at least.
Spin coating photoresist layer on said metal level 46a is removed the photoresist layer of said second area 40b top through exposure imaging, forms photoresist figure 47 shown in figure 24; As etching barrier layer, remove the metal level 46a that is covered with said photoresist figure 47, form the first metal layer 46c, remove said photoresist figure 47 by said photoresist figure 47.
Adopt with the same method of formation the first metal layer 46c and form the second metal level 46d shown in figure 25.The said second metal level 46d selects the material of the work function that can reduce the PMOS grid for use; Among the embodiment therein, the material of the said second metal level 46d comprises a kind of in vanadium, cobalt, palladium, nickel, rhenium, ruthenium, the platinum at least.
Step S220, flow chart shown in figure 21, graphical said the first metal layer forms the first grid pattern in said the first metal layer; Graphical said second metal level forms the second grid pattern in said second metal level.
Generalized section shown in figure 26 forms first grid pattern 46e and second grid pattern 46f through chemical wet etching technology.
Among the embodiment therein, the step that forms said first grid pattern 46e and second grid pattern 46f is following:
Spin coating photoresist layer (not shown) on the said the first metal layer 46c and the second metal level 46d; Form the first photoresist figure and the second photoresist figure of grid through the graphical said photoresist layer of exposure imaging technology; The wherein said first photoresist figure is positioned at said first area 40a top, and the said second photoresist figure is positioned at the top of said second area 40b;
Then, remove the first metal layer 46c that is not covered, the said first photoresist figure transfer in said the first metal layer 46c, is formed first grid pattern 46e by the said first photoresist figure through etching; And remove the second metal level 46d that is not covered through etching simultaneously by the said second photoresist figure, the said second photoresist figure transfer in the said second metal level 46d, is formed second grid pattern 46f;
Then, remove the said first photoresist figure and the second photoresist figure; The method of removing the said first photoresist figure and the second photoresist figure among the embodiment therein is the oxygen gas plasma etching.
In a further embodiment; Before the said photoresist layer of spin coating, on the said the first metal layer 46c and the second metal level 46d, form the anti-reflecting layer (not shown) earlier, said anti-reflecting layer is an organic substance; Its formation method is a spin-coating method, and then on said anti-reflecting layer the spin coating photoresist layer; And after removing the said first photoresist figure and the second photoresist figure, remove said anti-reflecting layer; Said anti-reflecting layer is used to eliminate or reduces in the influence to the side wall profile of the said first photoresist figure and the second photoresist figure of the reverberation on 46c of the first metal layer described in the exposure technology and second metal level 46d surface.
Step S230; Flow chart shown in figure 21; Etching is not by the polysilicon layer of said first grid pattern and second grid pattern covers; In said etching process, form polymeric layer at the polysilicon layer sidewall of said first grid pattern covers and the polysilicon layer sidewall of second grid pattern covers.
Generalized section shown in figure 27; With said first grid pattern 46e and second grid pattern 46f as etching barrier layer; Etching is removed not by the polysilicon layer 44 of said first grid pattern 46e and second grid pattern 46f covering; Form the first polysilicon gate 44a and the second polysilicon gate 44b, and further the said gate dielectric layer 42 of etching when expose on the surface of said Semiconductor substrate 40 till.
Among the embodiment therein, said etching is a dry plasma etch, and the etching gas of said plasma dry etching is the G&O that contains fluorine gas.Said fluorine-containing gas comprises CF
4, SF
6, C
2F
6Or NF
3
In the said polysilicon layer 44 of etching, the polymer that plasma etching produces forms polymeric layer 43a and 43b attached to the sidewall of the first polysilicon gate 44a and the sidewall of the second polysilicon gate 44b; Said polymer 43a and 43b partly are the oxide that oxygen and said the first metal layer 46c and the reaction of the second metal level 46d material in the plasma generates, and part is the material reacting generating compound of fluorine and carbon containing; This polymeric layer 43a and 43b can protect the sidewall of the first polysilicon gate 44a and the second polysilicon gate 44b sidewall in etching process, to avoid plasma etching or corrosion; Reduce the damage of plasma etching to said sidewall lattice; Help to make the surface roughness of said sidewall to reduce, also promptly help to make said sidewall more smooth.
Step S240, flow chart shown in figure 21 is removed said polymeric layer, and said Semiconductor substrate is carried out annealing process.
Generalized section shown in figure 28 is removed said polymer 43a and 43b, forms the first polysilicon gate 44a that the top has first grid pattern 46e, and the top has the second polycrystalline grid 44b of second grid pattern 46f.
Among the embodiment therein, the method for removing said polymer 43a and 43b is a wet etching, and the etchant solution of said wet etching is phosphoric acid or hydrofluoric acid.
Shown in figure 29, after the technology of said polymeric layer 43a and 43b is removed in completion, said Semiconductor substrate 40 is carried out annealing processs; Make the polysilicon reaction at part metals and the said first polysilicon gate 44a top among the said first grid pattern 46e through annealing process, generate the first metal silicide layer 48a; The polysilicon reaction at part metals among the said second grid pattern 46f and the said second polysilicon gate 44b top generates the second metal silicide layer 48b; The said first metal silicide layer 48a and the first polysilicon layer 44a form the grid of nmos device jointly, and the said second metal silicide layer 48b and the second polysilicon layer 44b form the grid of PMOS device jointly, reduce the resistivity of the grid that forms.Remaining metal material is removed through wet etching among said first grid pattern 46e and the second grid pattern 46f.
Through the hard mask of the formation the first metal layer and second metal level conduct on polysilicon layer, and when etching forms grid, form polymeric layer, the NMOS of formation and the gate lateral wall surface roughness of PMOS are reduced at sidewall, comparatively level and smooth; On the other hand, the said the first metal layer and second metal level also are respectively applied for the metal silicide that forms NMOS and PMOS grid, reduce the resistivity of grid; In addition, said the first metal layer can be different with the second metal level material, thereby can form the work function grid different with threshold voltage simultaneously, simplified processing step, reduced cost.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (14)
1. the manufacturing approach of a grid is characterized in that, comprising:
Semiconductor substrate is provided, on said Semiconductor substrate, has polysilicon layer;
On said polysilicon layer, form metal level;
Graphical said metal level forms gate pattern in said metal level;
The polysilicon layer that etching is not covered by said gate pattern, in said etching process, the polysilicon layer sidewall that covers at said gate pattern forms polymeric layer;
Remove said polymeric layer, said Semiconductor substrate is carried out annealing process.
2. the manufacturing approach of grid as claimed in claim 1 is characterized in that: said metal level material comprises a kind of in aluminium, tantalum, molybdenum, zirconium, hafnium, titanium, vanadium, cobalt, palladium, nickel, rhenium, ruthenium, the platinum at least.
3. the manufacturing approach of grid as claimed in claim 2 is characterized in that: the method that forms said metal level is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), sputter, the plating.
4. the manufacturing approach of grid as claimed in claim 1 is characterized in that, graphical said metal level, and the step that in said metal level, forms gate pattern comprises:
Spin coating photoresist layer on said metal level;
Graphical said photoresist layer forms the photoresist pattern of grid;
Etching is removed not by the metal level of said photoresist pattern covers, and said photoresist design transfer in said metal level, is formed gate pattern;
Remove said photoresist pattern.
5. the manufacturing approach of grid as claimed in claim 4 is characterized in that, this method further comprises: before the spin coating photoresist layer, on said metal level, form anti-reflecting layer earlier, and after removing said photoresist pattern, remove said anti-reflecting layer.
6. the manufacturing approach of grid as claimed in claim 1 is characterized in that, graphical said metal level, and the step that in said metal level, forms gate pattern comprises:
Spin coating photoresist layer on said metal level;
Graphical said photoresist layer forms the first photoresist pattern;
The said first photoresist pattern of etching reduces its live width, forms the second photoresist pattern;
Etching is removed not by the metal level of the said second photoresist pattern covers, and the said second photoresist design transfer in said metal level, is formed the first metal mask pattern;
The said first metal mask pattern of etching reduces its live width, forms gate pattern;
Remove the said second photoresist pattern.
7. the manufacturing approach of grid as claimed in claim 6; It is characterized in that; This method further comprises: before the said photoresist layer of spin coating, on said metal level, form anti-reflecting layer earlier, and after removing the said second photoresist pattern, remove said anti-reflecting layer.
8. the manufacturing approach of grid as claimed in claim 1, it is characterized in that: said etching is the plasma dry etching, the gas that produces said plasma comprises fluorine-containing G&O.
9. the manufacturing approach of grid as claimed in claim 1, it is characterized in that: the method for removing said polymeric layer is a wet etching.
10. the manufacturing approach of grid as claimed in claim 1 is characterized in that: the said rapid thermal annealing that is annealed into.
11. the manufacturing approach of a grid is characterized in that, comprising:
Semiconductor substrate with first area and second area is provided, and said first area is used to form nmos device, and said second area is used to form the PMOS device; On said Semiconductor substrate, has polysilicon layer;
On the polysilicon layer of said first area, form the first metal layer, on the polysilicon layer of said second area, form second metal level;
Graphical said the first metal layer forms the first grid pattern in said the first metal layer; Graphical said second metal level forms the second grid pattern in said second metal level;
Etching in said etching process, forms polymeric layer at the polysilicon layer sidewall of said first grid pattern covers and the polysilicon layer sidewall of second grid pattern covers not by the polysilicon layer of said first grid pattern and second grid pattern covers;
Remove said polymeric layer, said Semiconductor substrate is carried out annealing process.
12. the manufacturing approach of grid as claimed in claim 11 is characterized in that: the said the first metal layer and the second metal level material are identical or different.
13. the manufacturing approach of grid as claimed in claim 11 is characterized in that: the material of said the first metal layer comprises a kind of in aluminium, tantalum, molybdenum, zirconium, hafnium, the titanium at least; The said second metal level material comprises a kind of in vanadium, cobalt, palladium, nickel, rhenium, ruthenium, the platinum at least.
14. the manufacturing approach of grid as claimed in claim 11 is characterized in that: said etching is the plasma dry etching, and the gas that produces plasma comprises fluorine-containing G&O.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710039561 CN101290879B (en) | 2007-04-17 | 2007-04-17 | Manufacturing method of gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710039561 CN101290879B (en) | 2007-04-17 | 2007-04-17 | Manufacturing method of gate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101290879A CN101290879A (en) | 2008-10-22 |
| CN101290879B true CN101290879B (en) | 2012-12-12 |
Family
ID=40035064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710039561 Expired - Fee Related CN101290879B (en) | 2007-04-17 | 2007-04-17 | Manufacturing method of gate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101290879B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270573A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing grid |
| CN102403314B (en) * | 2010-09-08 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | Active area sidewall in bipolar CMOS (Complementary Metal Oxide Semiconductor) process and manufacturing method |
| CN102569073B (en) * | 2010-12-07 | 2014-11-05 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor apparatus |
| CN102891369B (en) * | 2011-05-11 | 2016-05-04 | 深圳光启高等理工研究院 | A kind of super material preparation method and super material based on CMOS technique |
| CN102776566A (en) * | 2011-05-11 | 2012-11-14 | 深圳光启高等理工研究院 | Preparation method of meta-material based on polysilicon, and meta-material based on polysilicon |
| CN102904028B (en) * | 2011-06-01 | 2014-12-24 | 深圳光启高等理工研究院 | Semiconductor based metamaterial preparation method and semiconductor based metamaterial |
| CN104022063B (en) * | 2013-03-01 | 2017-09-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of shallow slot |
| US10190232B2 (en) | 2013-08-06 | 2019-01-29 | Lam Research Corporation | Apparatuses and methods for maintaining pH in nickel electroplating baths |
| US9732434B2 (en) | 2014-04-18 | 2017-08-15 | Lam Research Corporation | Methods and apparatuses for electroplating nickel using sulfur-free nickel anodes |
| CN107678246B (en) * | 2017-09-07 | 2020-10-27 | 武汉华星光电半导体显示技术有限公司 | Exposure method and method for patterning target film layer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6268295B1 (en) * | 1997-11-27 | 2001-07-31 | Fujitsu Limited | Method of manufacturing semiconductor device |
| CN1787194A (en) * | 2004-12-08 | 2006-06-14 | 上海华虹Nec电子有限公司 | Method for mfg. large power MOS tube with small wire wide slot type structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6149473A (en) * | 1984-08-17 | 1986-03-11 | Mitsubishi Electric Corp | Manufacture of polycide gate mos ic |
-
2007
- 2007-04-17 CN CN 200710039561 patent/CN101290879B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6268295B1 (en) * | 1997-11-27 | 2001-07-31 | Fujitsu Limited | Method of manufacturing semiconductor device |
| CN1787194A (en) * | 2004-12-08 | 2006-06-14 | 上海华虹Nec电子有限公司 | Method for mfg. large power MOS tube with small wire wide slot type structure |
Non-Patent Citations (1)
| Title |
|---|
| JP昭61-49473A 1986.03.11 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101290879A (en) | 2008-10-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101290879B (en) | Manufacturing method of gate | |
| KR101716608B1 (en) | Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells | |
| US10886391B2 (en) | Single-electron transistor with wrap-around gate | |
| US7439138B2 (en) | Method of forming integrated circuitry | |
| CN101667541B (en) | Method for making metal gate stacks of a semiconductor device | |
| JP2007335891A (en) | Semiconductor device | |
| CN103779207A (en) | Method of forming a semiconductor structure including a wet etch process for removing silicon nitride | |
| WO2009012053A2 (en) | Isolated tri-gate transistor fabricated on bulk substrate | |
| CN104681498B (en) | Memory device and its manufacture method | |
| EP1298722A2 (en) | Method of forming dual work function gate electrodes in a semiconductor device | |
| CN100576513C (en) | The manufacture method of semiconductor device | |
| CN101364537A (en) | Manufacturing method for grid and semiconductor device, construction for manufacturing grid | |
| US6524938B1 (en) | Method for gate formation with improved spacer profile control | |
| CN101211783B (en) | Method for forming metal pattern in semiconductor device | |
| CN107579108B (en) | Method for forming semiconductor structure | |
| JP2007305892A (en) | Method of etching metal film, and method of manufacturing semiconductor device | |
| CN103839792B (en) | Method, semi-conductor device manufacturing method | |
| CN102969234B (en) | Method for manufacturing metal gate electrode | |
| JP2002289554A (en) | Semiconductor device and production method therefor | |
| US7544595B2 (en) | Forming a semiconductor device having a metal electrode and structure thereof | |
| TW466692B (en) | A method of manufacturing a semiconductor device | |
| US20050164460A1 (en) | Salicide process for metal gate CMOS devices | |
| JP2005123276A (en) | Semiconductor device and its manufacturing method | |
| CN104900522A (en) | MOS transistor manufacturing method and semiconductor device manufacturing method | |
| CN102779789B (en) | Manufacturing method of semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121116 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20121116 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121212 Termination date: 20190417 |