CN101297392B - 经硅化物化的内嵌硅 - Google Patents

经硅化物化的内嵌硅 Download PDF

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CN101297392B
CN101297392B CN2006800394948A CN200680039494A CN101297392B CN 101297392 B CN101297392 B CN 101297392B CN 2006800394948 A CN2006800394948 A CN 2006800394948A CN 200680039494 A CN200680039494 A CN 200680039494A CN 101297392 B CN101297392 B CN 101297392B
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哈桑·内贾德
托马斯·A·菲古拉
戈登·A·哈勒
拉维·耶尔
约翰·马克·梅尔德里姆
贾斯廷·哈尼什
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Micron Technology Inc
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Abstract

本发明提供用于使内嵌硅完全硅化物化的方法和结构。将硅(52)提供在沟槽(50)内。在硅(52)上提供金属混合物(55)，其中所述金属中的一者在硅中比硅在所述金属中更容易扩散，且所述金属中的另一者在硅中不如硅在所述金属中容易扩散。示范性混合物包含80％的镍和20％的钴。尽管所述沟槽(50)的纵横比相对较高，但允许沟槽(50)内的硅(52)完全成为硅化物(56)，而不形成空隙。除其它装置以外，可通过所述方法形成用于存储器阵列(10)的内嵌存取装置(RAD)。

Description

经硅化物化的内嵌硅 
技术领域
本发明大体上涉及硅化物化反应及其产物，且更明确地说，涉及凹座内硅的完全硅化物化。 
背景技术
集成电路设计在不断地按比例缩小以降低功率消耗且增加速度。随着每次更新换代，装置倾向于变得更小且更密集封装，从而产生多种关于集成的问题。集成问题之一是提供给导电元件的体积较小。为了实现可接受的电路速度，重要的是此类元件具备极高的传导率。 
其它问题与加衬或填充高纵横比沟槽或通孔的困难有关。举例来说，细长的沟槽是用于波纹金属化的；隔离的空穴或通孔是用于形成垂直触点的；衬底上方的堆叠沟槽和衬底内的深沟槽是用于存储器单元电容器的形成的；等等。随着每次更新换代，由于纵横比较高，此类通孔内的沉积变得更具挑战性。在沉积或随后的处理过程期间，可能容易形成空隙，从而导致装置良率较低。 
发明内容
根据本发明的一个方面，提供一种用于在集成电路内形成金属硅化物结构的方法。所述方法包含在部分制成的集成电路内提供凹座。将硅沉积到所述凹座中。将金属混合物沉积在所述凹座上并与硅接触，其中金属混合物包含至少两种相对于硅具有相反扩散性的金属。金属混合物与硅在所述凹座中反应，以在所述凹座内形成金属硅化物。 
根据本发明的另一方面，提供一种用于形成集成电路的内嵌存取装置的方法。所述方法包含在半导体结构中蚀刻沟槽。用介电层对所述沟槽进行加衬，且用硅至少部分地填充所述经加衬的沟槽。使金属层沉积在沟槽上并与硅接触。使沟槽中的硅在硅化物化反应中与金属层完全反应。 
根据本发明的另一方面，提供一种集成电路，其包含金属硅化物结构。金属硅化物无空隙地填充凹座的至少下部。所述金属硅化物包含至少第一金属的混合物，所述第一金属在硅中的扩散性高于硅在所述第一金属中的扩散性。所述金属硅化物还包含第二金属，所述第二金属在硅中的扩散性低于硅在所述第二金属中的扩散性。 
根据本发明的另一方面，提供一种存储器装置。所述装置包含存储器阵列中的内嵌存取装置，其包含位于半导体衬底内的凹座；对所述凹座进行加衬的薄介电层以及无空隙地填充所述沟槽的至少下部的金属硅化物。 
附图说明
从对优选实施例的详细描述内容中且从附图中将更好地理解本发明，附图意在说明而非限制本发明。 
图1是根据本发明优选实施例而布置的存储器装置的平面示意图。 
图2是根据本发明优选实施例，沿线2-2截取的图1的存储器装置的侧截面示意图。 
图3到图7是根据本发明优选实施例的半导体装置的一部分的一系列截面图，其说明与图1和图2的装置类似的DRAM存取晶体管的形成。 
图8是根据本发明一个实施例，在将硅内嵌在沟槽内之后且在沉积用于硅化物化的金属之前，图7的装置的截面示意图。 
图9是根据本发明另一实施例，在使沟槽内的硅平坦化且沉积用于硅化物化的金属之后，图7的装置的截面示意图。 
图10A到图11B是说明在图9的装置上执行硅化物化退火之后，存储器存取装置的经完全硅化物化的内嵌栅极的显微照片。 
图12是展示在将经完全硅化物化的栅极内嵌且掩埋在其沟槽内之后，图10A到11B的部分制成的半导体装置的截面示意图。 
图13到图21是根据本发明另一实施例的半导体装置的一部分的一系列截面图，其说明阵列中(与图1和图2的装置类似的)外围晶体管栅极堆叠与内嵌存取装置的同时形成。 
具体实施方式
虽然结合间距加倍技术说明本发明的优选实施例，但应了解这些优选实施例的电路设计可并入任何集成电路中。具体地说，它们可有利地应用于形成具有电气装置阵列的任何装置，包含逻辑或门阵列，以及易失性或非易失性存储器装置，例如DRAM、RAM或快闪存储器。通过本文所描述的方法形成的集成电路可并入许多较大系统的任何一者中，例如主板、桌上型计算机或膝上型计算机、数字摄像机、个人数字助理或存储器适用的许多装置中的任何一者。 
根据本发明一个实施例布置的一个存储器装置DRAM的设计和运作在图中说明且在下文更详细地描述。 
图1展示存储器装置10的一部分的视图。此示意性布置说明形成存储器装置10的各种电气装置和其它组件。当然，这些组件中的许多组件在纯直观表示中是不可区分的，且人为使图1中所展示的组件中的一些组件与其它组件区分开，以便强调其功能性。存储器装置10构建于衬底11上和衬底11中，所述衬底形成电气装置在其中形成的半导体材料的最低层。衬底11通常包括硅。当然，如所属领域的技术人员众所周知，还可使用其它合适材料(例如其它III-V族元素)。当描述其它组件时，如最佳在图2中可见，参考衬底11的上表面可最容易理解其它组件的深度或高度。 
图1中还展示沿存储器装置10延伸的4条伸长字线12a、12b、12c、12d。在优选实施例中，使用间距加倍技术形成这些字线12。具体地说，优选通过将参考图3到图9更详细论述的方法来形成这些字线12。使用这种技术，所得特征的间距可小于由光刻技术界定的最小间距。举例来说，在一个实施例中，所得特征的间距可等于由光刻技术界定的最小间距的一半。 
一般来说，如所属领域的技术人员所熟知，间距加倍可通过以下步骤序列来执行。首先，可使用光刻在上覆于一层可消耗材料和衬底上的光致抗蚀剂层中形成线图案。这种光刻技术在邻近线之间实现2F的间距，如上文所揭示，所述间距受光刻的光学特征限制。在一个实施例中，F在60nm到100nm的范围内。此范围对于用以界定特征的目前发展水平的光刻技术来说是典型的。在一种光刻系统中，F等于约86nm，而在另一系统中，F等于约78nm。 
如所属领域的技术人员所熟知，通常将由光刻界定的每条线的宽度也定义为F。接着可通过蚀刻步骤(优选为各向异性)来将图案转移到下面的可消耗材料层，从而在下层中形成预留位置或心轴。接着可去除光致抗蚀剂线，且可对心轴进行各向同性蚀刻以增加相邻心轴之间的距离。优选地，相邻心轴之间的距离从F增加到3F/2。或者，可能已经在抗蚀水平下执行了各向同性“收缩”或“修整”蚀刻。接着可将间隔物材料保形层沉积在心轴上。此材料层同时覆盖心轴的水平和垂直表面。因此，通过以定向间隔物蚀刻优先蚀刻来自水平表面的间隔物材料，来在心轴侧面形成间隔物，即从另一材料的侧壁延伸的材料。接着选择性地移除剩余的心轴，只留下间隔物，其可一起充当用于图案化的掩模。因此，在给定间距2F原先包含界定一个特征和一个间隔的图案的位置处，现在同一宽度包含由间隔界定的两个特征和两个间隔。因此，有效地减小了用给定光刻技术可实现的最小特征尺寸。将在下文中参考图3到图9更详细地论述这种间距加倍方法，其可重复以进一步减小特征的尺寸。 
当然，如此项技术中众所周知，收缩/修整蚀刻的程度和经沉积间隔物的厚度可改变以实现多种特征和间距尺寸。在所说明的实施例中，尽管光刻技术可解决2F的间距，但特征(即本实例中的字线12)具有间距F。字线12由约F/2的宽度界定，且邻近字线12a、12b或12c、12d以同一宽度F/2隔开。同时，作为间距加倍技术的副产物，间隔开的字线12b、12c之间的间隔距离为3F/2。在优选实施例中，用绝缘体填充隔离沟槽，且隔离沟槽位于这些字线12b、12c之间的此间隔距离内；然而，在其它实施例中，不需要存在此隔离沟槽。 
对于每一距离3F来说，存在两条字线，从而产生可被称为3F/2有效间距的间距。更一般来说，字线优选具有1.25F与1.9F之间的有效间距。当然，用以界定字线的特定间距只是实例。在其它实施例中，可通过更常规的技术来制造字线，且不需要使用间距加倍。举例来说，在一个实施例中，字线每一者可具有F的宽度，且可以F、2F、3F或某一其它宽度隔开。在其它实施例中，字线还不需要成对形成。举例来说，在一个实施例中，仅一条字线需要穿过每个有效区。 
图1中看不见字线12的全长，但在典型实施方案中，每条字线12可延伸越过数百、数千或数百万个晶体管。如所属领域的技术人员众所周知，在字线12的边缘处，字线12通常电耦合到例如电源的装置，所述装置在字线12上安置电流。通常，用于字线12的电源通过存储器控制器间接耦合到CPU。 
在一个实施例中，字线12包括p型半导体，例如掺杂有硼的硅。在其它实施例中，如所属领域的技术人员众所周知，字线12可包括n型半导体、金属硅化物、钨或其它类似作用的材料。在一些实施例中，字线12可在经分层、混合或化学键合的配置中包括多种材料。 
图1中可见的水平线由数字线(digit line)14a、14b形成。在一个示范性实施例中，图1中说明为DL的这些数字线中的每一者的宽度等于F。形成这些示范性数字线14的过程中未使用单距加倍。在优选实施例中，邻近数字线14a、14b以图1中说明为S的等于2F的距离隔开。数字线的间距优选大于2.5F，且优选小于4F。没有间距加倍技术，用以形成数字线的光刻技术当然强加较低限制。另一方面，在此范围的上限附近，光刻的精确度较小，且因此较为便宜，但存储器本身开始变得太大。在更优选的实施例中，数字线的间距介于2.75F与3.25F之间。此范围代表制造简易性与芯片尺寸之间的合乎需要的平衡。在所说明的实施例中，数字线14具有3F的间距。当然，在其它实施例中，不同宽度和间距是可能的。 
如同字线12，图1中看不见数字线14的全长，且数字线14通常延伸越过许多晶体管。如所属领域的技术人员众所周知，在数字线14的边缘处，数字线14通常电耦合到电流读出放大器，且从而耦合到电源或电压源。通常，用于数字线14的电源还通过存储器控制器间接耦合到CPU。由于数字线14之间的间距较宽松，所以读出放大器彼此可间隔较远，从而放宽其制造公差，并降低邻近数字信号的电容耦合的可能性。 
在一个实施例中，数字线14包括导电金属，例如钨、铜或银。在其它实施例中，如所属领域的技术人员众所周知，可使用其它导体或半导体。 
图1中可看到的其它特征是被说明位于曲线矩形中的有效区16，其形成相对于数字线的轴B成一角度的轴A。这些矩形代表衬底11内的掺杂区域或阱；然而，在其它实施例中，这些矩形不需要代表存储器装置10和衬底11之内或之上的物理结构或材料。有效区16界定存储器装置10的那些含有场效应晶体管且通常由场隔离元件(例如浅沟槽隔离(STI))环绕的部分。在一个优选实施例中，这些有效区每一者都包括两个漏极18和一个源极20。如所属领域的技术人员众所周知，所述源极和漏极可大于或小于图1所说明的源极和漏极。还可以所属领域的技术人员众所周知的许多方式中的任何一种方式来制造所述源极和漏极。 
在另一实施例中，有效区可包括一个源极和一个漏极，其中源极形成于数字线附近，且漏极经字线与源极隔开。在此类实施例中，存储器装置可类似于图1中的存储器装置10而配置，但只需要一条字线穿过每个有效区。当然，在另一实施例中，有效区可包括一个源极和一个漏极，且存储器装置可进一步包括在有效区附近延伸的两条字线，其类似于图1中所展示的成对字线12c、12d而配置。在此类实施例中，所述两条字线都可在源极与漏极之间延伸，且提供晶体管的冗余控制。 
如所说明，数字线14邻近位于数字线的行中的每个源极20且优选在其上方延伸(见图2)。同时，每个源极20的各侧经字线12与其邻近的极汲18隔开。在一个实施例中，源极20和漏极18包括n型半导电材料，例如掺杂有磷或锑的硅。在其它实施例中，如所属领域的技术人员众所周知，源极20和漏极18可包括p型半导体，或它们可由其它材料制造。事实上，源极20和漏极18不需要由相同化合物制造。 
参考展示有效区16中的一者的截面图的图2，简要论述存储器装置10的运作。对于DRAM运作的基本方式的进一步论述，颁发给Seely等人的第3,731,287号美国专利更详细地论述了DRAM，所述专利的全文以引用的方式并入本文中。 
如图2所示，漏极18和源极20可包括来自衬底11的相对平坦的上表面的突起。在 一个优选实施例中，将源极20和漏极18与衬底11制造成整体，且通过蚀刻单片晶片或衬底来使源极20和漏极18相对于衬底11的表面而凸起；在另一布置中，使用所属领域的技术人员众所周知的技术，通过选择性外延沉积来形成源极和漏极突起。 
在一个实施例中，数字线14b的至少一部分位于源极20的上表面上方。如图2所说明，源极20通过数字线插塞22电耦合到数字线14b，如图所示，可在多个阶段中或在单个阶段中形成所述插塞。同时，源极20经字线12a、12b与两个漏极18隔开。字线12a、12b优选嵌入衬底11中，其从表面向下延伸。这种设计的晶体管通常被称作内嵌存取装置或RAD。漏极18又通过接触插塞28电耦合到存储电容器24，且具体地说电耦合到存储电容器24的下电极26。在优选实施例中，存储电容器24包括经介电材料32与参考电极30隔开的下电极26。在此配置中，这些堆叠存储电容器24以所属领域的技术人员众所周知的方式起作用。如所说明，尽管可在其它布置中使用沟槽电容器，但将存储电容器24优选定位在衬底11的平面上方。 
在一个实施例中，每一存储电容器24的一侧都形成参考电极30，而下电极26电耦合到相关漏极18。字线12a、12b充当它们所穿过的场效应晶体管中的栅极，而数字线14b充当其电耦合到的源极的信号。因此，字线12a、12b优选通过允许或防止数字线14b上所载运的信号(代表逻辑“0”或逻辑“1”)写入到存储电容器24或从存储电容器24读取，来控制对耦合到每个漏极18的存储电容器24的存取。因此，连接到相关漏极18的两个电容器24中的每一者可含有一个数据位(即逻辑“0”或逻辑“1”)。在存储器阵列中，选定的数字线与字线的组合可唯一地识别应将数据写入到其中或从中读取数据的存储电容器24。 
接着返回到图1，可更详细地论述存储器装置10的设计和几何结构。在图1的右下角，已经说明了许多个轴。这些轴大体上与形成存储器装置10的电路元件的纵轴对准，且被说明以更清晰地展示形成于各个电气装置和元件之间的角。轴A代表有效区16的纵轴。每个有效区16的漏极18和源极20优选具有可用以界定纵轴的大体上线性关系。如所说明，所有有效区16都大体上平行。当然，将了解漏极18和源极20不需要形成绝对的直线，且实际上形成可由这三个点界定的大体角度。因此，在一些实施例中，轴A可由两个漏极18或由源极20和仅一个漏极18或以所属领域的技术人员将清楚理解的多种其它方式来界定。在其它实施例中，其中有效区包括单个漏极和单个源极，轴A可由单个漏极与单个源极之间的线来界定。 
轴B代表数字线14b的纵轴。在所说明的实施例中，数字线14b形成大体上的直线。 正如有效区16优选是平行的，数字线14a、14b也优选形成大体上平行的轴。因此，在优选实施例中，至少在每个存储器单元的区域中，每一有效区16的轴A与数字线14的每一轴B形成类似的角度。 
在图1所说明的优选实施例中，轴A与轴B之间形成锐角。在所说明的实施例中，轴A与轴B之间界定的此锐角θ为45°。 
有效区16相对于数字线14成角度促进了在漏极18与相关存储电容器24之间延伸的接触插塞28的定位。在优选实施例中(图2中所说明)，由于这些接触插塞28从漏极18的上表面开始延伸，所以如果数字线14不在漏极18的顶部上延伸，那么工程设计得以简化。即使在数字线14大体上重叠并接触同一有效区16的源极20时，也通过使有效区16成角度，可选择数字线14与漏极18之间的距离以促进漏极与接触插塞之间的电子接触。 
当然，角θ可具有许多值中的任何一个值，对所述值进行选择以使电气装置的间距最大化。如所属领域的技术人员将显而易见，不同角度将在邻近的有效区之间产生不同的间距。在一个实施例中，角θ优选介于10°与80°之间。在更优选的实施例中，角θ介于20°与60°之间。在更加优选的实施例中，角θ介于40°与50°之间。 
转向图3到图10，其更详细地说明一种制造存储器装置10的经间距加倍的字线12的方法。所属领域的技术人员将容易了解，所说明的实施例的特定材料可以其它组材料个别地代替或与其它组材料组合。图3说明半导体衬底11，已经根据常规半导体处理技术在所述半导体衬底11上形成了薄临时层40，其在优选实施例中包括氧化物。接着将例如氮化硅的硬掩模层42沉积在衬底11和临时层40上。可通过尤其例如溅镀、化学气相沉积(CVD)或低温沉积等任何众所周知的沉积工艺来形成硬掩模层42。尽管在优选实施例中，硬掩模层42包括氮化硅，但必须理解其还可由氧化硅(例如)或适用于下文所述的选择性蚀刻步骤的其它材料形成。 
接下来，在图中未说明的步骤中，使用形成于硬掩模层42上的光致抗蚀剂层来对硬掩模层42进行图案化。可使用常规光刻技术对光致抗蚀剂层进行图案化以形成掩模，且接着可通过经图案化的光致抗蚀剂对硬掩模层42进行各向异性蚀刻，以获得多个在y维度(如图1所界定)上延伸的硬掩模柱44，其中沟槽46使那些柱隔开。接着可通过常规技术，例如通过使用基于氧的等离子体来移除光致抗蚀剂层。 
参看图5A，在已经在硬掩模层42中形成沟槽46之后，可沉积间隔物材料保形层，以覆盖存储器装置10的整个表面。优选地，可相对于衬底11和临时层40选择性地蚀刻间隔物材料，且可相对于间隔物材料分别选择性地蚀刻衬底11和临时层40。在所说明的实施例中，间隔物材料包括多晶硅。可使用例如CVD或物理气相沉积(PVD)的任何合适的沉积工艺来沉积间隔物材料。
在将间隔物材料铺设在存储器装置10的垂直和水平表面上之后，可使用各向异性蚀刻，以定向间隔物蚀刻来优先将间隔物材料从水平表面移除。因此，间隔物材料形成间隔物48，即从另一种材料的侧壁延伸的材料。如图5A所示，间隔48形成于沟槽46内且使沟槽46变窄。 
参看图5B，接着可将第二硬掩模层49沉积在存储器装置10的整个表面上。优选将此硬掩模层49(在优选实施例中也为氮化硅)沉积到足以填充沟槽46的厚度。当然，可通过包含CVD或PVD的多种合适沉积工艺中的任何一种工艺来沉积硬掩模材料49。在沉积了足够量的硬掩模材料49之后，可通过所属领域的技术人员众所周知的多种工艺中的任何一种工艺来移除可能形成于间隔物48上和形成于先前沉积的硬掩模42的其它部分上的过量物。举例来说，可使装置10的表面平坦化到图5B的虚线的水平，使得剩余的间隔48的侧壁接近垂直。可使用例如化学机械平坦化磨的任何合适的平坦化工艺。 
可使用多种工艺中的任何一种工艺来去除现暴露于存储器装置10的上表面的间隔物48。在所说明的实施例中，可使用相对于氮化硅选择性地去除多晶硅的工艺。举例来说，在一个实施例中，可使用选择性湿式蚀刻。通过选择性地蚀刻临时层40以及衬底11的第二蚀刻来进一步加深形成于间隔物48已经被蚀刻之处的沟槽。还优选使用例如离子铣削或反应性离子蚀刻的定向工艺来形成这些沟槽。 
图6说明这些工艺的结果，其中呈沟槽50形式的开口或凹座经小于单独使用光刻技术所可能实现的最小间距的间距隔开。优选地，沟槽50在顶部具有约25nm与75nm之间的宽度。当然，所属领域的技术人员将了解，可使用用于间距倍增的大量其它技术来达到图6所示的阶段。许多此类技术都将大体上包含间隔物工艺，借此物理沉积可实现的间距小于单独的光刻技术可实现的间距。沟槽50通常还具有大于1∶1，且优选大于2∶1的纵横比。增加的深度使可用的体积最大化且因此使字线的传导率最大化，这是以用合适材料进行填充的难度为代价的。 
在形成这些沟槽50之后，通过所属领域的技术人员众所周知的多种方法中的任何一种方法来选择性去除硬掩模层42。在图7中，使栅极介电层54毯状沉积在装置上或在装置上热生长，从而对沟槽50的内表面进行加衬。在优选实施例中，所说明的栅极介电层54包括通过热氧化作用形成的氧化硅，但在其它实施例中栅极介电层54还可以是经沉积的高K材料。接着还可将在所说明的实施例中包括多晶硅的栅极材料层52毯状沉积在整个存储器装置10上。在一个实施例中，栅极层52完全填充沟槽50，且形成装置10的上表面。在优选实施例中，此多晶硅是未经掺杂的。 
在用以界定晶体管的漏极和源极的一系列掺杂步骤之后，对沟槽50中的未经掺杂的多晶硅进行回蚀，直到栅极层52的顶部驻留在衬底11的上表面之下为止。图8中展示此工艺阶段。如果经合适掺杂，那么图8的内嵌多晶硅52可充当存储器单元晶体管的字线和门电极。 
然而，优选的是，阵列中的门电极由比传统多晶硅栅极具有更高传导率的材料形成。这是因为内嵌栅极12(见图1和图2)比典型的门电极更狭窄。金属材料完全或部分地补偿阵列中的栅极的小体积，从而改进沿字线的横向信号传播速度。因此，可在内嵌之后，通过在上面沉积金属且进行反应来对图8的未经掺杂的多晶硅进行硅化物化。金属硅化物的传导率可比经掺杂的多晶硅的传导率好10倍，且表现合适的功函数。 
参看图9到图12，在另一布置中，最初将多晶硅52回蚀或向下平坦化到栅极氧化物54，而非内嵌，从而在此阶段无需内嵌而隔离沟槽50内的多晶硅。使沟槽50内的栅极层52的多晶硅经受硅化物化(自对准硅化物化)反应，以形成导电材料56层。可毯状沉积金属层55(图9)，且退火步骤可在金属接触硅的任何地方(例如在多晶硅栅极层52上)形成硅化物材料56(图12)。在一个实施例中，硅化物化材料包括硅和一种或一种以上金属，例如钨、钛、钌、钽、钴或镍。选择性金属蚀刻移除过量的金属，但不移除硅化物56。由此金属硅化物56形成增加沿字线的横向传导率的自对准层。 
优选地，将栅极层52完全硅化物化，以使横向传导率最大化。完全反应也确保了硅化物向下形成到沟槽50的底部。在所说明的内嵌存取装置(RAD)中，沟道不仅延伸越过栅极的底部，而且沿栅极的侧壁延伸。因此，不完全硅化物化会导致沿RAD沟道长度的不同功函数。此外，完全硅化物化确保了越过阵列，从阵列到阵列越过晶片且从晶片到晶片类似的栅极功函数。然而，已经发现，在用单种金属形成导电材料56的情况下，在所说明的沟槽50的紧密限制内难以实现完全硅化物化。举例来说，镍或钴倾向于在高纵横比的沟槽50内形成空隙。其它金属已对内嵌存取装置的完全硅化物化表现出类似的难度。所属领域的技术人员将了解，对于其它类型的凹座内的材料来说，完全硅化物化可能具有挑战性，所述其它类型的凹座例如是接触开口或通孔、电容器的堆叠容器形状、电容器沟槽等。 
不希望受理论束缚，空隙形成似乎是由硅化物化反应期间的扩散结合高纵横比沟槽 50的紧密限制所引起的。硅在钴中比钴在硅中更容易扩散。因此，硅倾向于在反应期间迁移，从而在沟槽50中留下空隙。此外，高温相变退火可将硅化物从CoSi转化成更稳定的CoSi2。另一方面，镍扩散到硅中比硅扩散到镍中更为容易，且因此也具有在将NiSi转化成NiSi2相的反应期间产生空隙的趋势。。 
因此，金属层55优选包括金属混合物，其中混合物中至少两种金属相对于硅具有相反扩散性。举例来说，金属层55可包括镍与钴的混合物，使得扩散方向倾向于彼此平衡且使空隙形成的风险降到最低。在此实例中，钴优选构成混合金属55的少于50at.％，且更优选的是混合物包括约70到90at.％的Ni和约10-30at.％的Co。已发现镍与钴的这种混合物更容易实现栅极层的完全硅化物化，而无空隙形成，从而增加沿字线的信号传播速度。与部分硅化物化相比，经完全硅化物化的字线不仅更具导电性，而且还将确保沿沟道长度的一致功函数。由于部分硅化物化视局部温度变化等因素而定将倾向于留下不一致的组合物，因此完全硅化物化还将从装置到装置越过阵列、从阵列到阵列或从晶片到晶片表现出更好的一致性。 
在一个实例中，将包括80％Ni和20％Co的溅镀目标溅镀在多晶硅52上以产生金属层55。接着使衬底经历硅化物化退火。虽然高温(例如800℃)退火持续较短时间是可能的，但优选在较低温度下进行退火持续较长时间。举例来说，在400到600℃下对衬底进行退火，持续25到35分钟。在实验中，在500℃在N2环境下，在分批炉中进行硅化物化退火，持续30分钟。 
鉴于本文的揭示内容，所属领域的技术人员可容易地选择其它合适的金属混合物用于沟槽内的完全硅化物化。在硅中比硅在其中更容易扩散的金属的实例包含Ni、Pt和Cu。硅在其中比其在硅中更容易扩散的金属的实例包含Co、Ti和Ta。 
图10A到图11B是展示在以氧化硅加衬的50nm宽的沟槽内的经内嵌且经完全硅化物化的NixCoySiz栅极材料的显微照片。图10A和图10B以两种不同的放大率展示越过双沟槽宽度的截面图。图11A和图11B以两种不同的放大率展示沿所述沟槽中的一者的长度的截面图。沟槽在顶部具有约50nm的宽度和约150nm的深度，从而使得这些沟槽的纵横比为约3∶1。观察到光滑均匀的组合物，其填充沟槽的至少下部而无空隙形成。在图11到图12的实例中，在沉积多晶硅52之后(图7)，可将多晶硅只回蚀到栅极介电上表面54，因此无需内嵌而隔离沟槽内的硅。 
现参看图12，可将硅化物化层56内嵌在沟槽内，且接着以例如氮化硅的第二绝缘层58覆盖。可沉积这些绝缘层58且接着对其进行蚀刻或平坦化。导电材料56由此形成完整的存储器装置10的字线12a、12b，且字线12a、12b经绝缘层58与其它电路元件隔开。因此，如所属领域的技术人员所熟知，字线12的间距倍增，且间距约为只使用光刻技术所可能获得的间距的一半。然而应注意，无论字线的间距是否倍增，本文揭示内容的某些方面都提供优点。 
当然，在其它实施例中，可通过所属领域的技术人员众所周知的多种工艺中的任何一种工艺来进行间距倍增。 
因此，所说明的实施例的经硅化物化的层56填充沟槽50的下部，优选填充大于50％的沟槽高度，更优选填充大于75％的沟槽高度。在所说明的实施例中，金属硅化物56中约70到90at％的金属是镍，且金属硅化物中约10到30at％的金属是钴。 
如所属领域的技术人员将了解，在优选实施例中，优选随着以上某些步骤的完成而同时界定外围中的逻辑，从而使芯片制造工艺的效率更高。具体地说，界定内嵌字线的硅和金属沉积步骤优选同时界定外围中的CMOS晶体管的衬底上的门电极。 
参看图13到图21，根据另一实施例，可针对外围中的阵列和逻辑区域中的经同时处理的门电极，确定不同的功函数和电阻率。在所说明的实施例中，这是通过经由形成外围中的栅极堆叠的部分的多晶硅层蚀刻阵列RAD沟槽来促进的。 
参看图13，在形成沟槽之前，可将多晶硅层60沉积在衬底11上。可首先将多晶硅层60沉积在薄电介质54a(例如生长栅极氧化物)上。接着可用例如相对于图3到图6所描述的间距加倍掩模(未图标)来对衬底进行图案化。还形成蚀刻终止层61，在所说明的实施例中，其包括约100到 
Figure S2006800394948D00111
的以TEOS沉积的氧化物。 
参看图14，经由上覆蚀刻终止层61、多晶硅层60、下伏电介质54a和衬底11来蚀刻沟槽50。接着可例如通过使沟槽壁氧化，来在衬底11的暴露部分上形成栅极电介质54b。如图所示，由于预先存在的蚀刻终止层61，无显著的其它氧化物在多晶硅60的上表面上生长。 
随后，如图15所展示，可将金属材料62沉积在多晶硅60上且进入沟槽50中。如相对于图9到图12所描述，优选用比多晶硅更具导电性的材料来填充沟槽50。在所说明的实施例中，金属材料62包括氮化钛(TiN)。 
参看图16，优选对金属材料62进行回蚀或平坦化，以使导电材料62的经隔离的线留在沟槽50中，在氧化物蚀刻终止层61上终止(见图15)。在回蚀之后，移除上覆在多晶硅层60上的蚀刻终止层61(例如对蚀刻终止层61的优选氧化物材料使用HF浸渍)，而沟槽50内的介电层54b受金属材料62保护。随后，将金属层64、66沉积在硅层60 上。如所属领域的技术人员将了解，第一介电层54a、多晶硅层60和上覆金属层64、66可充当外围中的晶体管栅极堆叠。所有这些层都沉积在所关注的两个区域中(在存储器实例中，沉积在外围和存储器阵列区域中)。多晶硅可经不同掺杂以建立所要的晶体管功函数，使得可使用单次材料沉积和不同的掺杂步骤来界定CMOS电路的NMOS和PMOS两者的栅极。上覆金属层66可用以改进沿控制所述栅极的线的横向信号传播速度，且在所说明的实施例中包括钨(W)。介入金属层64可确保多晶硅层60与上覆金属层66之间的接合点处的物理和电兼容性(例如实现粘附和势垒功能)，且在所说明的实施例中包括氮化钛，且更明确地说，包括富集金属的金属氮化物。 
参看图17，栅极堆叠还包含在所说明的实施例中由氮化硅形成的顶盖层68。图17展示在衬底的第一或存储器阵列区域70中用金属材料62填充的沟槽50。栅极堆叠层54a、60、64、66和68延伸越过衬底的阵列区域70和第二或外围或逻辑域区72两者。光致抗蚀剂掩模76经配置以用于对外围72中的晶体管栅极进行图案化。 
如图18所展示，一系列蚀刻步骤首先蚀刻穿过顶盖层68，包含用以移除金属层64、66的金属蚀刻。基于氯的反应性离子蚀刻(RIE)(例如)可选择性地移除典型的金属材料，例如所说明的钨短接层66和介入金属氮化物层64，而在下伏多晶硅层60上终止。如图所示，高度选择性允许在多晶硅60暴露之后继续进行金属蚀刻，直到金属材料62内嵌在沟槽50中为止。 
现参看图19，在将金属栅极材料62内嵌在阵列沟槽中之后可转换蚀刻化学作用，且可使用同一掩模76对硅60进行图案化，从而完成外围72的栅极堆叠80的图案化。 
现参看图20，在移除掩模之后，将间隔层84沉积在衬底上，保形涂覆栅极堆叠80，但填充阵列沟槽50顶部的凹座。在所说明的实施例中，间隔物层84包括氮化硅，但所属领域的技术人员将了解，可使用多种不同的绝缘材料。 
如图21所展示，随后的间隔物蚀刻(定向蚀刻)沿栅极堆叠80的侧壁留下侧壁间隔物86，从而容许源极/漏极区的自对准掺杂。然而在阵列72中，因为沟槽顶部的浅凹座被间隔物层84填充(见图20)，所以间隔物蚀刻在阵列72中只回蚀间隔物材料，从而留下绝缘顶盖层88将栅极材料62掩埋在沟槽50内。 
所属领域的技术人员将了解，为简明起见，本文的描述内容中省略了包含源极/漏极、沟道增强、门电极、轻掺杂漏极(LDD)和晕轮掺杂(halo doping)的CMOS晶体管的各种掺杂步骤。 
因此，图13到图21的实施例有助于阵列与外围中的晶体管的同时处理。在所说明 的实施例中，阵列晶体管为内嵌存取装置(RAD)，而外围栅极如常规平面MOS晶体管那样形成于衬底11上方。虽然在外围中的常规CMOS电路的情形下进行描述，但所属领域的技术人员将了解，外围晶体管可采取其它形式。有利的是，在所说明的实施例中，可在对外围栅极堆叠进行图案化的同时内嵌RAD沟槽中的金属层。此外，外围侧壁间隔物与RAD栅极或字线上的绝缘顶盖同时形成。 
尽管未图示，但将了解可使用常规DRAM制造技术来制造图2中展示的其它电路元件。举例来说，可使用不同等级的掺杂来形成图2的漏极18和源极20，且可根据多个沉积和掩蔽步骤形成堆叠存储电容器24。 
由于装置布置及其制造方法的缘故，图1和图2所展示的完整存储器装置10与常规DRAM相比具有许多优点。举例来说，每个存储器单元的尺寸和存储器装置10的总尺寸可实质上减小，而邻近的读出放大器之间的距离不会对应地实质上减小。此外，字线12和数字线14可具有实质上不同的间距，这允许数字线14与字线12相比具有大得多的间隔距离。举例来说，在优选实施例中，字线12具有1.5F的有效间距，而数字线14可具有3F的间距。此外，通过使数字线14和字线12实质上呈线性且大体上彼此垂直来简化其形成步骤，同时通过将有效区16与这些元件成一定角度放置来实现空间节约。在优选实施例中，字线12也是内嵌的，且不同于常规DRAM的布置，不存在用尽栅极与有效区的源极或漏极之间的有价值空间的间隔物(如在图2中可以容易地看到)。因此，可更密集地制造存储器装置10。 
此外，金属混合物的使用有助于掩埋在沟槽50内的硅的完全硅化物化，而不会有害地形成空隙。因此，对于体积相对较小的字线可实现较高传导率。 
虽然已经描述了本发明的某些实施例，但这些实施例只是作为实例而呈现，且不希望限制本发明的范围。实际上，本文描述的新颖方法和装置可以多种其它形式来体现；此外，可在不脱离本发明的精神的情况下，对本文所描述的方法和装置的形式作各种省略、替代和改变。所附权利要求书及其均等物意在涵盖属于本发明的范围和精神内的此类形式或修改。 

Claims (12)

1.一种在集成电路中形成金属硅化物结构的方法，所述方法包括：
在部分制成的集成电路内提供凹座；
将硅沉积到所述凹座中；
将金属混合物沉积在所述凹座上且使其与所述硅接触，所述金属混合物包括至少两种金属，所述至少两种金属的一者扩散到硅中比硅扩散到其中更为容易，所述至少两种金属的另一者扩散到硅中比硅扩散到其中更不容易；以及
使所述金属混合物与所述硅在所述凹座中反应，以在所述凹座内形成金属硅化物，
其中所述金属混合物包括70到80at.％的镍和10到30at.％的钴，且其中所述凹座具有大于2∶1的纵横比。
2.根据权利要求1所述的方法，其中反应包括在400℃与600℃之间的温度下对衬底进行退火。
3.根据权利要求1所述的方法，其中沉积所述金属混合物包括将来自单个溅镀目标的所述至少两种金属溅镀在所述凹座上。
4.根据权利要求3所述的方法，其进一步包括在沉积硅之前在所述凹座内的表面上形成薄介电层。
5.根据权利要求4所述的方法，其中所述凹座界定用于存储器阵列的内嵌存取装置。
6.根据权利要求5所述的方法，其中所述凹座是界定所述存储器阵列的字线的细长沟槽。
7.根据权利要求6所述的方法，其中所述凹座在所述沟槽的顶部具有25nm与75nm之间的宽度。
8.一种形成用于集成电路的内嵌存取装置的方法，所述方法包括：
在半导体结构中以大于2∶1的纵横比蚀刻沟槽；
用介电层对所述沟槽进行加衬；
用硅至少部分地填充所述经加衬的沟槽；
将金属层沉积在所述沟槽上且使其与所述硅接触；以及
使所述沟槽内的所述硅与所述金属层在硅化物化反应中完全反应，其中，进行完全反应而不产生空隙，其中沉积所述金属层包括沉积镍和钴的混合物，且其中所述混合物包括70到90at.％的镍和10到30at.％的钴。
9.根据权利要求8所述的方法，其中用硅至少部分地填充所述沟槽包括沉积硅和回蚀所述硅到界定所述沟槽的结构的上表面。
10.根据权利要求8所述的方法，其中用硅至少部分地填充所述沟槽包括回蚀所述硅直到其内嵌在所述沟槽中低于界定所述沟槽的结构的上表面。
11.根据权利要求8所述的方法，其中沉积所述金属层包括溅镀包含固定组成成分镍和钴的目标物。
12.根据权利要求8所述的方法，其中以大于2∶1的纵横比蚀刻沟槽包括以大于3∶1的纵横比蚀刻沟槽。
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Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7349232B2 (en) * 2006-03-15 2008-03-25 Micron Technology, Inc. 6F2 DRAM cell design with 3F-pitch folded digitline sense amplifier
KR100801078B1 (ko) * 2006-06-29 2008-02-11 삼성전자주식회사 수직 채널을 갖는 비휘발성 메모리 집적 회로 장치 및 그제조 방법
US8852851B2 (en) 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US7858471B2 (en) 2006-09-13 2010-12-28 Micron Technology, Inc. Methods of fabricating an access transistor for an integrated circuit device, methods of fabricating periphery transistors and access transistors, and methods of fabricating an access device comprising access transistors in an access circuitry region and peripheral transistors in a peripheral circuitry region spaced from the access circuitry region
US7696057B2 (en) * 2007-01-02 2010-04-13 International Business Machines Corporation Method for co-alignment of mixed optical and electron beam lithographic fabrication levels
US7989307B2 (en) 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
US10151981B2 (en) 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
US8222159B2 (en) * 2008-08-25 2012-07-17 Elpida Memory, Inc. Manufacturing method of semiconductor device
US8796155B2 (en) 2008-12-04 2014-08-05 Micron Technology, Inc. Methods of fabricating substrates
US8247302B2 (en) 2008-12-04 2012-08-21 Micron Technology, Inc. Methods of fabricating substrates
US8273634B2 (en) * 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
US8268543B2 (en) * 2009-03-23 2012-09-18 Micron Technology, Inc. Methods of forming patterns on substrates
US9330934B2 (en) 2009-05-18 2016-05-03 Micron Technology, Inc. Methods of forming patterns on substrates
CN102054526B (zh) * 2009-11-10 2012-10-31 中芯国际集成电路制造(上海)有限公司 一种dram存储器
US20110129991A1 (en) * 2009-12-02 2011-06-02 Kyle Armstrong Methods Of Patterning Materials, And Methods Of Forming Memory Cells
US20110223770A1 (en) * 2010-03-15 2011-09-15 Lam Research Corporation Nitride plasma etch with highly tunable selectivity to oxide
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8455341B2 (en) 2010-09-02 2013-06-04 Micron Technology, Inc. Methods of forming features of integrated circuitry
US8569810B2 (en) 2010-12-07 2013-10-29 International Business Machines Corporation Metal semiconductor alloy contact with low resistance
US8575032B2 (en) 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
WO2013013698A1 (en) * 2011-07-22 2013-01-31 X-Fab Semiconductor Foundries Ag A semiconductor device
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
JP2013135029A (ja) * 2011-12-26 2013-07-08 Elpida Memory Inc 半導体装置の製造方法
US9177794B2 (en) 2012-01-13 2015-11-03 Micron Technology, Inc. Methods of patterning substrates
KR101901322B1 (ko) 2012-02-28 2018-09-21 삼성전자주식회사 가변 저항 메모리 소자
KR20130104200A (ko) * 2012-03-13 2013-09-25 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
US8629048B1 (en) 2012-07-06 2014-01-14 Micron Technology, Inc. Methods of forming a pattern on a substrate
US20140036565A1 (en) * 2012-08-02 2014-02-06 Nanya Technology Corporation Memory device and method of manufacturing memory structure
US9064745B2 (en) 2012-08-29 2015-06-23 International Business Machines Corporation Sublithographic width finFET employing solid phase epitaxy
US10103247B1 (en) 2017-10-17 2018-10-16 Globalfoundries Inc. Vertical transistor having buried contact, and contacts using work function metals and silicides
WO2020191068A1 (en) * 2019-03-20 2020-09-24 Tokyo Electron Limited Method of selectively forming metal silicides for semiconductor devices
US11088147B2 (en) 2019-06-26 2021-08-10 Micron Technology, Inc. Apparatus with doped surfaces, and related methods with in situ doping
DE102021203566A1 (de) 2021-04-12 2022-10-13 Robert Bosch Gesellschaft mit beschränkter Haftung MEMS Schalter mit eingebettetem Metallkontakt

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465309B1 (en) * 2000-12-12 2002-10-15 Advanced Micro Devices, Inc. Silicide gate transistors
EP0967643B1 (en) * 1998-06-22 2006-12-13 International Business Machines Corporation Method of providing low-resistance salicide fill for trench capacitors

Family Cites Families (293)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE755502A (fr) 1969-09-09 1971-03-01 Basf Ag Bismonocarboxylates du formyl-3-butanediol-1,2 et procede pour leur preparation
US3731287A (en) 1971-07-02 1973-05-01 Gen Instrument Corp Single device memory system having shift register output characteristics
US4234362A (en) 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4508579A (en) 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
US4432132A (en) 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
US4419809A (en) 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
DE3242113A1 (de) 1982-11-13 1984-05-24 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper
US4716131A (en) 1983-11-28 1987-12-29 Nec Corporation Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film
US4570325A (en) 1983-12-16 1986-02-18 Kabushiki Kaisha Toshiba Manufacturing a field oxide region for a semiconductor device
JPS60202166A (ja) 1984-03-26 1985-10-12 Toshiba Chem Corp 導電性塗料
US4648937A (en) 1985-10-30 1987-03-10 International Business Machines Corporation Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
GB8528967D0 (en) 1985-11-25 1986-01-02 Plessey Co Plc Semiconductor device manufacture
US5514885A (en) 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
US4983544A (en) 1986-10-20 1991-01-08 International Business Machines Corporation Silicide bridge contact process
JPS6413290A (en) 1987-07-07 1989-01-18 Oki Electric Ind Co Ltd Semiconductor memory
US4776922A (en) 1987-10-30 1988-10-11 International Business Machines Corporation Formation of variable-width sidewall structures
US4838991A (en) 1987-10-30 1989-06-13 International Business Machines Corporation Process for defining organic sidewall structures
US5024959A (en) 1989-09-25 1991-06-18 Motorola, Inc. CMOS process using doped glass layer
US5497497A (en) 1989-11-03 1996-03-05 Compaq Computer Corp. Method and apparatus for resetting multiple processors using a common ROM
US5387555A (en) * 1992-09-03 1995-02-07 Harris Corporation Bonded wafer processing with metal silicidation
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
JP2792211B2 (ja) 1990-07-06 1998-09-03 日本電気株式会社 半導体記憶装置
US5013680A (en) 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5053105A (en) 1990-07-19 1991-10-01 Micron Technology, Inc. Process for creating an etch mask suitable for deep plasma etches employing self-aligned silicidation of a metal layer masked with a silicon dioxide template
US5177027A (en) 1990-08-17 1993-01-05 Micron Technology, Inc. Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path
US5047117A (en) 1990-09-26 1991-09-10 Micron Technology, Inc. Method of forming a narrow self-aligned, annular opening in a masking layer
US5064683A (en) * 1990-10-29 1991-11-12 Motorola, Inc. Method for polish planarizing a semiconductor substrate by using a boron nitride polish stop
DE4034612A1 (de) 1990-10-31 1992-05-07 Huels Chemische Werke Ag Verfahren zur herstellung von methacryloxy- oder acryloxygruppen enthaltenden organosilanen
IT1243919B (it) 1990-11-20 1994-06-28 Cons Ric Microelettronica Procedimento per l'ottenimento di solchi submicrometrici planarizzati in circuiti integrati realizzati con tecnologia ulsi
US5122848A (en) 1991-04-08 1992-06-16 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5250450A (en) 1991-04-08 1993-10-05 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
JP2851962B2 (ja) 1992-01-21 1999-01-27 シャープ株式会社 半導体読み出し専用メモリ
JPH05343370A (ja) 1992-06-10 1993-12-24 Toshiba Corp 微細パタ−ンの形成方法
US5330879A (en) 1992-07-16 1994-07-19 Micron Technology, Inc. Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer
US5420819A (en) 1992-09-24 1995-05-30 Nonvolatile Electronics, Incorporated Method for sensing data in a magnetoresistive memory using large fractions of memory cell films for data storage
DE4236609A1 (de) 1992-10-29 1994-05-05 Siemens Ag Verfahren zur Erzeugung einer Struktur in der Oberfläche eines Substrats
JP2884962B2 (ja) 1992-10-30 1999-04-19 日本電気株式会社 半導体メモリ
US6042998A (en) 1993-09-30 2000-03-28 The University Of New Mexico Method and apparatus for extending spatial frequencies in photolithography images
US5645887A (en) * 1994-01-14 1997-07-08 Lg Semicon Co., Ltd. Method for forming platinum silicide plugs
JP3720064B2 (ja) 1994-01-20 2005-11-24 株式会社ルネサステクノロジ 半導体集積回路
US5604159A (en) 1994-01-31 1997-02-18 Motorola, Inc. Method of making a contact structure
JP2658870B2 (ja) 1994-04-22 1997-09-30 日本電気株式会社 半導体記憶装置およびその製造方法
US5841611A (en) * 1994-05-02 1998-11-24 Matsushita Electric Industrial Co., Ltd. Magnetoresistance effect device and magnetoresistance effect type head, memory device, and amplifying device using the same
US5495441A (en) 1994-05-18 1996-02-27 United Microelectronics Corporation Split-gate flash memory cell
JPH0855920A (ja) 1994-08-15 1996-02-27 Toshiba Corp 半導体装置の製造方法
JPH0855908A (ja) 1994-08-17 1996-02-27 Toshiba Corp 半導体装置
JP3469362B2 (ja) 1994-08-31 2003-11-25 株式会社東芝 半導体記憶装置
US5600153A (en) 1994-10-07 1997-02-04 Micron Technology, Inc. Conductive polysilicon lines and thin film transistors
US6252267B1 (en) 1994-12-28 2001-06-26 International Business Machines Corporation Five square folded-bitline DRAM cell
US5539229A (en) 1994-12-28 1996-07-23 International Business Machines Corporation MOSFET with raised STI isolation self-aligned to the gate stack
US6175128B1 (en) 1998-03-31 2001-01-16 International Business Machines Corporation Process for building borderless bitline, wordline and DRAM structure and resulting structure
US5795830A (en) 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
US5700733A (en) 1995-06-27 1997-12-23 Micron Technology, Inc. Semiconductor processing methods of forming field oxide regions on a semiconductor substrate
KR100190757B1 (ko) 1995-06-30 1999-06-01 김영환 모스 전계 효과 트랜지스터 형성방법
US5604370A (en) 1995-07-11 1997-02-18 Advanced Micro Devices, Inc. Field implant for semiconductor device
US5756395A (en) 1995-08-18 1998-05-26 Lsi Logic Corporation Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures
US5638318A (en) 1995-09-11 1997-06-10 Micron Technology, Inc. Ferroelectric memory using ferroelectric reference cells
US5680344A (en) 1995-09-11 1997-10-21 Micron Technology, Inc. Circuit and method of operating a ferrolectric memory in a DRAM mode
US5677865A (en) 1995-09-11 1997-10-14 Micron Technology, Inc. Ferroelectric memory using reference charge circuit
US5771150A (en) 1996-01-03 1998-06-23 Micron Technology, Inc. Capacitor constructions
US5789320A (en) 1996-04-23 1998-08-04 International Business Machines Corporation Plating of noble metal electrodes for DRAM and FRAM
JP3164026B2 (ja) 1996-08-21 2001-05-08 日本電気株式会社 半導体装置及びその製造方法
US5861328A (en) 1996-10-07 1999-01-19 Motorola, Inc. Method of fabricating GMR devices
US5998256A (en) 1996-11-01 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
US6395613B1 (en) 2000-08-30 2002-05-28 Micron Technology, Inc. Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts
US6150211A (en) 1996-12-11 2000-11-21 Micron Technology, Inc. Methods of forming storage capacitors in integrated circuitry memory cells and integrated circuitry
JP2956626B2 (ja) 1996-12-12 1999-10-04 日本電気株式会社 Ｍｏｓ型半導体装置の製造方法
US5748519A (en) 1996-12-13 1998-05-05 Motorola, Inc. Method of selecting a memory cell in a magnetic random access memory device
US5804458A (en) 1996-12-16 1998-09-08 Motorola, Inc. Method of fabricating spaced apart submicron magnetic memory cells
US5913116A (en) 1997-01-08 1999-06-15 Advanced Micro Devices Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidewall spacer
JP2982895B2 (ja) 1997-02-06 1999-11-29 日本電気株式会社 Ｃｍｏｓ半導体装置およびその製造方法
US5780349A (en) 1997-02-20 1998-07-14 National Semiconductor Corporation Self-aligned MOSFET gate/source/drain salicide formation
US5902690A (en) 1997-02-25 1999-05-11 Motorola, Inc. Stray magnetic shielding for a non-volatile MRAM
US5998257A (en) 1997-03-13 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry
US6004835A (en) 1997-04-25 1999-12-21 Micron Technology, Inc. Method of forming integrated circuitry, conductive lines, a conductive grid, a conductive network, an electrical interconnection to anode location and an electrical interconnection with a transistor source/drain region
EP0882806B1 (en) * 1997-05-21 2002-01-02 Kabushiki Kaisha Toyota Chuo Kenkyusho Hard molybdenum alloy, wear resistant alloy and method for manufacturing the same
US5917749A (en) 1997-05-23 1999-06-29 Motorola, Inc. MRAM cell requiring low switching field
US6072209A (en) 1997-07-08 2000-06-06 Micro Technology, Inc. Four F2 folded bit line DRAM cell structure having buried bit and word lines
US6150687A (en) * 1997-07-08 2000-11-21 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
US6191470B1 (en) 1997-07-08 2001-02-20 Micron Technology, Inc. Semiconductor-on-insulator memory cell with buried word and body lines
US5909618A (en) 1997-07-08 1999-06-01 Micron Technology, Inc. Method of making memory cell with vertical transistor and buried word and body lines
US6063688A (en) 1997-09-29 2000-05-16 Intel Corporation Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
US5989966A (en) 1997-12-15 1999-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and a deep sub-micron field effect transistor structure for suppressing short channel effects
US5956267A (en) * 1997-12-18 1999-09-21 Honeywell Inc Self-aligned wordline keeper and method of manufacture therefor
US6165833A (en) 1997-12-19 2000-12-26 Micron Technology, Inc. Semiconductor processing method of forming a capacitor
US6291334B1 (en) 1997-12-19 2001-09-18 Applied Materials, Inc. Etch stop layer for dual damascene process
US6004862A (en) 1998-01-20 1999-12-21 Advanced Micro Devices, Inc. Core array and periphery isolation technique
US5963803A (en) 1998-02-02 1999-10-05 Advanced Micro Devices, Inc. Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths
JP2975917B2 (ja) 1998-02-06 1999-11-10 株式会社半導体プロセス研究所 半導体装置の製造方法及び半導体装置の製造装置
US6104633A (en) 1998-02-10 2000-08-15 International Business Machines Corporation Intentional asymmetry imposed during fabrication and/or access of magnetic tunnel junction devices
US6147405A (en) * 1998-02-19 2000-11-14 Micron Technology, Inc. Asymmetric, double-sided self-aligned silicide and method of forming the same
US5963469A (en) 1998-02-24 1999-10-05 Micron Technology, Inc. Vertical bipolar read access for low voltage memory cell
US6097065A (en) 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6696746B1 (en) 1998-04-29 2004-02-24 Micron Technology, Inc. Buried conductors
US5933725A (en) 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
US6632718B1 (en) 1998-07-15 2003-10-14 Texas Instruments Incorporated Disposable spacer technology for reduced cost CMOS processing
US6245662B1 (en) 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
US6362506B1 (en) 1998-08-26 2002-03-26 Texas Instruments Incorporated Minimization-feasible word line structure for DRAM cell
US6104068A (en) * 1998-09-01 2000-08-15 Micron Technology, Inc. Structure and method for improved signal processing
US6320222B1 (en) * 1998-09-01 2001-11-20 Micron Technology, Inc. Structure and method for reducing threshold voltage variations due to dopant fluctuations
JP4197775B2 (ja) 1998-09-10 2008-12-17 浜松ホトニクス株式会社 半導体位置検出器
WO2000017939A1 (fr) * 1998-09-22 2000-03-30 Hitachi, Ltd. Dispositif a semi-conducteur et son procede de production
US6333866B1 (en) 1998-09-28 2001-12-25 Texas Instruments Incorporated Semiconductor device array having dense memory cell array and heirarchical bit line scheme
US6071789A (en) 1998-11-10 2000-06-06 Vanguard International Semiconductor Corporation Method for simultaneously fabricating a DRAM capacitor and metal interconnections
US6005800A (en) * 1998-11-23 1999-12-21 International Business Machines Corporation Magnetic memory array with paired asymmetric memory cells for improved write margin
US5977579A (en) 1998-12-03 1999-11-02 Micron Technology, Inc. Trench dram cell with vertical device and buried word lines
US6211044B1 (en) 1999-04-12 2001-04-03 Advanced Micro Devices Process for fabricating a semiconductor device component using a selective silicidation reaction
US6136662A (en) 1999-05-13 2000-10-24 Lsi Logic Corporation Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same
US6908800B1 (en) 1999-06-04 2005-06-21 Texas Instruments Incorporated Tunable sidewall spacer process for CMOS integrated circuits
JP4063450B2 (ja) 1999-06-14 2008-03-19 エルピーダメモリ株式会社 半導体集積回路装置
US6436526B1 (en) 1999-06-17 2002-08-20 Matsushita Electric Industrial Co., Ltd. Magneto-resistance effect element, magneto-resistance effect memory cell, MRAM and method for performing information write to or read from the magneto-resistance effect memory cell
US6274905B1 (en) * 1999-06-30 2001-08-14 Fairchild Semiconductor Corporation Trench structure substantially filled with high-conductivity material
US6134139A (en) * 1999-07-28 2000-10-17 Hewlett-Packard Magnetic memory structure with improved half-select margin
JP2001077196A (ja) 1999-09-08 2001-03-23 Sony Corp 半導体装置の製造方法
US6282113B1 (en) 1999-09-29 2001-08-28 International Business Machines Corporation Four F-squared gapless dual layer bitline DRAM array architecture
US6362057B1 (en) 1999-10-26 2002-03-26 Motorola, Inc. Method for forming a semiconductor device
SE518965C2 (sv) * 1999-11-04 2002-12-10 Ruben Haegglund Sedelhanteringsanordning
US6582891B1 (en) 1999-12-02 2003-06-24 Axcelis Technologies, Inc. Process for reducing edge roughness in patterned photoresist
KR100311050B1 (ko) 1999-12-14 2001-11-05 윤종용 커패시터의 전극 제조 방법
US6271080B1 (en) 1999-12-16 2001-08-07 International Business Machines Corporation Structure and method for planar MOSFET DRAM cell free of wordline gate conductor to storage trench overlay sensitivity
JP4860022B2 (ja) 2000-01-25 2012-01-25 エルピーダメモリ株式会社 半導体集積回路装置の製造方法
US6573030B1 (en) 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
US6967140B2 (en) 2000-03-01 2005-11-22 Intel Corporation Quantum wire gate device and method of making same
US6297554B1 (en) 2000-03-10 2001-10-02 United Microelectronics Corp. Dual damascene interconnect structure with reduced parasitic capacitance
US6251711B1 (en) 2000-03-17 2001-06-26 United Microelectronics Corp. Method for forming bridge free silicide
US6423474B1 (en) 2000-03-21 2002-07-23 Micron Technology, Inc. Use of DARC and BARC in flash memory processing
US20050164443A1 (en) 2000-05-18 2005-07-28 Youngmin Kim Tunable sidewall spacer process for CMOS integrated circuits
CA2349139C (en) 2000-05-31 2007-09-11 Kansai Paint Co., Ltd. Cationic resin composition
JP3773755B2 (ja) * 2000-06-02 2006-05-10 セイコーインスツル株式会社 縦形ｍｏｓトランジスタ及びその製造方法
US6396096B1 (en) 2000-06-21 2002-05-28 International Business Machines Corporation Design layout for a dense memory cell structure
US6424561B1 (en) 2000-07-18 2002-07-23 Micron Technology, Inc. MRAM architecture using offset bits for increased write selectivity
US6632741B1 (en) 2000-07-19 2003-10-14 International Business Machines Corporation Self-trimming method on looped patterns
US6236590B1 (en) * 2000-07-21 2001-05-22 Hewlett-Packard Company Optimal write conductors layout for improved performance in MRAM
US6455372B1 (en) 2000-08-14 2002-09-24 Micron Technology, Inc. Nucleation for improved flash erase characteristics
US6348380B1 (en) 2000-08-25 2002-02-19 Micron Technology, Inc. Use of dilute steam ambient for improvement of flash devices
DE10041749A1 (de) * 2000-08-27 2002-03-14 Infineon Technologies Ag Vertikale nichtflüchtige Halbleiter-Speicherzelle sowie Verfahren zu deren Herstellung
US7118960B2 (en) * 2000-08-31 2006-10-10 Micron Technology, Inc. Selective polysilicon stud growth
SE517275C2 (sv) 2000-09-20 2002-05-21 Obducat Ab Sätt vid våtetsning av ett substrat
US6667237B1 (en) 2000-10-12 2003-12-23 Vram Technologies, Llc Method and apparatus for patterning fine dimensions
JP2002124585A (ja) 2000-10-17 2002-04-26 Hitachi Ltd 不揮発性半導体記憶装置およびその製造方法
US6534243B1 (en) 2000-10-23 2003-03-18 Advanced Micro Devices, Inc. Chemical feature doubling process
US6926843B2 (en) 2000-11-30 2005-08-09 International Business Machines Corporation Etching of hard masks
US6475874B2 (en) * 2000-12-07 2002-11-05 Advanced Micro Devices, Inc. Damascene NiSi metal gate high-k transistor
US6368950B1 (en) * 2000-12-12 2002-04-09 Advanced Micro Devices, Inc. Silicide gate transistors
US6566682B2 (en) 2001-02-09 2003-05-20 Micron Technology, Inc. Programmable memory address and decode circuits with ultra thin vertical body transistors
US6496034B2 (en) 2001-02-09 2002-12-17 Micron Technology, Inc. Programmable logic arrays with ultra thin body transistors
US6559491B2 (en) 2001-02-09 2003-05-06 Micron Technology, Inc. Folded bit line DRAM with ultra thin body transistors
US6448601B1 (en) 2001-02-09 2002-09-10 Micron Technology, Inc. Memory address and decode circuits with ultra thin body transistors
US6424001B1 (en) 2001-02-09 2002-07-23 Micron Technology, Inc. Flash memory with ultra thin vertical body transistors
US6377070B1 (en) * 2001-02-09 2002-04-23 Micron Technology, Inc. In-service programmable logic arrays with ultra thin vertical body transistors
US6531727B2 (en) 2001-02-09 2003-03-11 Micron Technology, Inc. Open bit line DRAM with ultra thin body transistors
US6649476B2 (en) 2001-02-15 2003-11-18 Micron Technology, Inc. Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array
JP2002261161A (ja) * 2001-03-05 2002-09-13 Hitachi Ltd 半導体装置の製造方法
US20040074949A1 (en) * 2001-03-07 2004-04-22 Masayuki Narita Friction agitation joining method flat material for plastic working and closed end sleeve like body
US6545904B2 (en) 2001-03-16 2003-04-08 Micron Technology, Inc. 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array
US6475867B1 (en) 2001-04-02 2002-11-05 Advanced Micro Devices, Inc. Method of forming integrated circuit features by oxidation of titanium hard mask
US6548347B2 (en) 2001-04-12 2003-04-15 Micron Technology, Inc. Method of forming minimally spaced word lines
US6498062B2 (en) 2001-04-27 2002-12-24 Micron Technology, Inc. DRAM access transistor
ATE358891T1 (de) * 2001-04-28 2007-04-15 Koninkl Philips Electronics Nv Halbleiteranordnungen mit graben-gateelektrode und verfahren zu deren herstellung
US6740594B2 (en) 2001-05-31 2004-05-25 Infineon Technologies Ag Method for removing carbon-containing polysilane from a semiconductor without stripping
KR100418581B1 (ko) * 2001-06-12 2004-02-11 주식회사 하이닉스반도체 메모리 소자의 제조방법
KR20030002863A (ko) * 2001-06-30 2003-01-09 주식회사 하이닉스반도체 코어를 가진 플러그 구조 상의 강유전체 메모리소자 및 그제조방법
JP2003023150A (ja) * 2001-07-10 2003-01-24 Sony Corp トレンチゲート型半導体装置及びその作製方法
US6522584B1 (en) 2001-08-02 2003-02-18 Micron Technology, Inc. Programming methods for multi-level flash EEPROMs
US6744094B2 (en) 2001-08-24 2004-06-01 Micron Technology Inc. Floating gate transistor with horizontal gate layers stacked next to vertical body
TW497138B (en) 2001-08-28 2002-08-01 Winbond Electronics Corp Method for improving consistency of critical dimension
DE10142590A1 (de) 2001-08-31 2003-04-03 Infineon Technologies Ag Verfahren zur Seitenwandverstärkung von Resiststrukturen und zur Herstellung von Strukturen mit reduzierter Strukturgröße
US7226853B2 (en) 2001-12-26 2007-06-05 Applied Materials, Inc. Method of forming a dual damascene structure utilizing a three layer hard mask structure
US6638441B2 (en) 2002-01-07 2003-10-28 Macronix International Co., Ltd. Method for pitch reduction
US7078296B2 (en) 2002-01-16 2006-07-18 Fairchild Semiconductor Corporation Self-aligned trench MOSFETs and methods for making the same
DE10207131B4 (de) 2002-02-20 2007-12-20 Infineon Technologies Ag Verfahren zur Bildung einer Hartmaske in einer Schicht auf einer flachen Scheibe
US6838722B2 (en) * 2002-03-22 2005-01-04 Siliconix Incorporated Structures of and methods of fabricating trench-gated MIS devices
US6759180B2 (en) 2002-04-23 2004-07-06 Hewlett-Packard Development Company, L.P. Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography
US20030207584A1 (en) 2002-05-01 2003-11-06 Swaminathan Sivakumar Patterning tighter and looser pitch geometries
US6951709B2 (en) 2002-05-03 2005-10-04 Micron Technology, Inc. Method of fabricating a semiconductor multilevel interconnect structure
US6602779B1 (en) 2002-05-13 2003-08-05 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer
US6900521B2 (en) 2002-06-10 2005-05-31 Micron Technology, Inc. Vertical transistors and output prediction logic circuits containing same
TW543195B (en) 2002-06-12 2003-07-21 Powerchip Semiconductor Corp Split-gate flash memory structure and method of manufacture
US6734107B2 (en) 2002-06-12 2004-05-11 Macronix International Co., Ltd. Pitch reduction in semiconductor fabrication
US6559017B1 (en) 2002-06-13 2003-05-06 Advanced Micro Devices, Inc. Method of using amorphous carbon as spacer material in a disposable spacer process
KR100476924B1 (ko) 2002-06-14 2005-03-17 삼성전자주식회사 반도체 장치의 미세 패턴 형성 방법
US6777725B2 (en) 2002-06-14 2004-08-17 Ingentix Gmbh & Co. Kg NROM memory circuit with recessed bitline
US6924191B2 (en) 2002-06-20 2005-08-02 Applied Materials, Inc. Method for fabricating a gate structure of a field effect transistor
DE10228807B4 (de) 2002-06-27 2009-07-23 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Mikrostrukturelementen
AU2003280498A1 (en) 2002-06-27 2004-01-19 Advanced Micro Devices, Inc. Method of defining the dimensions of circuit elements by using spacer deposition techniques
US6689695B1 (en) 2002-06-28 2004-02-10 Taiwan Semiconductor Manufacturing Company Multi-purpose composite mask for dual damascene patterning
US6835663B2 (en) 2002-06-28 2004-12-28 Infineon Technologies Ag Hardmask of amorphous carbon-hydrogen (a-C:H) layers with tunable etch resistivity
US6960510B2 (en) 2002-07-01 2005-11-01 International Business Machines Corporation Method of making sub-lithographic features
US7182823B2 (en) * 2002-07-05 2007-02-27 Olin Corporation Copper alloy containing cobalt, nickel and silicon
US20040018738A1 (en) 2002-07-22 2004-01-29 Wei Liu Method for fabricating a notch gate structure of a field effect transistor
US6764949B2 (en) 2002-07-31 2004-07-20 Advanced Micro Devices, Inc. Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US6673684B1 (en) 2002-07-31 2004-01-06 Advanced Micro Devices, Inc. Use of diamond as a hard mask material
US6939808B2 (en) 2002-08-02 2005-09-06 Applied Materials, Inc. Undoped and fluorinated amorphous carbon film as pattern mask for metal etch
US20040046048A1 (en) * 2002-08-13 2004-03-11 Hsu Shih Hao Sprayer assembly for positioning hoses
US7071043B2 (en) 2002-08-15 2006-07-04 Micron Technology, Inc. Methods of forming a field effect transistor having source/drain material over insulative material
US6566280B1 (en) 2002-08-26 2003-05-20 Intel Corporation Forming polymer features on a substrate
US6794699B2 (en) 2002-08-29 2004-09-21 Micron Technology Inc Annular gate and technique for fabricating an annular gate
US7205598B2 (en) 2002-08-29 2007-04-17 Micron Technology, Inc. Random access memory device utilizing a vertically oriented select transistor
US6756284B2 (en) 2002-09-18 2004-06-29 Silicon Storage Technology, Inc. Method for forming a sublithographic opening in a semiconductor process
US7041047B2 (en) * 2002-10-04 2006-05-09 Boston Scientific Scimed, Inc. Method and apparatus for the delivery of brachytherapy
US6706571B1 (en) 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6888755B2 (en) 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US6804142B2 (en) 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US7119020B2 (en) 2002-12-04 2006-10-10 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
US6825529B2 (en) 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
JP2004193483A (ja) 2002-12-13 2004-07-08 Renesas Technology Corp 半導体記憶装置
US6686245B1 (en) 2002-12-20 2004-02-03 Motorola, Inc. Vertical MOSFET with asymmetric gate structure
US7084076B2 (en) 2003-02-27 2006-08-01 Samsung Electronics, Co., Ltd. Method for forming silicon dioxide film using siloxane
US6861701B2 (en) * 2003-03-05 2005-03-01 Advanced Analogic Technologies, Inc. Trench power MOSFET with planarized gate bus
US7105089B2 (en) 2003-03-13 2006-09-12 3M Innovative Properties Company Liquid—liquid extraction system and method
KR100870176B1 (ko) * 2003-06-27 2008-11-25 삼성전자주식회사 니켈 합금 샐리사이드 공정, 이를 사용하여 반도체소자를제조하는 방법, 그에 의해 형성된 니켈 합금 실리사이드막및 이를 사용하여 제조된 반도체소자
US7015124B1 (en) 2003-04-28 2006-03-21 Advanced Micro Devices, Inc. Use of amorphous carbon for gate patterning
US6773998B1 (en) 2003-05-20 2004-08-10 Advanced Micro Devices, Inc. Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning
JP4578785B2 (ja) 2003-05-21 2010-11-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
DE10332725A1 (de) 2003-07-18 2005-02-24 Forschungszentrum Jülich GmbH Verfahren zur selbstjustierenden Verkleinerung von Strukturen
US7049702B2 (en) * 2003-08-14 2006-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Damascene structure at semiconductor substrate level
US7112483B2 (en) * 2003-08-29 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a device having multiple silicide types
KR100499175B1 (ko) 2003-09-01 2005-07-01 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US7384868B2 (en) * 2003-09-15 2008-06-10 International Business Machines Corporation Reduction of silicide formation temperature on SiGe containing substrates
US6844591B1 (en) 2003-09-17 2005-01-18 Micron Technology, Inc. Method of forming DRAM access transistors
DE10345455A1 (de) 2003-09-30 2005-05-04 Infineon Technologies Ag Verfahren zum Erzeugen einer Hartmaske und Hartmasken-Anordnung
US20050156208A1 (en) * 2003-09-30 2005-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Device having multiple silicide types and a method for its fabrication
KR100536801B1 (ko) 2003-10-01 2005-12-14 동부아남반도체 주식회사 반도체 소자 및 그 제조 방법
US6867116B1 (en) 2003-11-10 2005-03-15 Macronix International Co., Ltd. Fabrication method of sub-resolution pitch for integrated circuits
US6946709B2 (en) 2003-12-02 2005-09-20 International Business Machines Corporation Complementary transistors having different source and drain extension spacing controlled by different spacer sizes
US7153734B2 (en) * 2003-12-29 2006-12-26 Intel Corporation CMOS device with metal and silicide gate electrodes and a method for making it
US20050144792A1 (en) 2004-01-06 2005-07-07 The Shire Corporation In-line sanding paddle with multiple extensions having certain tensile strengths
US7056794B2 (en) * 2004-01-09 2006-06-06 International Business Machines Corporation FET gate structure with metal gate electrode and silicide contact
US6875703B1 (en) 2004-01-20 2005-04-05 International Business Machines Corporation Method for forming quadruple density sidewall image transfer (SIT) structures
US20060033678A1 (en) * 2004-01-26 2006-02-16 Applied Materials, Inc. Integrated electroless deposition system
US7372091B2 (en) 2004-01-27 2008-05-13 Micron Technology, Inc. Selective epitaxy vertical integrated circuit components
KR100574317B1 (ko) * 2004-02-19 2006-04-26 삼성전자주식회사 게이트 구조물, 이를 갖는 반도체 장치 및 그 형성 방법
US7262089B2 (en) 2004-03-11 2007-08-28 Micron Technology, Inc. Methods of forming semiconductor structures
WO2005094231A2 (en) 2004-03-19 2005-10-13 The Regents Of The University Of California Methods for fabrication of positional and compositionally controlled nanostructures on substrate
DE102004016073B4 (de) * 2004-03-30 2010-12-23 Texas Instruments Deutschland Gmbh Verfahren zur Erzeugung eines Impulsausgangssignals aus einem periodischen Sägezahnsignal und einer Referenzspannung, und getakteter Stromwandler
US6955961B1 (en) 2004-05-27 2005-10-18 Macronix International Co., Ltd. Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution
US7183205B2 (en) 2004-06-08 2007-02-27 Macronix International Co., Ltd. Method of pitch dimension shrinkage
US7473644B2 (en) 2004-07-01 2009-01-06 Micron Technology, Inc. Method for forming controlled geometry hardmasks including subresolution elements
US7396767B2 (en) * 2004-07-16 2008-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure including silicide regions and method of making same
US7518182B2 (en) 2004-07-20 2009-04-14 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
US7176125B2 (en) * 2004-07-23 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a static random access memory with a buried local interconnect
KR100704470B1 (ko) 2004-07-29 2007-04-10 주식회사 하이닉스반도체 비결정성 탄소막을 희생 하드마스크로 이용하는반도체소자 제조 방법
US7122425B2 (en) 2004-08-24 2006-10-17 Micron Technology, Inc. Methods of forming semiconductor constructions
US7151040B2 (en) 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7442976B2 (en) 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7910288B2 (en) 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7042047B2 (en) 2004-09-01 2006-05-09 Micron Technology, Inc. Memory cell, array, device and system with overlapping buried digit line and active area and method for forming same
US7547945B2 (en) 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7285812B2 (en) 2004-09-02 2007-10-23 Micron Technology, Inc. Vertical transistors
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7115525B2 (en) 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
JP4771271B2 (ja) 2004-09-24 2011-09-14 トヨタ自動車株式会社 単電池、単電池の製造方法、燃料電池、燃料電池の製造方法
US20060073613A1 (en) * 2004-09-29 2006-04-06 Sanjeev Aggarwal Ferroelectric memory cells and methods for fabricating ferroelectric memory cells and ferroelectric capacitors thereof
KR100614651B1 (ko) 2004-10-11 2006-08-22 삼성전자주식회사 회로 패턴의 노광을 위한 장치 및 방법, 사용되는포토마스크 및 그 설계 방법, 그리고 조명계 및 그 구현방법
US7098536B2 (en) * 2004-10-21 2006-08-29 International Business Machines Corporation Structure for strained channel field effect transistor pair having a member and a contact via
US20060094180A1 (en) * 2004-11-02 2006-05-04 Intel Corporation Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode
US7214629B1 (en) 2004-11-16 2007-05-08 Xilinx, Inc. Strain-silicon CMOS with dual-stressed film
US7208379B2 (en) 2004-11-29 2007-04-24 Texas Instruments Incorporated Pitch multiplication process
US7476920B2 (en) 2004-12-15 2009-01-13 Infineon Technologies Ag 6F2 access transistor arrangement and semiconductor memory device
KR100596795B1 (ko) 2004-12-16 2006-07-05 주식회사 하이닉스반도체 반도체 소자의 캐패시터 및 그 형성방법
US7432553B2 (en) 2005-01-19 2008-10-07 International Business Machines Corporation Structure and method to optimize strain in CMOSFETs
US7238580B2 (en) 2005-01-26 2007-07-03 Freescale Semiconductor, Inc. Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration
US7271107B2 (en) 2005-02-03 2007-09-18 Lam Research Corporation Reduction of feature critical dimensions using multiple masks
US7163853B2 (en) * 2005-02-09 2007-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a capacitor and a metal gate on a semiconductor device
US7227331B2 (en) 2005-02-14 2007-06-05 International Rectifier Corporation Safety interlock and protection circuit for permanent magnet motor drive
US7390746B2 (en) 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7253118B2 (en) 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7659203B2 (en) * 2005-03-18 2010-02-09 Applied Materials, Inc. Electroless deposition process on a silicon contact
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
KR100640639B1 (ko) 2005-04-19 2006-10-31 삼성전자주식회사 미세콘택을 포함하는 반도체소자 및 그 제조방법
JP2006313784A (ja) * 2005-05-06 2006-11-16 Nec Electronics Corp 半導体装置およびその製造方法
US7214621B2 (en) * 2005-05-18 2007-05-08 Micron Technology, Inc. Methods of forming devices associated with semiconductor constructions
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7547599B2 (en) 2005-05-26 2009-06-16 Micron Technology, Inc. Multi-state memory cell
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7541632B2 (en) 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
US8338887B2 (en) * 2005-07-06 2012-12-25 Infineon Technologies Ag Buried gate transistor
US7413981B2 (en) 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US7291560B2 (en) 2005-08-01 2007-11-06 Infineon Technologies Ag Method of production pitch fractionizations in semiconductor technology
US7816262B2 (en) 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7829262B2 (en) 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7776744B2 (en) 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7572572B2 (en) 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US8716772B2 (en) 2005-12-28 2014-05-06 Micron Technology, Inc. DRAM cell design with folded digitline sense amplifier
US7807536B2 (en) 2006-02-10 2010-10-05 Fairchild Semiconductor Corporation Low resistance gate for power MOSFET applications and method of manufacture
US20070210449A1 (en) 2006-03-07 2007-09-13 Dirk Caspary Memory device and an array of conductive lines and methods of making the same
US7537866B2 (en) 2006-05-24 2009-05-26 Synopsys, Inc. Patterning a single integrated circuit layer using multiple masks and multiple masking layers
US8129289B2 (en) 2006-10-05 2012-03-06 Micron Technology, Inc. Method to deposit conformal low temperature SiO2

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0967643B1 (en) * 1998-06-22 2006-12-13 International Business Machines Corporation Method of providing low-resistance salicide fill for trench capacitors
US6465309B1 (en) * 2000-12-12 2002-10-15 Advanced Micro Devices, Inc. Silicide gate transistors

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
hong-xiang mo, et al.formation and properties of ternary silicide (CoxNi1-x)Si2 thinfilms.IEEE.1998,271-274.
hong-xiang mo, et al.formation and properties of ternary silicide (CoxNi1-x)Si2 thinfilms.IEEE.1998,271-274. *
J.liu, et al.dual-work-function metal gates by full silicidation of poly-si with co-ni bi-layers.IEEE electron device letters26 4.2005,26(4),228-230.
J.liu, et al.dual-work-function metal gates by full silicidation of poly-si with co-ni bi-layers.IEEE electron device letters26 4.2005,26(4),228-230. *
莫鸿翔 等.三元硅化物（CoxNi1-x）Si2薄膜的制备及特性.微细加工技术1 1.1999,1(1),16-18.
莫鸿翔 等.三元硅化物(CoxNi1-x)Si2薄膜的制备及特性.微细加工技术1 1.1999,1(1),16-18. *

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