CN101312031B - Display device and semiconductor device - Google Patents
Display device and semiconductor device Download PDFInfo
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- CN101312031B CN101312031B CN2008101251779A CN200810125177A CN101312031B CN 101312031 B CN101312031 B CN 101312031B CN 2008101251779 A CN2008101251779 A CN 2008101251779A CN 200810125177 A CN200810125177 A CN 200810125177A CN 101312031 B CN101312031 B CN 101312031B
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Abstract
This invention provides a display device of high definition, multiple colors and low power consumption includes a display panel 110, a scanning circuit 109 and a data line driving circuit. The external of the display panel includes a controller IC102 having a display memory for storing display data, an output buffer 112 for reading data out of the display memory and outputting this data to the display panel, and a controller 113 for controlling the display memory and output buffer and communication with the host device; the display panel is provided with a DAC circuit 106, which forms part ofthe data-line driver, for converting display data represented by a digital signal to an analog signal; the width of a bus for data transfer between the controller IC 102 and data-line driver of the display panel is such that data of a greater number of bits is transferred in parallel by a single transfer than is transferred by the bus between the controller and the host device. This allows the operating frequency of the data-line driver to be reduced.
Description
The application be submitted on October 8th, 2002, application number be 02144327.0, denomination of invention divides an application for the application of " display device ".
Technical field
The present invention relates to the display device of employing among projector, notebook computer, monitor, mobile phone, the PDA etc., particularly relate to voltage driven type display device and current-driven displays such as liquid crystal indicator.
Background technology
Development along with multimedia era, display device is from the midget plant of the view finder that is used for projector, video camera and mobile phone (mabile phone) etc., to the display screen of automotive tv and navigational system, PDA (Personal Digital Assistants), and the middle-scale device of portable PC usefulness such as portable terminal such as (Personal Computer), the large-scale plant of usefulness such as notebook computer, monitor is popularized just fast.In these display device, liquid crystal indicator is used in product group the most widely now.Particularly by thin film transistor (TFT) (Thin FilmTransistor (below be abbreviated as " TFT ")) etc. the active array type LCD that drives, owing to compare with simple matrix type liquid crystal indicator, can obtain high resolving power, high picture quality, and become the main flow of liquid crystal indicator.TFT is divided into non-crystalline silicon tft and multi-crystal TFT because of the difference of employed semiconductor material.
Non-crystalline silicon tft is not owing to need high-temperature technology, so can adopt substrate manufacture display screen such as glass.
Multi-crystal TFT always because of need the quartz base plate of high price with high-temperature technology, only is defined in display screen small-sized and that surcharge is high.In the last few years; along with development of technology such as laser annealings; developed by decompression (LP) CVD, plasma (P) CVD, sputtering method etc.; form precursor film; it is used the laser annealing multiple crystallization; and under the low temperature that can use glass basis plate etc., can form the technology of multi-crystal TFT, display screen medium-sized and that notebook computer is used also can have been made of multi-crystal TFT.
The degree of excursion of multi-crystal TFT, with non-crystalline silicon tft relatively, high one more than the order of magnitude, the current driving ability height.
When constituting liquid crystal indicator with multi-crystal TFT, because the current driving ability of multi-crystal TFT is strong, the institute so that peripheral circuit and pixel be integrated on the same substrate, so the quantity of LSI (LargeScale Integrated Circuit) reduces, miniaturization can be realized, installation cost can be reduced.
Like this, peripheral circuit incorporate liquid crystal indicator on same substrate is called " integral with drive circuit liquid crystal indicator ".
The integral with drive circuit liquid crystal indicator, what popularize the most as peripheral circuit is to have data driver that the data line that is connected on the pixel TFT source terminal is driven, and the form of gate drivers that the gate line that is connected on the pixel TFT gate terminal is driven, at the liquid crystal projector that requires small-sized and high-precision liquid crystal indicator and require in the portable notebook computer that the edge edge dwindles etc. use more.
In existing liquid crystal indicator, do not make in the driving circuit integrated drive device, gate drivers LSI chip group, gate drivers LSI chip group, controller, and DC-DC transducer etc. are arranged on TCP (Tape Carrier Package) and flexible substrate or the connecting circuit substrate.In this structure, height become more meticulous and many gray processings in, complicated, and the increase of edge edge that can't avoid installing.Simultaneously because the increase of frequency makes EMI (ElectroMagnetic Interference: problem increase wave interference).Therefore the element material configuration change of the reinforcement of using the printed base plate ground wire, printed base plate, and distribution draw the increase of change, electromagnetic interface filter and improve interface etc. and aspect the noise measure, will pay a lot of effort.
In contrast to this, the one of peripheral circuit incorporate driving circuit on same substrate is then installed easily, even and height becomes more meticulous and the development of many gray processings, edge edge size also changes hardly, is very effective as portable applications therefore.
Figure 37 is the display system synoptic diagram of the existing general integral with drive circuit liquid crystal indicator of expression.According to Figure 37, in existing integral with drive circuit liquid crystal indicator, press rectangular wiring, the Active Matrix LCD At zone 110 that disposes the capable N row of M pixel, line direction sweep circuit (sweep trace (gate line) driving circuit) 109, column direction sweep circuit (data line drive circuit) 3504, analog switch 3505, reach level shifter 3503 etc., on display device substrate 101, form by multi-crystal TFT is integrated.
Analog switch 3503 has with the bar of the column direction data line in Active Matrix LCD At zone 110 counts the identical output number of N.
In addition, in existing integral with drive circuit liquid crystal indicator, also there is the inner more device of complicated circuit form such as DAC circuit that is equipped with.Figure 38 represents the display system synoptic diagram of the liquid crystal indicator of existing interior dress DAC circuit type.The liquid crystal indicator of dress DAC circuit type in existing, except not adorning the same Active Matrix LCD At zone 110 of Figure 37 device of DAC circuit, line direction sweep circuit 109, the column direction sweep circuit 3506 circuit below also forming on the display device substrate 101 by the capable N row of the arrangement M pixel of rectangular wiring with inside.That is, on display device substrate 101, form data register 3507, latch cicuit 105, DAC circuit 106, selector circuit 107, level shifter/timing impact damper 108, reach level shifter etc.
This does not comprise the DAC circuit in constituting in the controller IC of interior device, memory, storer 111, output buffer 112, controller 113 all are made of digital circuit.Consequently owing to just making, so the price of IC is than the driver IC low price of device, memory in above-mentioned without the technology of mimic channel.
Slim, the light weight of above-mentioned liquid crystal indicator, and compare with CRT (Cathode Ray Tube) pipe, consumed power is low.Bring into play such characteristics, liquid crystal indicator is installed on the portable information processing device.
In the last few years, along with mobile phone, and the popularizing fast of portable terminal devices such as PDA or mobile PC, the demand of the display of portable (moving) purposes was further improved.In the display of this portable terminal, following requirement is for example arranged.
(1), display unit area is in addition dwindled in order to improve Portability.
(2) the battery-operated mode of general employing in portable terminal in order to prolong the once battery-operated duration of charging, requires low power consumption.
(3) the popularizing of portable terminal, also require price low, so portable display also requires low cost.
And, wish liquid crystal indicator that these require to pass through integral with drive circuit and organic EL (Electro Luminescence: electroluminescence) realization such as device.
Low power consumption as dress peripheral circuit type LCD in measuring, miniaturization, the device that height becomes more meticulous, for example opened the spy and disclose signal end peripheral circuit and the scanning end peripheral circuit that on the TFT substrate, is formed for driving liquid crystal in the flat 11-202290 communique, reach the coupling arrangement that on signal routing, has the trunk bus that is used for the transmitting and displaying data, on liquid crystal indicator, install by this coupling arrangement and make the video data that writes from CPU store the video memory of 1 row amount at least and form the video memory chip of read-out control circuit, carry out the device that parallel transmission constitutes with the clock of low speed from each row video data of video memory chip output.
Summary of the invention
Problem to above-mentioned existing display device describes below.
The 1st problem is that the height along with display becomes more meticulous and many gray processings, and the price of driver IC and power consumption are risen.
Its reason is for Liquid Crystal Module, must carry out the serial high-speed transfer to the video data of whole pixels at per 1 frame time.Highly more become more meticulous, number of picture elements is many more, transfer rate at this moment increases more.The result of high-speed transfer is, driver IC is also required high speed, produces perforation electric current etc. on a plurality of CMOS of forming circuit device, and power consumption increased when operating rate rose.In addition, the IC price of carrying out high speed operation also increases.And when grey increased, the complicated and transmission speed that circuit constitutes further increased, and caused the increase of further increase of power consumption and cost.In addition, as mentioned above, the IC of interior dress DAC circuit etc. need and use other technology, thereby cost is further increased.
The 2nd problem is from all power consumption of inhibition system and the necessity of price, limit number of picture elements and grey.
Its reason is: when number of picture elements and grey increase, the power consumption of driver IC increases as mentioned above.
The 3rd problem is because high-frequency work has problem on reliability.
Its reason is: when making low temperature polycrystalline silicon TFT carry out high-frequency work, the TFT characteristic changes easily.
The 4th problem is the voltage difference of using owing to each circuit block on the display screen substrate, so need and use the technology corresponding to most voltages.
In addition, when the frequency of input signal improved, the problem of EMI was very big.Its reason is the direct drive source driver of incoming frequency IC.The result is, parasitism (Spurious) electric wave that produces from the square wave of driving circuit increases, and the EMI noise also increases.Therefore as mentioned above, in measure, paid very big effort to various EMI.
On the other hand, when the noise level of EMI very hour, various reference tests can pass through easily, not only reliability can improve, and also can reduce with EMI test cost related.
Thereby the present invention proposes in view of the above problems, and its purpose is to provide low cost, low power consumption, and realizes the display device that high meticulous, many gray scales show.
Another object of the present invention provides the display device that makes reliability high.
Another purpose of the present invention provides the display device that suppresses the EMI influence.
A further object of the present invention provides not and uses the technology to most voltages, and by just can drive the display device of the integral with drive circuit of whole circuit to a kind of technology of voltage.
In order to achieve the above object, display device involved in the present invention comprises on a face (side): display screen has that pixel clusters is configured to rectangular display unit on the intersection point of many data lines and multi-strip scanning line; Scan line drive circuit is to above-mentioned multi-strip scanning line making alive successively; And data line drive circuit, receive the video data of supplying with from epigyny device, will be added on above-mentioned many data lines corresponding to the signal of above-mentioned video data; Outside at above-mentioned display screen has controller IC, and this controller IC comprises: the display-memory of storage video data, from above-mentioned display-memory sense data and to communicating by letter and the controller of control between output buffer, the above-mentioned display-memory of control and the above-mentioned output buffer of the output of above-mentioned display screen and management and above-mentioned epigyny device; On above-mentioned display screen, have a part that constitutes above-mentioned data line drive circuit, and will be transformed to the digital to analog conversion circuit (being called " DAC circuit ") of simulating signal from the video data of the digital signal that above-mentioned control device transferred out; Data transmission highway width between above-mentioned controller IC and the above-mentioned display screen than bus between above-mentioned controller and the above-mentioned epigyny device, but once transmits more long numeric data of parallel transmission.In the present invention, because the highway width of data transmission strengthens, reduced the frequency of operation of data line drive circuit, like this, constitute the transistor device of the peripheral circuit that comprises data line drive circuit and scan line drive circuit, form with identical technology with the TFT (Thin Film Transistor) of formed pixel switch on the above-mentioned display screen of formation, the thickness of the gate insulating film of the transistor device of above-mentioned peripheral circuit is set at identical with the thickness of the TFT gate insulating film of the pixel switch of high voltage drive.
In addition, the present invention on another side, on above-mentioned display screen, have the storage video data display-memory, and the video data of digital signal is transformed to the digital to analog conversion circuit (claim " DAC circuit ") of simulating signal.Among the present invention, DAC circuit and display-memory form technology with the TFT (Thin Film Transistor) of pixel unit and form with identical technology.
Display device involved in the present invention, has the video data that reception is supplied with from epigyny device, to be added to the data line drive circuit on the data line corresponding to the signal of video data, it is characterized in that: video data is being carried out in the circuit of phase demodulation at least, the wiring of transmitting display signal therefor does not intersect with the wiring of other shows signal of transmission.
Display device involved in the present invention, has the video data that reception is supplied with from epigyny device, this video data is carried out the circuit of phase demodulation, it is characterized in that: certain signal wire of the signal before the transmission phase demodulation, intersect to count and (k-1)/2 lack with other signal wires intersect than C=n (n-1), wherein, n represents the video data supplied with and line number, k * n represent behind the phase demodulation video data and line number.
Semiconductor device involved in the present invention, has the video data that reception is supplied with from epigyny device, this video data is carried out the circuit of phase demodulation, it is characterized in that: certain signal wire of the signal before the transmission phase demodulation, intersect to count and (k-1)/2 lack with other signal wires intersect than C=n (n-1), wherein, n represents the video data supplied with and line number, k * n represent behind the phase demodulation video data and line number.
Among the present invention, in above-mentioned display screen, have with above-mentioned DAC circuit and be output as input, on the data line-group, connect the selector circuit of output.Among the present invention, have the signal amplitude of stipulating by the supply voltage of above-mentioned controller IC in above-mentioned display screen, level shift is to the high-tension level shifter of above-mentioned display screen end.Among the present invention, in above-mentioned display screen, have the serial parallel change-over circuit that serial data is converted to parallel data, on above-mentioned DAC circuit, supply with and convert parallel data to by above-mentioned serial parallel change-over circuit.From following embodiment narration, the practitioner is understood, the present invention of the every claim by patent claim can achieve the above object.
The simple declaration of accompanying drawing
Fig. 1 is the display device pie graph of expression the present invention the 1st embodiment.
Fig. 2 is the figure that regularly moves for the display device of explanation the present invention the 1st embodiment.
Fig. 3 is that expression is for the driver IC of interior device, memory and the controller IC of interior device, memory, the figure that the memory span of interior dress and IC cost concern.
Fig. 4 is the figure of expression read frequency and interface circuit consumed power relation.
Fig. 5 is the display device pie graph of expression the present invention the 2nd embodiment.
Fig. 6 is the display device pie graph of expression the present invention the 3rd embodiment.
Fig. 7 is the display device pie graph of expression the present invention the 4th embodiment.
Fig. 8 is the display device pie graph of expression the present invention the 5th embodiment.
Fig. 9 is the figure that regularly moves for the display device of explanation the present invention the 5th embodiment.
Figure 10 is the display device pie graph of expression the present invention the 6th embodiment.
Figure 11 is the display device pie graph of expression the present invention the 7th embodiment.
Figure 12 is the figure that regularly moves for the display device of explanation the present invention the 7th embodiment.
Figure 13 is the display device pie graph of expression the present invention the 8th embodiment.
Figure 14 is the display device pie graph of expression the present invention the 9th embodiment.
Figure 15 is the display device pie graph of expression the present invention the 10th embodiment.
Figure 16 is the figure that regularly moves for the display device of explanation the present invention the 10th embodiment.
Figure 17 is the display device pie graph of expression the present invention the 11st embodiment.
Figure 18 is the display device pie graph of expression the present invention the 12nd embodiment.
Figure 19 is the figure that regularly moves for the display device of explanation the present invention the 12nd embodiment.
Figure 20 is the display device pie graph of expression the present invention the 13rd embodiment.
Figure 21 is the display device pie graph of expression the present invention the 14th embodiment.
Figure 22 is the display device pie graph of expression the present invention the 15th embodiment.
Figure 23 is the display device pie graph of expression the present invention the 16th embodiment.
Figure 24 is the figure that regularly moves for the display device of explanation the present invention the 16th embodiment.
Figure 25 is the display device pie graph of expression the present invention the 17th embodiment.
Figure 26 is the display device pie graph of expression the present invention the 18th embodiment.
Figure 27 is the figure that regularly moves for the display device of explanation the present invention the 18th embodiment.
Figure 28 is the display device pie graph of expression the present invention the 19th embodiment.
Figure 29 is the display device pie graph of expression the present invention the 20th embodiment.
Figure 30 is the display device pie graph of expression the present invention the 21st embodiment.
Figure 31 is the figure that regularly moves for the display device of explanation the present invention the 21st embodiment.
Figure 32 is the display device pie graph of expression the present invention the 22nd embodiment.
Figure 33 is the display device pie graph of expression the present invention the 23rd embodiment.
Figure 34 is the display device pie graph of expression the present invention the 24th embodiment.
Figure 35 is the sectional drawing for the master operation of the explanation display screen substrate that embodiments of the invention adopted making.
Figure 36 is the sectional drawing for the master operation of the explanation display screen substrate that embodiments of the invention adopted making.
Figure 37 is the figure that the display system summary of existing integral with drive circuit liquid crystal indicator is adopted in expression.
Figure 38 be expression adopt existing in the figure of display system summary of integral with drive circuit liquid crystal indicator of dress DAC circuit.
Figure 39 represents as a comparative example, uses the pie graph of the display device of existing structure design.
Figure 40 is the circuit diagram of the shift register of expression Figure 39.
Figure 41 be expression Figure 39 6 bit data register and with the circuit diagram of the digital data bus that is connected.
Figure 42 is that 6 * 66 of expression Figure 39 loads the circuit diagram that latchs.
Figure 43 is the signal timing diagram of importing on the shift-register circuit of Figure 39 and the digital data bus.
Figure 44 is the circuit diagram of the existing level shifting circuit of expression.
Figure 45 is the block scheme that the display device of the expression embodiment of the invention constitutes.
Figure 46 is the circuit diagram that has the 1-to-2 serial parallel change-over circuit of level conversion function in the embodiment of the invention shown in expression Figure 45.
Figure 47 is the sequential chart of the 1-to-2 serial parallel change-over circuit timing waveform shown in expression Figure 46.
Figure 48 is the graph of measured results of the maximum operation frequency of the 1-to-2 serial parallel change-over circuit among expression Figure 46.
Figure 49 is the curve map that the level conversion portion that is comprised among Figure 46 and the consumed power between the existing level shifting circuit shown in Figure 44 are compared.
Figure 50 is to the situation that integrated digital signal processing portion consumed power compares on display base plate of the display device shown in the display device shown in Figure 39 and Figure 45.
Embodiment
Below inventive embodiment is described.Display device involved in the present invention comprises in display device in an embodiment of its best: have the display unit that is configured to rectangular pixel unit on the intersection point of many data lines and multi-strip scanning line (Fig. 1 110); To the alive successively scan line drive circuit of above-mentioned multi-strip scanning line (Fig. 1 109); The video data that reception is supplied with from epigyny device will be added to the data line drive circuit of above-mentioned many data lines corresponding to the signal of above-mentioned video data.Outside display device substrate (Fig. 1 101), have controller IC (Fig. 1 102), comprising: storage corresponding to the display-memory of the video data of above-mentioned pixel unit (Fig. 1 111); From the display-memory sense data and to the output buffer of display device substrate (Fig. 1 101) output (Fig. 1 112); And display-memory (Fig. 1 111) and output buffer (Fig. 1 112) controlled communicating by letter and the controller of control (Fig. 1 113) between management and epigyny device.A part that on display device substrate (Fig. 1 101), has the composition data line drive circuit, the video data of digital signal is transformed to DAC (digital to analog conversion) circuit (Fig. 1 106) of simulating signal, data transmission between the data line drive circuit on controller IC (Fig. 1 102) and the display device substrate (Fig. 1 101) is with the width of bus, compare with the bus between controller (Fig. 1 113) and the above-mentioned epigyny device (Fig. 1 114), but the more bit data of parallel transmission once.
In more detail, display device involved in the present invention is in an embodiment of its best, have display device substrate (Fig. 1 101) and on the intersection point of many data lines (N bar) and multi-strip scanning line (M bar), be configured to the display unit (Fig. 1 110) of the capable N row of rectangular M pixel clusters, except that display device substrate (Fig. 1 101), has controller IC (Fig. 1 102), comprising: storage (the B position gray scale video data of individual pixel of M * N) (the i.e. display-memory of (M * N * B)) (Fig. 1 111), from display-memory (Fig. 1 111) sense data and to the output buffer of display screen substrate (Fig. 1 101) side output (Fig. 1 112), and display-memory (Fig. 1 111) and output buffer (Fig. 1 112) controlled communicating by letter and the controller of control (Fig. 1 113) between management and epigyny device.
In controller IC (Fig. 1 102), the quantity of output buffer (Fig. 1 112) configuration is, will be equivalent to storer (in the position of M * N * B) 1 row amount (position of N * B) is by { (N * B)/S} of cutting apart that several S cut apart of piece.
The output buffer of slave controller IC (Fig. 1 102) (Fig. 1 112), by the { (data bus of N * B)/S} bit width, to display device substrate (Fig. 1 a 101) side, with (N * B)/the S} position is a unit, in 1 horizontal period, cut apart above-mentioned and cut apart several S time, transmission 1 row video data.
On display device substrate (Fig. 1 101), have: data line drive circuit, comprising: the signal amplitude that will receive from above-mentioned data bus to the signal of high amplitude more carry out the level shifter of level shift (Fig. 1 104), the B position output of latch cicuit that the output of this level shifter is latched (Fig. 1 105), input latch circuit, the DAC circuit (Fig. 1 106) of output simulating signal, be output as input, have the N outlet selector identical (Fig. 1 107) with above-mentioned display unit N row with the DAC circuit; And to the alive successively scan line drive circuit of above-mentioned multi-strip scanning line (gate line) (Fig. 1 109).Level shifter (Fig. 1 104) and latch cicuit (Fig. 1 105) all dispose { (N * B)/S}, DAC circuit (Fig. 1 106) configuration (N/S) is individual, selector circuit (Fig. 1 107) receives the output of (N/S) individual DAC circuit (Fig. 1 106), according to the selector control signal of being imported, each above-mentioned DAC circuit output, by 1 horizontal period is cut apart the time that several S are cut apart with above-mentioned, supply with data-signal to S bar data line successively, the controller of controller IC (Fig. 1 113) to the level shifter of (Fig. 1 101) on the display device substrate regularly impact damper (Fig. 1 108) supply with clock signal, by level shifter regularly the latch clock signal and the selector control signal of impact damper (Fig. 1 the 108) output of boosting, supply with above-mentioned latch cicuit (Fig. 1 105) and selector circuit (Fig. 1 107) respectively.
In one embodiment of this invention, constitute the transistor device of the peripheral circuit be included in the data line drive circuit that forms on the display device substrate and scan line drive circuit, form with identical technology with the TFT (Thim Film Transistor) of the formation pixel switch that forms on the display unit, preferably constitute by multi-crystal TFT.Be the thickness of gate insulating film of the transistor device of data line drive circuit and above-mentioned scan line drive circuit, the thickness of TFT gate insulating film that is set at pixel switch with high voltage drive etc. is identical.
In an embodiment of the present invention, its constitute also can have two of display unit to scan line drive circuit (Fig. 5 109), and data line drive circuit supply with the level shifter/timing impact damper (Fig. 5 108) of clock signal.
In an embodiment of the present invention, latch cicuit and level shifter at last formation of display device substrate (101) and composition data line drive circuit also can exchange its position (with reference to Fig. 6).
In an embodiment of the present invention, the signal amplitude of the signal amplitude that can make controller IC (Fig. 7 102) and display device substrate (Fig. 7 101) is identical.On display device substrate (Fig. 7 101), can omit level shift circuit.
In an embodiment of the present invention, for the driving pixel device of drive current, it constitutes and also can have generation corresponding to the electric current of video data gray scale and to the current/charge-voltage convertor/electric current output buffer of data line supplying electric current (Fig. 8, Figure 15 801), demoder and electric current output buffer (Figure 10, Figure 17 1001 and 1002).
In an embodiment of the present invention, it constitutes also can be with the output buffer of controller IC (Figure 11, Figure 29 102) (Figure 11, Figure 13 112) configuration (N * B) individual, slave controller IC is by (the data bus of bit width of N * B), to display device substrate (Figure 11, Figure 13 a 101) side, so that (N * B) position is a unit, at 1 horizontal period 1 time transmission, 1 row video data, make DAC circuit (Figure 11, Figure 13 106) have N corresponding to data line.In described formation, the signal amplitude of the signal amplitude that can make controller IC (Figure 14, Figure 29 102) and display device substrate (Figure 14, Figure 29 101) is identical.In display device substrate (Figure 14 101), can omit level shift circuit.
In an embodiment of the present invention, it constitutes also can have the serial parallel change-over circuit (Figure 18, Figure 20～Figure 23, Figure 25, Figure 26, Figure 28～Figure 30, Figure 32～Figure 34 1801) that serial data is converted to parallel data on display device substrate (101), the DAC circuit is supplied be converted to parallel data by the serial parallel change-over circuit.Owing to will convert the input of data (it is carried out the signal of latched signal and/or level shift) the supply DAC circuit of parallel position by the serial parallel change-over circuit to, so can reduce the frequency of operation of DAC circuit.
Display device involved in the present invention in another embodiment, on display screen (Figure 33, Figure 34 101), have the DAC circuit (Figure 33 106), and the display-memory of storage video data (Figure 33, Figure 34 111) that the video data of digital signal are transformed to simulating signal, above-mentioned DAC circuit and display-memory are used and are formed the identical technology of technology with the TFT (Thin FilmTransistor) of pixel unit and form.
In more detail, display device involved in the present invention, in another embodiment, display device substrate (Figure 33 101) is comprising on the same substrate: have on the intersection point of many data lines (N bar) and multi-strip scanning line (M bar) display unit by the pixel clusters of the capable N row of rectangular configuration M (Figure 33 110), storage (the B position gray scale video data of individual pixel of M * N) (the i.e. storer of (M * N * B)) (Fig. 3 111), from the display-memory sense data and to the output buffer of above-mentioned display screen substrate one side output (Figure 33 112), and control display-memory (Figure 33 111) and output buffer (Figure 33 112), and communicate by letter between management and epigyny device and the controller controlled (Figure 33 113).The configuration quantity of output buffer (Figure 33 112), will be equivalent to above-mentioned storer (Figure 33 111) (in the position of M * N * B) 1 row amount (quantity of cutting apart the position several S by piece of N * B) and P { (N * B)/(P * S) } cut apart mutually are individual.
Display device substrate (Figure 33 101) has: data line drive circuit, comprising: with the output serial input of output buffer (Figure 33 112), and the serial parallel change-over circuit of P phase demodulation output (Figure 33 1801), the latch cicuit that the output of serial parallel change-over circuit (Figure 33 1801) is latched (Figure 33 105), import the B position output of above-mentioned latch cicuit, the DAC circuit (Figure 33 106) of output simulating signal, and with the output of DAC circuit as input, have the selector switch (Figure 33 107) of the N output identical with the N row of above-mentioned display unit; And to the alive successively scan line drive circuit of above-mentioned multi-strip scanning line (Figure 33 109).Serial/row change-over circuit (Figure 33 1081) configuration (N * B)/(P * S) } individual, { (N * B)/S} of latch cicuit (Figure 33 105) configuration, DAC circuit (Figure 33 106) configuration (N/S) is individual, selector circuit (Figure 33 107) receives the output of (N/S) individual DAC circuit (Fig. 3 106), according to selector control signal, the output of each DAC circuit is cut apart several time by being divided into above-mentioned, successively S bar data line-group is supplied with data-signal.Slave controller (Figure 33 113) is supplied with the latch clock signal to latch cicuit (Figure 33 105), selector circuit (Figure 33 107) is supplied with selector control signal, serial-to-parallel converter circuit (Figure 33 1801) is supplied with the parallel changeover control signal of serial.
In this embodiment, constitute the TFT of the peripheral circuit that comprises data line drive circuit, scan line drive circuit, form with identical technology with the pixel switch TFT of display unit.In the invention of every claim of patent claim, some claims are corresponding with accompanying drawing, and its corresponding relation is: claim 11 corresponding diagram 1, claim 12 corresponding diagram 6, claim 13 corresponding diagram 7, claim 14 corresponding diagram 8, the corresponding Figure 10 of claim 15, the corresponding Figure 11 of claim 16, the corresponding Figure 13 of claim 17, the corresponding Figure 14 of claim 18, the corresponding Figure 15 of claim 19, the corresponding Figure 17 of claim 20, the corresponding Figure 18 of claim 21, the corresponding Figure 21 of claim 22, the corresponding Figure 22 of claim 23, the corresponding Figure 23 of claim 24, the corresponding Figure 25 of claim 25, the corresponding Figure 26 of claim 26, the corresponding Figure 28 of claim 27, the corresponding Figure 29 of claim 28, the corresponding Figure 30 of claim 29, the corresponding Figure 32 of claim 30, the corresponding Figure 33 of claim 31, the corresponding Figure 34 of claim 32, the corresponding Figure 35 of claim 33 to 35,36.
Embodiment
With reference to the accompanying drawings embodiments of the invention are illustrated in greater detail.
Fig. 1 represents the pie graph of the 1st embodiment of the present invention.Describe the 1st embodiment of the present invention in detail with reference to Fig. 1.With reference to Fig. 1, the present invention the 1st embodiment by system side circuitry substrate 103, controller IC 102, and display device substrate 101 constitute.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, reaches output buffer 112, is connected with circuit system substrate 103 and display device substrate 101.Display device substrate 101 inside are equipped with level shifter/timing impact damper (controller) 106, sweep circuit (scan line drive circuit) 109, level shifter 104, latch cicuit 105, DAC circuit 106, are selected circuit 107 and display unit 110, are connected with controller IC 102.Level shifter circuit 104, latch cicuit 105, DAC circuit 106, selection circuit 107 dispose in the following order, select circuit 107 to be connected row one side of display 110, the output of level shifter circuit 104 is latched by latch cicuit 105, the output of latch cicuit 105 is transformed into simulating signal by DAC circuit 106, by selecting circuit 107, output to the data line of display unit 110.
On the display unit 110 of present embodiment, carry out the capable N row of M Active Matrix LCD At with gray scale figure place B.Storer 111 has the (capacity of the position of M * N * B).Select circuit 107, identical with display unit 110 row end input numbers have N output.
Level shifter 104 and latch cicuit 105 are identical with output buffer 112, by { (circuit of N * B)/S} figure place constitutes.Level shifter 104 and latch cicuit 105 are { (N * B)/S}.
DAC circuit 106 is made of (N/S) circuit (DAC), input gray level figure place B, and output is corresponding to the simulating signal of the digital value of each gray scale.
Fig. 2 is the figure in order to illustrate that the 1st embodiment of the present invention regularly moves.According to Fig. 2, when in 1 horizontal period, the output buffer 112 of slave controller IC102 is by the { (data bus of N * B)/S} position, when display device substrate 101 input input data signals, latch at the negative edge of the latch clock signal of supplying with latch cicuit.The result is that the output signal of latch cicuit 105 becomes the input signal to next DAC circuit 106.The latch clock signal is supplied with latch cicuit 105 from level shifter/timing impact damper 108.
Each data-signal carries out DA conversion (digital to analog conversion) by DAC circuit 106, forms the simulating signal corresponding to each gray scale digital value.
As the selector control signal of supplying with selector circuit 109, as shown in Figure 2, to piece cut apart several S (among Fig. 2, S=4) Liang wiring, gating pulse scans successively.Select control signal to supply with selector circuit 107 from level shifter/timing impact damper 108.
When this selector control signal is inputed to selector circuit 107, from the output signal of DAC circuit 106, select signal successively, be separated into piece and cut apart the signal of several S quantity (S bar), be transferred to the bar number and be each signal wire (data line) of the signal line-group that piece cuts apart several S.
By to the parallel signal of supplying with of such (N/S) individual ensemble, can be implemented in 1 horizontal period and supply with signal to the N signal line.
The signal of each gate line of the capable pixel switch of M of driving display unit 110, (M) supplies with from sweep circuit 109, keeps high level in 1 horizontal period, is low level during other.Such signal is scanned successively, and each gate line of M bar is supplied with signal.
In the present embodiment, according to the formation of Fig. 1 and Fig. 2, can the display unit 110 of the capable N row of M be shown.
Data-signal to the display unit 110 of the capable N of M row is a digital signal, according to the figure place B of digital gray scale, and (the data of position of M * N * B) of storage in storer 111.
Institute's data signals transmitted is carried out input data the boosting to high-voltage value (voltage amplitude) from the low-voltage amplitude on level shift circuit 104.
By this level shift circuit 104, because data transmission that need be under high voltage, so consumed power descends significantly.
In latch cicuit 105, as shown in Figure 2, data-signal is latched at the negative edge of the latch clock signal of supplying with latch cicuit 105.On latch cicuit 105, the signal of slave controller 113 outputs is supplied with as the latch clock signal to the signal that the high voltage amplitude boosts by level shifter/timing impact damper 108.This level shifter circuit 104 and latch cicuit 105, with identical from the figure place of output buffer 112 transmission, by (N * B)/handle the S} position.
DAC circuit 106 is made of (N/S) circuit, from imported { (data group of each the gray scale figure place B in N * B)/S} position carries out digital to analog conversion, obtains 1 simulating signal, and whole circuit is exported (N/S) bar (position) analog signal data thus.Promptly { (B output of N * B)/S} latch cicuit 105 inputs to a corresponding DAC106, from the analog voltage signal of DAC106 output corresponding to gradation data.
(N/B) bar (position) analog data signal of DAC106 according to selecting signal, is cut apart the time that S is cut apart by piece on selector circuit 107, select each output successively, supplies with data-signal to S bar (S=4 in Fig. 2) data line-group.
The result is to supply with data-signal to N bar data line.
When each data line of M bar is scanned, read corresponding data successively from storer 111, write to display unit 110 and show.
Below the 2nd embodiment of the present invention is described.Fig. 5 represents the pie graph of the present invention the 2nd embodiment.As shown in Figure 5, the 2nd embodiment of the present invention by system side circuitry substrate 103, controller IC 102, and display device substrate 101 constitute.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, reaches output buffer 112, is connected with circuit system substrate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, DAC circuit 106, selector circuit 107 are housed in the display device substrate 101, reach display unit 110, be connected with controller IC 102.Level shifter circuit 104, latch cicuit 105, DAC circuit 106, selector circuit 107 are arranged in this order, and selector circuit 107 is connected row one side of display unit 110.
Present embodiment is different with above-mentioned the 1st embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 are clipped in the middle display unit 110, are configured in relative both sides.Can reduce the gate drivers of sweep circuit 109 driving force, and eliminate delay between the gate line two ends.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit.Storer 111 has the (capacity of the position of M * N * B).In addition, row one side of selection circuit 107 and display unit 110 input number is identical has N to export.In output buffer 112, have and to be equivalent to the (({ (circuit of N * B)/S} bit quantity that N * B) carries out the position that piece cuts apart that several S quantity cut apart of 1 row amount in the position of M * N * B) of storer 111.Level shifter 104 and latch cicuit 105 are identical with output buffer 112, and the { (circuit of N * B)/S} figure place is arranged.DAC circuit 106 is made of (N/S) circuit.
Below the 3rd embodiment of the present invention is described.Fig. 6 represents the pie graph of the present invention the 3rd embodiment.In Fig. 6, the 3rd embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system substrate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, DAC circuit 106, selector circuit 107 and display unit 110 are housed in the display device substrate 101, are connected with controller IC 102.Latch cicuit 105, level shifter 104, DAC circuit 106, selector circuit 107 are by this series arrangement, and selector circuit 107 is connected row one side of display unit 110.
That is, in the present embodiment, the configuration of latch cicuit 105 and level shifter 104, different with the 1st embodiment.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit.
In addition, select circuit 107 to have the N output identical with the row one side input number of display unit 110.In output buffer 112, have be equivalent to storer 111 (in the position of M * N * B) 1 row amount (N * B) carries out the position the { (circuit of N * B)/S} figure place that piece is cut apart several S quantity.
Level shifter 104 and latch cicuit 105, identical with output buffer 112, the { (circuit of N * B)/S} figure place is arranged.DAC circuit 106 is by (N * B) circuit constitutes.
Present embodiment can certainly be same with the 2nd embodiment, level shifter/timing impact damper 108 and sweep circuit 109 is configured in the left and right sides of display unit 110.
Below the 4th embodiment of the present invention is described.Fig. 7 represents the pie graph of the present invention the 4th embodiment.In Fig. 7, the 4th embodiment of the present invention is made of system side circuitry substrate 130, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system substrate 103 and display device substrate 101.Regularly impact damper 701, sweep circuit 109, latch cicuit 105, DAC circuit 106, selector circuit 107 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Latch cicuit 105, DAC circuit 106, selector circuit 107 are arranged in this order, select circuit 107 to be connected row one side of display unit 110.
That is, there is not level shifter circuit 104 in present embodiment, replaces level shifter/timing impact damper 108, has disposed regularly impact damper 701, and this point is different with the 1st and the 3rd embodiment.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, selector circuit 107 has the N output identical with the row one side input number of display unit 110.In output buffer 112, have be equivalent to storer 111 (in the position of M * N * B) 1 row amount (N * B) carries out the position the { (circuit of N * B)/S} figure place that piece is cut apart several S quantity.Latch circuit 105 is identical with output buffer 112, and the { (circuit of N * B)/S} figure place is arranged.DAC circuit 106 is by (N * S) circuit constitutes.Present embodiment is the same with the 2nd embodiment, and regularly impact damper 701 and sweep circuit 109 can certainly be configured in the left and right sides of display unit 110.
Below the 5th embodiment of the present invention is described.Fig. 8 represents the pie graph of the present invention the 5th embodiment.In Fig. 8, the 5th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, DAC circuit 106, selector circuit 107, current/charge-voltage convertor/electric current output buffer 801 and display unit 110 are housed in the display device substrate 101, are connected with controller IC 102.Level shifter circuit 104, latch cicuit 105, DAC circuit 106, current/charge-voltage convertor/electric current output buffer 801, selector circuit 107 are arranged in this order, and selector circuit 107 is connected row one side of display unit 110.
That is, in the present embodiment, have current/charge-voltage convertor/electric current output buffer 801, this point is different with the 1st to the 4th embodiment.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale B on display unit.Storer 111 has the (capacity of the position of M * N * B).In addition, selector circuit 107 has the N output identical with the row one side input number of display unit 110, in output buffer 112, have be equivalent to storer 111 (in the position of M * N * B) 1 row amount (N * B) carries out the position the { (circuit of N * B)/S} figure place that piece is cut apart several S quantity.Level shifter 104 and latch cicuit 105, identical with output buffer 112, the { (circuit of N * B)/S} figure place is arranged.
DAC circuit 106 and current/charge-voltage convertor/electric current output buffer 801 is made of (N/S) circuit.Present embodiment is the same with the 2nd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 can certainly be configured in the left and right sides of display unit 110.
Present embodiment is different with the 1st to the 4th embodiment, owing to have current/charge-voltage convertor/electric current output buffer 801, can supply with data-signal with current drives to display device without driven.
Fig. 9 is the figure of the timing action of explanation the present invention the 5th embodiment.In Fig. 9,, latch at the negative edge of the latch clock signal of supplying with latch cicuit 105 when in 1 horizontal period during to display device substrate 101 input data signals.As a result, the output signal of latch cicuit 105 as shown in Figure 9.This signal becomes the input signal to next DAC circuit 106.
In DAC circuit 106, data-signal carries out DA conversion (digital to analog conversion), becomes the simulating signal corresponding to the digital value of each gray scale.This DAC output signal is converted to current signal by current/charge-voltage convertor/electric current output buffer 801 from voltage signal.
Selector control signal, the wiring of cutting apart several S (S=4 among Fig. 9) amount with piece is relative, and control scans by shown in Figure 9 successively with pulse.
When to selector circuit 107 these selector control signals of input, from the output signal of current/charge-voltage convertor/electric current output buffer 801, select signal successively, be separated into piece and cut apart the signal of several S quantity, being transferred to the bar number is each signal wire that piece is cut apart the signal line-group of several S.
Such signal line-group is the individual and all parallel signal of supplying with by (N/S), can be implemented in 1 horizontal period and supplies with signal to the N signal line.
Signal keeps high level in 1 horizontal period, is low level during in addition.Such signal is scanned successively, and each gate line of M bar is supplied with signal.
Present embodiment can show display unit 110 by the current signal of the capable N row of M by the formation of Fig. 8 and Fig. 9.Data-signal to the display unit of the capable N of M row is a digital signal, and according to the figure place B of digital gray scale, (data storage of the position of M * N * B) is in storer 111.In output buffer 112, cut apart several S and export owing to be divided into piece by each controlling grid scan line of M bar, so with (N * B)/S} position transmission data.As a result, compare with existing transmission method, can be with slow transmission speed transmission data.
Institute's data signals transmitted is carried out input data boosting to high-voltage value from low voltage value by level shift circuit 104.By this level shift circuit 104, do not need to carry out data transmission, so consumed power greatly reduces with high voltage.Latch cicuit 105 latchs data-signal as shown in Figure 9.This level shift circuit 104 and latch cicuit 105, identical with the figure place of being transmitted from output buffer 112, with (N * B)/handle the S} position.DAC circuit 106 is made of (N/S) circuit, from imported { (data group of each gray scale figure place B carries out digital to analog conversion in N * B)/S} position, obtain 1 simulating signal, thereby whole circuit is exported the analog signal data of (N/S).
Analog data signal that should (N/S) is transformed to current value by next voltage-to-current translation circuit/output buffer 801 from magnitude of voltage.This signal is divided into the time that piece is cut apart several S with per 1 on next selector circuit 107, supply with data-signal to selected S bar data line-group successively.
As a result, can supply with data-signal (1 row amount) to N bar data line.When scanning each gate line of M bar, carry out reading of data successively from storer 111, and write to display unit 111.
Below the 6th embodiment of the present invention is described.Figure 10 represents the pie graph of the present invention the 6th embodiment.In Figure 10, the 6th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114 herein, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, selector circuit 107, decoder circuit 1001, electric current output buffer 1002 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Level shifter circuit 104, latch cicuit 105, decoder circuit 1001, electric current output buffer 1002, selector circuit 107 are arranged in this order, and selector circuit 107 is connected row one side of display unit 110.
That is, in the present embodiment, do not have DAC circuit 106, and have decoder circuit 1001, electric current output buffer 1002, this point is different with the 1st to the 5th embodiment.Electric current output buffer 1002 is output current changeable types, and output is corresponding to the electric current of decoder circuit 1001 decoded results.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, selector circuit 107 has the N output identical with the row one side input number of display unit 110.In output buffer 112, have and to be equivalent to the (({ (circuit of N * B)/S} figure place that the position of N * B) cuts apart by piece that several S quantity cut apart of 1 row amount in the position of M * N * B) of storer 111.Level shifter 104 and latch cicuit 105, identical with output buffer 112, the { (circuit of N * B)/S} figure place is arranged.Decoder circuit 1001 and electric current output buffer 1002 are made of (N/S) circuit.Present embodiment is the same with the 2nd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 can certainly be configured in the left and right sides of display unit 110.
Below the 7th embodiment of the present invention is described.Figure 11 represents the pie graph of the present invention the 7th embodiment.In Figure 11, the 7th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.
Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, selector circuit 106 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Level shifter circuit 104, latch cicuit 105, DAC circuit 106 are arranged in this order, and DAC circuit 106 is connected row one side of display unit 110.Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has that (capacity of the position of M * N * B), DAC circuit 106 has the identical N output of row one side input number of display unit 110 in addition.((the circuit of figure place of N * B) that 1 row is measured in the position of M * N * B) that is equivalent to storer 111 is arranged in output buffer 112.Level shifter 104 and latch cicuit 105, identical with output buffer 112, (the circuit of figure place of N * B) is arranged.
That is, in the present embodiment, do not have selector circuit 107, and do not carry out piece and cut apart, this point is different with the 1st to the 6th embodiment.Present embodiment is the same with the 2nd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Figure 12 is the figure for the timing action that the 7th embodiment of the present invention is described.According to Figure 12, when during to display device substrate 101 input data signals, latching at the latch clock signal negative edge of supplying with latch cicuit 105 in 1 horizontal period.
As a result, the output signal of latch cicuit 105 as shown in figure 12.This signal becomes the input signal to next DAC circuit 106.Each data-signal carries out DA conversion (digital to analog conversion) on DAC circuit 106, becomes the simulating signal corresponding to each gray scale digital value.The DAC output signal directly is transferred to each data signal line.
Signal keeps high level in 1 horizontal period, is low level during all the other.Such signal scans successively, and each gate line of M bar is supplied with signal.
In the present embodiment, by the formation of Figure 11 and Figure 12, can the display unit 110 of the capable N row of M be shown.Data-signal to the capable N row of M display unit is a digital signal, according to the figure place B of digital gray scale, and the storage (bit data of M * N * B) in storer 111.In output buffer 112 because to each controlling grid scan line output of M bar, so can be with (the position transmission data of N * B).As a result, compare, can transmit data with slow transmission speed with existing transmission method.Data signals transmitted is carried out input data boosting to high-voltage value from low voltage value by level shift circuit 104.By this level shift circuit 104, do not need to carry out data transmission, so consumed power greatly reduces with high voltage.
In latch cicuit 105, as shown in Figure 12, data-signal is latched.This level shift circuit 104 and latch cicuit 105, identical with the figure place of being transmitted from output buffer 112, so that (N * B) handle the position.DAC circuit 106 is made of the N circuit, from input (data group of each gray scale figure place B carries out digital to analog conversion in the position of N * B), obtains 1 simulating signal, thus on whole circuit the analog signal data of output N position.The analog data signal of this N position is directly supplied with N bar data line, carries out the supply of data-signal.When each gate line of M bar scans, carry out reading of data successively from storer 111, and write to display unit 110.
Below the 8th embodiment of the present invention is described.Figure 13 represents the pie graph of the present invention the 8th embodiment.According to Figure 13, the 8th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114 herein, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111 and output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, DAC circuit 106 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Latch cicuit 105, level shifter circuit 104, DAC circuit 106 are arranged in this order, and DAC circuit 106 is connected row one side of display unit 110.
That is, in the present embodiment, the configuration of latch cicuit 105 and level shifter 104 is different with the 7th embodiment.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, DAC circuit 106 has the N output identical with the row one side input number of display unit 110.In output buffer 112, the ((circuit of figure place of N * B) of 1 row amount in the position of M * N * B) that is equivalent to storer 111 is arranged.Level shifter 104 and latch cicuit 105 identically with output buffer 112 have the (circuit of figure place of N * B).
That is, in the present embodiment, do not have selector circuit 107 and do not carry out piece and cut apart, this point is the same with the 7th embodiment, and is different with the 1st to the 6th embodiment.Present embodiment is the same with the 2nd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Embodiment 9
Below the 9th embodiment of the present invention is described.Figure 14 represents the pie graph of the present invention the 9th embodiment.According to Figure 14, the 9th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114 herein, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111 and output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Regularly impact damper 401, sweep circuit 109, latch cicuit 105, DAC circuit 106 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.
Latch cicuit 105, DAC circuit 106 are arranged in this order, and N DAC circuit 106 is connected row one side of display unit 110.That is, do not have level shifter circuit 104 in the present embodiment, replace level shifter/timing impact damper 108, disposed regularly impact damper 401, this point is different with the 7th and the 8th embodiment.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, row one side of DAC circuit 106 and display unit 110 input number is identical N output.
In output buffer 112, the ((circuit of figure place of N * B) of 1 row amount in the position of M * N * B) be equivalent to storer 111 is set.In latch cicuit 105, identical with output buffer 112, be provided with (the circuit of figure place of N * B).
That is, in the present embodiment, there is not selector circuit 107 and do not carry out piece that to cut apart this point the same with the 7th embodiment, different with the 1st to the 6th embodiment.Present embodiment is also the same with the 2nd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Below the 10th embodiment of the present invention is described.Figure 15 represents the pie graph of the present invention the 10th embodiment.In Figure 15, the 10th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, DAC circuit 106, current/charge-voltage convertor/electric current output buffer 801 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Level shifter circuit 104, latch cicuit 105, DAC circuit 106, current/charge-voltage convertor/electric current input buffer 801 are arranged in this order, and current/charge-voltage convertor/electric current output buffer 801 is connected row one side of display unit 110.
The present invention carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit.Storer 111 has the (bit capacity of M * N * B).Current/charge-voltage convertor/electric current output buffer 801 has the N output identical with the row-side input number of display 110.((the circuit of figure place of N * B) that 1 row is measured in the position of M * N * B) that is equivalent to storer 111 is arranged in output buffer 112.Level shifter 104 and latch cicuit 105, identical with output buffer 112, (the circuit of figure place of N * B) is arranged.DAC circuit 106 is made of the N circuit.
That is, in the present embodiment, there is not selector circuit 107 and do not carry out piece and cut apart this point, different with the 5th embodiment.Present embodiment is the same with the 2nd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Figure 16 is the figure for the timing action that the 10th embodiment of the present invention is described.According to Figure 16, when during to display device substrate 101 input data signals, latching at the latch clock signal negative edge of supplying with latch cicuit 105 in 1 horizontal period.As a result, the output signal of latch cicuit 105 as shown in figure 16.This signal becomes the input signal of next DAC circuit 106.By the DAC circuit, each data-signal carries out DA conversion (digital to analog conversion), becomes the simulating signal corresponding to each gray scale digital value.This DAC output signal is a voltage signal, but is converted to current output signal by current/charge-voltage convertor electric current output buffer 801.This current output signal directly is transferred to each data signal line.Signal keeps high level in 1 horizontal period, be low level during all the other.Such signal scans successively, and each gate line of M bar is supplied with signal.
In the present embodiment, by the formation of Figure 15 and Figure 16, can the display unit 110 of the capable N row of M be shown.Data-signal to the capable N row of M display unit is a digital signal, according to the figure place B of digital gray scale, and (the data of the position of M * N * B) of storage in storer 111.In output buffer 112 because each controlling grid scan line of M bar is exported, so with (the position transmission data of N * B).As a result, compare, can transmit data with slow transmission speed with existing transmission method.Data signals transmitted is carried out input data boosting to high-voltage value from low voltage value by level shift circuit 104.By this level shift circuit, owing to do not need to transmit data with high voltage, so consumed power greatly reduces.
In latch cicuit 105, as shown in Figure 16 data-signal is latched.This level shift circuit 104 and latch cicuit 105, identical with the figure place of being transmitted from output buffer 112, so that (N * B) handle the position.
DAC circuit 106 is made of the N circuit, from input (data group of each gray scale figure place B carries out digital to analog conversion in the position of N * B), obtains 1 simulating signal, thus in the analog signal data of whole circuit output N position.The analog data signal of this N position is converted to current signal by current/charge-voltage convertor/electric current output buffer 801 from voltage signal.The analog current signal of this N position is directly supplied with N bar data line, carries out the supply of data-signal.When each gate line of M bar scans,, write to display unit 110 from storer 111 sense data successively.
Below the 11st embodiment of the present invention is described.Figure 17 represents the pie graph of the present invention the 11st embodiment.According to Figure 17, the 11st embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114 herein, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, decoder circuit 1001, electric current output buffer 1002 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.The decoder circuit 1001 of the output of level shifter circuit 104, latch cicuit 105, B latch cicuit 105 of input, import the output of decoding circuit 1001 and arrange in this order according to the electric current output buffer 1002 of decoded result output current value, electric current follower 1002 is connected row one side of display unit 110.Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (bit capacity of M * N * B).In addition, electric current output buffer 1002 has the N output identical with the row one side input number of display unit 110.((the circuit of figure place of N * B) that 1 row is measured in the position of M * N * B) that is equivalent to storer 111 is arranged in output buffer 112.Level shifter 104 and latch cicuit 105, identical with output buffer 112, (the circuit of figure place of N * B) is arranged.Decoder circuit 1001 is made of the N circuit.
That is, in the present embodiment, to cut apart this point different with the 6th embodiment with not carrying out piece selector circuit 107.Present embodiment is also the same with the 2nd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Below the 12nd embodiment of the present invention is described.Figure 18 represents the pie graph of the present invention the 12nd embodiment.According to Figure 18, the 12nd embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, DAC circuit 106, selector circuit 107, serial-to-parallel converter circuit 1801 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Level shifter circuit 104, serial-to-parallel converter circuit 1801, latch cicuit 105, DAC circuit 106, selector circuit 107 are arranged in this order, and selector circuit 107 is connected display unit 110 row one side.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, selector circuit 107 has the N output identical with the row one side input number of display unit 110.On output buffer 112, have and to be equivalent to the ((circuit of { (N * B)/(P * S) } figure place that the position of N * B) cuts apart that the quantity of several S and serial phase demodulation count that P cuts apart by piece of 1 row amount in the position of M * N * B) of storer 111.Level shifter 104 is identical with output buffer 112, and the circuit of { (N * B)/(P * S) } figure place is arranged.Latch cicuit 105 has the { (circuit of N * B)/S} figure place.DAC circuit 106 is by (N * S) circuit constitutes.
In the present embodiment, serial-to-parallel converter circuit 1801 is set, the figure place difference of each circuit, this point is different with other embodiment.
Figure 19 is the figure for the timing action of saying the present invention the 12nd embodiment.According to Figure 19,,, become and be launched into the signal that serial is launched number P (P=2 herein) by serial-to-parallel converter circuit 1801 when in 1 horizontal period during to display device substrate 101 input data.
This P phase demodulation is controlled by S/P change-over circuit control signal in serial-to-parallel converter circuit (below be abbreviated as " S/P change-over circuit ") 1801.S/P change-over circuit control signal is supplied with S/P change-over circuit 1801 from level shifter/timing impact damper 108.
In the example of Figure 19, at odd number (even number) the pulse negative edge of S/P change-over circuit control signal, the odd data of input data signal is latched, generate S/P change-over circuit output A.On the other hand,, the even data of input data signal is latched, generate S/P change-over circuit output B at even number (odd number) the pulse negative edge of S/P change-over circuit control signal.When launching number P, data-signal is launched at the multiple of each P 3 when above.Negative edge at the latch clock signal of supplying with latch cicuit 105 latchs then.As a result, the output signal of latch cicuit 105 as shown in the figure.This signal becomes the input signal to next DAC circuit 106.On the DAC circuit, each data-signal carries out DA conversion (digital to analog conversion), becomes the simulating signal corresponding to each gray scale digital value.
As selector control signal, cut apart the wiring that several S (S=4 in Figure 19) measure for piece, as shown in figure 19, the scan control pulse scans successively.When this selector control signal is input to selector circuit 107, from the DAC output signal, select signal successively, be separated into the signal that piece is cut apart several S quantity, being transferred to the bar number is each signal wire that piece is cut apart the signal line-group of several S.
Such signal line-group is arranged (N/S) individual and all parallel signal of supplying with, and can be implemented in 1 horizontal period thus and supplies with signal to the N signal line.Signal keeps high level in 1 horizontal period, be low level during all the other.Such signal scans successively, can supply with signal to each gate line of M bar.
Present embodiment is by the formation of Figure 18 and Figure 19, can the display unit 110 of the capable N row of M be shown, and be digital signal to the data-signal of the display unit of the capable N row of M, according to digital gray scale figure place B, (the data of position of M * N * B) of storage in storer 111.Output buffer 112.Because on the controlling grid scan line of each M bar, be divided into piece and cut apart several S, and be separated into the serial phase demodulation and count the laggard line output of P, so carry out data transmission with { (N * B)/(P * S) } position.
As a result, compare, can transmit data with slow transmission speed with existing transmission method.Institute's data signals transmitted by level shift circuit 104, is carried out input data the boosting to high-voltage value from low-voltage.By this level shift circuit, owing to do not need to transmit data with high voltage, so consumed power greatly reduces.On serial-to-parallel converter circuit 1801, as shown in Figure 19, expand into the output signal that serial is carried out several P (P=2 herein) mutually.This level shift circuit 104 and serial-to-parallel converter circuit 1801, identical with the figure place of being transmitted from output buffer 112, handle with { (N * B)/(P * S) } position.
In latch cicuit 105, as shown in Figure 19 data-signal is latched.This latch cicuit 105 becomes P figure place doubly by serial conversion, handles with { (N * B)/(P * S) } position.DAC circuit 106 is made of (N/S) circuit, from imported { (data group of each gray scale figure place B carries out digital to analog conversion in N * B)/S}} position, obtains 1 simulating signal, in the analog signal data of whole circuit output (N/S).Should (N/S) analog data signal of position on next selection circuit 107, be divided into piece with per 1 and cut apart the time of several S and select successively, supply with data-signal to the data line-group.As a result, N bar data line is carried out the supply of data-signal.When each gate line of scanning M bar, carry out reading of data successively from storer 111, and write to display unit 110.
In the present embodiment, latch at the negative edge of S/P change-over circuit control signal, but also can latch at rising edge.In addition, also can latch data A, and output B be latched on (decline) edge of rising on (rising) edge that descends.When constituting like this, S/P change-over circuit control signal can be utilized the waveform of 2 doubling times of the S/P change-over circuit control signal of Figure 19.
Below the 13rd embodiment of the present invention is described.Figure 20 represents the pie graph of the present invention the 13rd embodiment.According to Figure 20, the 13rd embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, DAC circuit 106, selector circuit 107, serial-to-parallel converter circuit 1801 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Level shifter circuit 104, serial-to-parallel converter circuit 1801, latch cicuit 105, DAC circuit 106, selector circuit 107 are arranged in this order, and selector circuit 107 is connected row one side of display unit 110.
Present embodiment is different with the 12nd embodiment, and level shifter/timing impact damper 108 and sweep circuit are configured in the left and right sides of display unit 110.Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, selector circuit 107 has the N output identical with the row one side input number of display unit 110.In output buffer 112, have be equivalent to storer 111 (in the position of M * N * B) 1 row amount (position of N * B) is divided into piece and cuts apart the circuit that several S and serial phase demodulation are counted { (N * B)/(P * S) } figure place of P.Level shifter 104 is identical with output buffer 112, and the circuit of { (N * B)/(P * S) } figure place is arranged, and latch cicuit 105 has the { (circuit of N * B)/S} figure place.DAC circuit 106 is made of (N/S) circuit.
Below the 14th embodiment of the present invention is described.Figure 21 represents the pie graph of the present invention the 14th embodiment.According to Figure 21, the 14th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, DAC circuit 106, selector circuit 107, serial-to-parallel converter circuit 1801 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Level shifter circuit 1801, latch cicuit 105, level shifter 104, DAC circuit 106, selector circuit 107 are arranged in this order, and selector circuit 107 is connected row one side of display unit 110.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, selector circuit 107 has the N output identical with the row one side input number of display unit 110.In output buffer 112, have be equivalent to storer 111 (in the position of M * N * B) 1 row amount (position of N * B) is divided into piece and cuts apart the circuit that several S and serial phase demodulation are counted { (N * B)/(P * S) } figure place of P.
Level shifter 104 and latch cicuit 105 be because in serial conversion back configuration, thus have the many P of the number of specific output impact damper doubly (N/B)/circuit of S} bit quantity.
DAC circuit 106 is made of (N/S) circuit.
In the present embodiment, the configuration sequence of serial-to-parallel converter circuit 1801, level shifter 104 and latch cicuit 105 and circuit number, different with the 12nd, the 13rd embodiment.Present embodiment is the same with the 13rd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Below the 15th embodiment of the present invention is described.Figure 22 represents the pie graph of the present invention the 15th embodiment.According to Figure 22, the 15th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114 herein, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Regularly impact damper 401, sweep circuit 109, latch cicuit 105, DAC circuit 106, selector circuit 107, serial-to-parallel converter circuit 1801 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Serial-to-parallel converter circuit 1801, latch cicuit 105, DAC circuit 106, selector circuit 107 are arranged in this order, and selector circuit 107 is connected row one side of display unit 110.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, selector circuit 107 has the N output identical with the row one side input number of display unit 110.In output buffer 112, have be equivalent to storer 111 ((position of N * B) is divided into piece and cuts apart the circuit that several S and serial phase demodulation are counted { (N * B)/(P * S) } figure place of P 1 row amount in the position of M * N * B).Latch cicuit 105 is because in serial conversion back configuration, thus the many P of specific output number of buffers doubly, have (N/B)/circuit of S} figure place.DAC circuit 106 is made of (N/S) circuit.
In the present embodiment, do not have level shifter 104, what replace level shifter/timing impact damper 108 is regularly impact damper 401 of configuration, and this point is different with the 12nd and the 14th embodiment.Present embodiment is the same with the 2nd embodiment, and regularly impact damper 401 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Below the 16th embodiment of the present invention is described.Figure 23 represents the pie graph of the present invention the 16th embodiment.According to Figure 23, the 16th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114 herein, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, DAC circuit 106, selector circuit 107, serial-to-parallel converter circuit 1801, current/charge-voltage convertor/electric current output buffer 801 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Level shifter circuit 104, serial-to-parallel converter circuit 1801, latch cicuit 105, DAC circuit 106, current/charge-voltage convertor/electric current output buffer 801, selector circuit 107 are arranged in this order, and selector circuit 107 is connected display unit 110 row one side.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, selector circuit 107 has the N output identical with the row one side input number of display unit 110.On output buffer 112, have and to be equivalent to the ((circuit of { (N * B)/(P * S) } figure place that the position of N * B) is divided into that piece cuts apart that the quantity of several S and serial phase demodulation count that P cuts apart of 1 row amount in the position of M * N * B) of storer 111.
Level shifter 104 is identical with output buffer 112, and the circuit of { (N * B)/(P * S) } figure place is arranged.
Latch cicuit 105 has the { (circuit of N * B)/S} figure place.DAC circuit 106 and current/charge-voltage convertor/electric current output buffer 801 is by (N * S) circuit constitutes.
Have current/charge-voltage convertor/electric current output buffer 801 in the present embodiment, this point is different with other embodiment.Present embodiment is the same with the 13rd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Figure 24 is the figure for the timing action of saying the present invention the 16th embodiment.According to Figure 24, when during to display device substrate 101 input data signals,, expanding into the signal that serial is launched number P (P=2 herein) by serial-to-parallel converter circuit 1801 in 1 horizontal period.This is deployed on the serial-to-parallel converter circuit (below write a Chinese character in simplified form title " S/P change-over circuit ") 1801 and is controlled by S/P change-over circuit control signal.
In the example of Figure 24, at odd number (even number) the pulse negative edge of S/P change-over circuit control signal, the odd data of input data signal is latched, generate S/P change-over circuit output A.On the other hand,, the even data of input data signal is latched, generate the output B of S/P change-over circuit 1801 at the negative edge of even number (odd number) pulse of S/P change-over circuit control signal.
When launching number P, the multiple of data-signal at each P launched 3 when above.
Negative edge at the latch clock signal of supplying with latch cicuit 105 latchs then.
As a result, the output signal of latch cicuit 105 as shown in figure 24.This signal becomes the input signal to next DAC circuit 106.
On DAC circuit 106, data-signal carries out DA conversion (digital to analog conversion), becomes the simulating signal corresponding to each gray scale digital value.This DAC output signal is converted to current signal by current/charge-voltage convertor/electric current output buffer 801 from voltage signal.As selector control signal, piece is cut apart the distribution that several S (S=4 among Figure 24) measure, control scans with pulse as shown in figure 24 successively.
When this selector control signal is input to selector circuit 107, from the DAC output signal, select signal successively, be separated into the signal that piece is cut apart several S quantity, being transferred to the bar number is each signal wire that piece is cut apart the signal line-group of several S.Such signal line-group is arranged (N/S) individual and all parallel signal of supplying with, and can be implemented in 1 horizontal period thus and supplies with signal to the N signal line.Signal keeps high level in 1 horizontal period, be low level during all the other.Such signal scans successively, and each gate line of M bar is supplied with signal.
In the present embodiment, by the formation of Figure 23 and Figure 24, can the display unit 110 of the capable N of M row be shown, be digital signal to the data-signal of the display unit 110 of the capable N row of M, according to the figure place B of digital gray scale, (the data of the position of M * N * B) of storage in storer 111.
In output buffer 112, each controlling grid scan line of M bar is divided into piece cuts apart several S, and count the laggard line output of P, so can be with { (N * B)/(P * S) } position transmission data owing to be separated into the serial phase demodulation.As a result, compare, can transmit data with slow transmission speed with existing transmission method.
Institute's data signals transmitted is carried out input data boosting to high-voltage value from low-voltage by level shift circuit 104.By this level shift circuit 104, owing to do not need to transmit data with high voltage, so consumed power greatly reduces.
In serial-to-parallel converter circuit 1801, as shown in Figure 24, expand into the output signal that serial is carried out several P (P=2 herein) mutually.This level shift circuit 104 and serial-to-parallel converter circuit 1801, identical with the figure place of being transmitted from output buffer 112, handle with { (N * B)/(P * S) } position.
In latch cicuit 105, as shown in Figure 24 data-signal is latched.This latch cicuit 105 becomes P figure place doubly by the serial conversion, with (N * B)/handle the S} position.
DAC circuit 106 is made of (N/S) circuit, from imported { (data group of each gray scale figure place B carries out digital to analog conversion in N * B)/S} position, obtains 1 simulating signal, the analog signal data of output (N/S) on whole circuit.
Be somebody's turn to do the analog data signal of (N/S) position,, convert current signal to from voltage signal by current/charge-voltage convertor/electric current output buffer 801.Should (N/S) analog current signal of position, in next selector circuit 107, be divided into piece with per 1 and cut apart the time of several S and select successively, supply with data-signal to S bar data line-group.As a result, can supply with data-signal to N bar data line.
When each gate line scanning of M bar,, and write to display unit 110 from storer 111 sense data successively.
In the present embodiment, latch at the negative edge of S/P change-over circuit control signal, but also can latch at rising edge.In addition, also can latch output A, and output B be latched on (decline) edge of rising on (rising) edge that descends.When this constituted, S/P change-over circuit control signal can be utilized the waveform of 2 doubling times of the S/P change-over circuit control signal of Figure 24.
Below the 17th embodiment of the present invention is described.Figure 25 represents the pie graph of the present invention the 17th embodiment.According to Figure 25, the 17th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114 herein, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, demoder 1001, selector circuit 107, serial-to-parallel converter circuit 1801, electric current output buffer 1002 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Level shifter circuit 104, serial-to-parallel converter circuit 1801, latch cicuit 105, decoder circuit 1001, electric current output buffer 1002, selector circuit 107 are arranged in this order, and selector circuit 107 is connected row one side of display unit 110.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, selector circuit 107 has the N output identical with the row one side input number of display unit 110.In output buffer 112, have be equivalent to storer 111 ((block of N * B) is cut apart the circuit that the quantity of several S and serial phase demodulation are counted { (N * B)/(P * S) } figure place of P to 1 row amount in the position of M * N * B).Level shifter 104 is identical with output buffer 112, and the circuit of { (N * B)/(P * S) } figure place is arranged.Latch cicuit 105 has the { (circuit of N * B)/S} figure place.Decoder circuit 1001 and electric current output buffer 1002 are made of (N/S) circuit.
In the present embodiment, have decoder circuit 1001 and electric current output buffer 1002, this point is different with the above embodiments.Present embodiment is the same with the 13rd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Below the 18th embodiment of the present invention is described.Figure 26 represents the pie graph of the present invention the 18th embodiment.According to Figure 26, the 18th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114 herein, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, DAC circuit 106, serial-to-parallel converter circuit 1801 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Level shifter circuit 104, serial-to-parallel converter circuit 1801, latch cicuit 105, DAC circuit 106 are arranged in this order, and DAC circuit 106 is connected row one side of display unit 110.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).
In addition, DAC circuit 106 has the N output identical with the row one side input number of display unit 110.On output buffer 112, have be equivalent to storer 111 ((position of N * B) is divided into the { (circuit of N * B)/P} figure place that the serial phase demodulation is counted P to 1 row amount in the position of M * N * B).Level shifter 104 identically with output buffer 112 has the { (circuit of N * B)/P} figure place.Latch cicuit 105 has the (circuit of figure place of N * B).DAC circuit 106 is made of the N circuit.
The figure place difference that does not have selector circuit 107, each circuit in the present embodiment, this point is different with other embodiment.Present embodiment is also the same with the 13rd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Figure 27 is the figure in order to say that the present invention the 18th embodiment regularly moves.According to Figure 27, when during to display device substrate 101 input data signals,, expanding into the signal that serial is launched number P (P=2 herein) by serial-to-parallel converter circuit 1801 in 1 horizontal period.This is deployed in the serial-to-parallel converter circuit (hereinafter to be referred as " S/P change-over circuit ") 1801, is controlled by S/P change-over circuit control signal.
In the example of Figure 27, at odd number (even number) the pulse negative edge of S/P change-over circuit control signal, the odd data of input data signal is latched, generate S/P change-over circuit output A.On the other hand,, the even data of input data signal is latched, generate S/P change-over circuit output B at the negative edge of even number (odd number) pulse of S/P change-over circuit control signal.When launching number P, press the multiple expanding data signal of each P 3 when above.Negative edge at the latch clock signal of supplying with latch cicuit 105 latchs then.As a result, the output signal of latch cicuit 105 as shown in the figure.This signal becomes the input signal to next DAC circuit 106.On the DAC circuit, each data-signal carries out DA conversion (digital to analog conversion), becomes the simulating signal corresponding to each layer digital value.The output signal of DAC directly is transferred to each data signal line.Signal remains on high level in 1 horizontal period, is low level during all the other.Such signal scans successively, and each gate line of M bar is supplied with signal.
This enforcement is by the formation of Figure 26 and Figure 27, can the display unit 110 of the capable N row of M be shown, and be digital signal to the data-signal of the display unit of the capable N row of M, according to the figure place B of digital gray scale, (the data of position of M * N * B) of storage in storer 111.On output buffer 112, owing to be separated into the serial phase demodulation and count the laggard line output of P on each controlling grid scan line of M bar, so can be with { (N * B)/P}} position transmission data.As a result, compare, can transmit data with slow transmission speed with existing transmission method.Institute's data signals transmitted is carried out input data boosting to high-voltage value from low-voltage by level shift circuit 104.By this level shift circuit, owing to do not need to transmit data with high voltage, so consumed power greatly reduces.
In serial-to-parallel converter circuit 1801, as shown in Figure 27, expand into the output signal that serial is carried out several P (P=2 herein) mutually.This level shift circuit 104 and serial-to-parallel converter circuit 1801, identical with the figure place of being transmitted from output buffer 112, with (N * B)/handle the P} position.In latch cicuit 105, as shown in Figure 27 data-signal is latched.This latch cicuit 105 becomes P figure place doubly by the serial conversion, so that (N * B) handle the position.DAC circuit 106 is made of the N circuit, from imported (each the gray scale figure place B in the position of N * B) carries out digital to analog conversion, obtains 1 simulating signal, the analog signal data of output N position on whole circuit.The analog data signal of this N position is directly supplied with N bar data line.When each gate line of M bar scans,, write to display unit 110 from storer 111 sense data successively.
In the present embodiment, latch at the negative edge of S/P change-over circuit control signal, but also can latch at rising edge.In addition, also can latch output A, and output B be latched on (decline) edge of rising on (rising) edge that descends.When this constituted, S/P change-over circuit control signal can be utilized the waveform of 2 doubling times of the S/P change-over circuit control signal of Figure 27.
Below the 19th embodiment of the present invention is described.Figure 28 represents the pie graph of the present invention the 19th embodiment.According to Figure 28, the of the present invention the 19th executes example is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.
Circuit system end group plate 103 comprises interface circuit 114 herein, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shift/timing impact damper 108, sweep circuit 109, serial-to-parallel converter circuit 1801, level shifter 104, latch cicuit 105, DAC circuit 106 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Serial-to-parallel converter circuit 1801, level shifter circuit 104, latch cicuit 105, DAC circuit 106 are arranged in this order, and DAC circuit 106 is connected row one side of display unit 110.Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, DAC circuit 106 has the N output identical with the row one side input number of display unit 110.
In output buffer 112, ({ (the circuit of N * B)/P} figure place of 1 row amount in the position of M * N * B) that is equivalent to storer 111 is arranged.Latch cicuit 105 has the (circuit of figure place of N * B).The DAC circuit is made of the N circuit.
In the present embodiment, the aligning method of level shifter 104 and figure place are different with the 18th embodiment.Present embodiment is the same with the 13rd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Below the 20th embodiment of the present invention is described.Figure 29 represents the pie graph of the present invention the 20th embodiment.According to Figure 29, the 20th embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Regularly impact damper 401, sweep circuit 109, serial-to-parallel converter circuit 1801, latch cicuit 105, DAC circuit 106 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Serial-to-parallel converter circuit 1801, latch cicuit 105, DAC circuit 106 are arranged in this order, and DAC circuit 106 is connected row one side of display unit 110.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, DAC circuit 106 has the N output identical with the row one side input number of display unit 110.
In output buffer 112, ({ (the circuit of N * B)/P} figure place of 1 row amount in the position of M * N * B) that is equivalent to storer 111 is arranged.Serial-to-parallel converter circuit 1801, to from the serial of output buffer 112 output, receives P time, expand into P phase (output of P bit parallel), export (N * B) side by side from serial-to-parallel converter circuit 1801.Latch cicuit 105 has the (circuit of figure place of N * B).The DAC circuit is made of the N circuit.
In the present embodiment, do not have level shifter 104, replace level shifter/timing impact damper 108, disposed regularly impact damper 401, this point is different with the 18th and the 19th embodiment.Present embodiment is the same with the 13rd embodiment, and regularly impact damper 401 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Below the 21st embodiment of the present invention is described.Figure 30 represents the pie graph of the present invention the 21st embodiment.According to Figure 30, the 21st embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, serial-to-parallel converter circuit 1801, level shifter 104, latch cicuit 105, DAC circuit 106, current/charge-voltage convertor/electric current output buffer 801 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Level shifter circuit 104, serial-to-parallel converter circuit 1801, latch cicuit 105, DAC circuit 106, current/charge-voltage convertor/electric current output buffer 801 are arranged in this order,, current/charge-voltage convertor/electric current output buffer 801 is connected row one side of display unit 110.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, current/charge-voltage convertor/electric current output buffer 801 has the N output identical with the row one side input number of display unit 110.
On output buffer 112, have and to be equivalent to the (({ (circuit of N * B)/P} figure place that the position of N * B) is cut apart by P of 1 row amount in the position of M * N * B) of storer 111.Level shifter 104 identically with output buffer 112 has the { (circuit of N * B)/P} figure place.Receive latch cicuit 105 serial-to-parallel converter circuit 1801 and line output, (the individual circuit of N * B) is arranged.DAC circuit 106 and current/charge-voltage convertor/electric current output buffer 801 is made of the N circuit.
In the present embodiment, have current/charge-voltage convertor/electric current output buffer 801, this point is different with other embodiment.Present embodiment is the same with the 13rd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Figure 31 is the figure for the timing action of saying the present invention the 21st embodiment.According to Figure 31, when during to display device substrate 101 input data signals,, becoming by serial and launch the signal that number P (P=2 herein) launches by serial-to-parallel converter circuit 1801 in 1 horizontal period.
This is deployed in the serial-to-parallel converter circuit (hereinafter to be referred as " S/P change-over circuit ") 1801 and is controlled by S/P change-over circuit control signal.In the example of Figure 31, at the negative edge of odd number (even number) pulse of S/P change-over circuit control signal, the odd data of input data signal is latched, generate S/P change-over circuit output A.On the other hand,, the even data of input data signal is latched, generate S/P change-over circuit output B at the negative edge of even number (odd number) pulse of S/P change-over circuit control signal.When launching number, data-signal is launched by the multiple of each P 3 when above.
Negative edge at the latch clock signal of supplying with latch cicuit 105 latchs then.As a result, the output signal of latch cicuit 105 as shown in the figure.This signal becomes the input signal to next DAC circuit 106.On the DAC circuit, each data-signal carries out DA conversion (digital to analog conversion), becomes the simulating signal corresponding to the digital value of each gray scale.This DAC output signal is a voltage signal, but by current/charge-voltage convertor/electric current output buffer 801, converts current output signal to.This current output signal directly is transferred to each data signal line.Signal remains on high level in 1 horizontal period, be low level during all the other.Such signal scans successively, and each gate line of M bar is supplied with signal.
In the present embodiment, by the formation of Figure 30 and Figure 31, can the display unit 110 of the capable N row of M be shown.Data-signal to the capable N row of M display unit is a digital signal, according to the figure place B of digital gray scale, and (the data of the position of M * N * B) of storage in storer 111.On output buffer 112, count the laggard line output of P owing on each sweep trace of M bar, be separated into the serial phase demodulation, so with (N * B)/P}} position transmission data.As a result, compare with existing transmission method, can be with slow transmission speed transmission data.Institute's data signals transmitted is carried out input data boosting to high-voltage value from low-voltage by level shift circuit 104.By this level shift circuit 104, owing to do not need to transmit data with high voltage, so consumed power greatly reduces.In serial-to-parallel converter circuit 1801, as shown in Figure 31, expand into the output signal that serial is carried out several P (P=2 herein) mutually.This level shift circuit 104 and serial-to-parallel converter circuit 1801, identical with the figure place of being transmitted from output buffer 112, with (N * B)/handle the P} position.
In latch cicuit 105, as shown in Figure 31 data-signal is latched.This latch cicuit 105 by the serial conversion, becomes P figure place doubly, so that (N * B) handle the position.DAC circuit 106 is made of the N circuit, from imported (data group of each the gray scale figure place B in the position of N * B) carries out digital to analog conversion, obtains 1 simulating signal, thus on whole circuit the analog signal data of output N position.The analog data signal of this N position in current/charge-voltage convertor/electric current output buffer 1801 that the N position constitutes, is converted to current signal from voltage signal.The analog current data-signal of this N position is directly supplied with N bar data line.When each gate line of M bar scans,, write to display unit 110 from storer 111 sense data successively.
In the present embodiment, latch at the negative edge of S/P change-over circuit control signal, but also can latch at rising edge.In addition, also can latch output A, and output B be latched on (decline) edge of rising on (rising) edge that descends.When this constituted, S/P change-over circuit control signal can be utilized the waveform of 2 doubling times of the S/P change-over circuit control signal of Figure 31.
Below the 22nd embodiment of the present invention is described.Figure 32 represents the pie graph of the present invention the 20th embodiment.According to Figure 32, the 22nd embodiment of the present invention is made of system side circuitry substrate 103, controller IC 102 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114 herein, is connected with controller IC 102.Controller IC 102 comprises controller 113, storer 111, output buffer 112, is connected with circuit system end group plate 103 and display device substrate 101.Level shifter/timing impact damper 108, sweep circuit 109, level shifter 104, latch cicuit 105, serial-to-parallel converter circuit 1801, decoder circuit 1001, electric current output buffer 1002 and display unit 110 are housed in the display device substrate 101, are connected on the controller IC 102.Level shifter circuit 104, serial-to-parallel converter circuit 1801, latch cicuit 105, decoder circuit 1001, electric current output buffer 1002 are arranged in this order, and electric current output buffer 1002 is connected row one side of display unit 110.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).Electric current output buffer 1002 has the N output identical with the row one side input number of display unit 110.
In output buffer 112, have be equivalent to storer 111 (in the position of M * N * B) 1 row amount (position of N * B) is divided into the { (circuit of N * B)/P} figure place that the serial phase demodulation is counted P.
Level shifter 104 identically with output buffer 112 has the { (circuit of N * B)/P} figure place.Latch cicuit 105 has the (circuit of figure place of N * B).
Decoder circuit 1001 and electric current output buffer 1002 are made of the N circuit.
In the present embodiment, exist electric current output buffer 1002 this point different with other embodiment.Present embodiment is also the same with the 13rd embodiment, and level shifter/timing impact damper 108 and sweep circuit 109 can certainly be configured in the left and right sides of display unit 110.
Below the 23rd embodiment of the present invention is described.Figure 33 represents the pie graph of the present invention the 23rd embodiment.According to Figure 33, the 23rd embodiment of the present invention is made of system side circuitry substrate 103 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with display device substrate 101.Controller 113, storer 111, impact damper 112, sweep circuit 109, latch cicuit 105, serial-to-parallel converter circuit 1801, DAC circuit 106, selector circuit 107 and display unit 110 are housed in the display device substrate 101, are connected on the system side circuitry substrate 103.Serial-to-parallel converter circuit 1801, latch cicuit 105, DAC circuit 106, selector circuit 107 are arranged in this order, and selector circuit 107 is connected row one side of display unit 110.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).In addition, selector circuit 107 has the N output identical with the row one side input number of display unit 111.In impact damper 112, have be equivalent to storer 111 (position of M * N * B) 1 row amount (position of N * B) is divided into piece and cuts apart the circuit that the quantity of several S and serial phase demodulation are counted { (N * B)/(P * S) } figure place of P.Latch cicuit 105 is because after being configured in the serial conversion, so the many P of specific output impact damper doubly, have (the circuit of N * B)/S} figure place.
DAC circuit 106 is made of (N/S) circuit.Do not have controller IC 102 in the present embodiment, storer 111 and impact damper 112 are configured on the display device substrate 101, and this point is different with other embodiment.Present embodiment is the same with the 2nd embodiment, and controller 113 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Embodiment 24
Below the 24th embodiment of the present invention is described.Figure 34 represents the pie graph of the present invention the 24th embodiment.According to Figure 34, the of the present invention the 24th executes example is made of system side circuitry substrate 103 and display device substrate 101.Circuit system end group plate 103 comprises interface circuit 114, is connected with display device substrate 101.Controller 113, storer 111, impact damper 112, sweep circuit 109, latch cicuit 105, serial-to-parallel converter circuit 1801, DAC circuit 106 and display unit 110 are housed in the display device substrate 101, are connected on the system side circuitry substrate 103.Parallel/serial conversion circuit 1801, latch cicuit 105, DAC circuit 106 are arranged in this order, and DAC circuit 106 is connected row one side of display unit 110.
Present embodiment carries out the Active Matrix LCD At of the capable N row of M with gray scale figure place B on display unit 110.Storer 111 has the (capacity of the position of M * N * B).
In addition, DAC circuit 106 has the N circuit, has the N output identical with the row one side input number of display unit 110.In impact damper 112, be provided be equivalent to storer 111 (in the position of M * N * B) 1 row amount (position of N * B) is divided into the { (circuit of N * B)/P} figure place that the serial phase demodulation is counted P.Latch cicuit 105 is owing to be configured in after the serial conversion, so the many P of specific output impact damper doubly, have (the circuit of figure place of N * B).In the present embodiment, do not have controller IC 102, storer 111 and impact damper 112 are configured on the display device substrate 101, and this point is different with other embodiment.Present embodiment is the same with the 2nd embodiment, and controller 113 and sweep circuit 109 also can be configured in the left and right sides of display unit 110.
Manufacture method to the display screen substrate that adopted in the various embodiments described above describes below.
Embodiment 25
Made the tft array of polysilicon (poly-Si) in the present embodiment.Figure 35 to Figure 36 is illustrated in the process profile diagram that the array manufacturing of the multi-crystal TFT (planar structure) that forms raceway groove on the superficial layer of polysilicon constitutes.
Specifically, on glass substrate 10, form after the silicon oxide film 11, make amorphous silicon 12 growths.Anneal with excimer laser then, make amorphous silicon multi-crystal silicification (Figure 35 (a)).
Making thickness again is silicon oxide film 13 growths of 10nm, after pattern forms (Figure 35 (b)), coating photoresist 14 carries out pattern and forms (the p channel region is added mask), by Doping Phosphorus (P) ion, form source electrode and drain region (Figure 35 (c)) of n raceway groove.
After the thickness that makes gate insulating film again was silicon oxide film 15 growth of 90nm, (μ-c-Si) 16 and tungsten silicon compound (WSi) 17 generated, and pattern forms grid shapes (Figure 35 (d)) to make the microcrystal silicon that constitutes grid.
After making silicon oxide film and silicon nitride film 19 continued growths, opening connection uses hole (Figure 36 (f)), forms aluminium and titanium 20 with sputtering method, carry out pattern and form (Figure 36 (g)), in this pattern forms, form the source-drain electrode of peripheral circuit CMOS, the data line that is connected with the drain electrode of pixel switch TFT and connect up, reach and the coupling part of pixel switch.
Then form the silicon nitride film 21 of dielectric film, open to connect and use the hole, form the transparency electrode ITO (Indium Tin Oxide) 22 that uses as pixel capacitors, carry out pattern-forming (Figure 36 (h)).
Like this, make the TFT pixel switch of planar structure, form tft array.
The peripheral circuit part, with pixel switch be the n channel TFT equally, adopt the technology identical substantially simultaneously with the n channel TFT, the doping formation by boron is as the TFT of p raceway groove.In Figure 36 (h), represented n channel TFT, the P channel TFT of peripheral circuit, pixel switch (n channel TFT), maintenance capacitor, the pixel capacitors of peripheral circuit from left to right.
The formation of circuit is the structure of the 1st embodiment shown in Fig. 1.Constitute the TFT of circuit on the display device substrate, make by the TFT of same process.Pixel switch that needs ceiling voltage and the technology of selecting circuit 107 work have been carried out to make.
On this TFT substrate, make the post (not drawing among the figure) that 4 μ m patterns form again, can be used as the isolated area that keeps the device gap and use, have impact resistance simultaneously.
In addition the pixel area of relative substrate (not drawing among the figure) external coated the ultraviolet curing encapsulant.
To behind TFT substrate and the relative substrate bonding, inject liquid crystal.Liquid crystal material uses nematic liquid crystal, by adding chirality (chiral) material, frictional direction is cooperated, and becomes spiral fashion to row (NT) type.
In the present embodiment, compare, can realize satisfying simultaneously the transmissive display device of high meticulous, many gray scales, low cost, low power consumption with existing formation.
In the present embodiment, in the formation of polysilicon film, adopted excimer laser, but also can use other laser instruments, for example the CW laser instrument of continuous oscillation etc.
In above-mentioned the 1st embodiment etc., slave controller IC102 is to the data drive circuit of display device substrate 101, with 1 behavior unit or 1 row is cut apart several S (=4) by piece to wait the bit data cut apart be that unit transmits, and the reduction of the frequency of operation of data line drive circuit.In general, the thickness of transistorized gate insulating film is thick more, and threshold value is high more, and operating rate is slow more.In the foregoing description that the frequency of operation that makes peripheral circuit reduces,, also can work even adopt the slow TFT of operating rate.That is, when frequency of operation improves, need carry out the optimization of transistor threshold etc., but owing to reduce frequency of operation, so do not need in the present embodiment to transistorized threshold value optimization.Can adopt and make in the present embodiment needs high-tension pixel switch, and the cmos circuit of the multi-crystal TFT (film of gate insulating film saves as 90nm) that selector circuit 107 workable technology same process make constitutes peripheral circuit.
Embodiment 26
The 26th embodiment of the present invention makes the tft array of polysilicon (poly-Si), constitutes reflection display device.According to Figure 35, Figure 36, after forming silicon oxide film 11 on the glass substrate 10, make amorphous silicon 12 growths, anneal with excimer laser then, make amorphous silicon multi-crystal silicification (Figure 35 (a)), make the oxide growth (Figure 35 (b)) of 10nm again.
Behind pattern-forming, by to the photoresist pattern-forming, Doping Phosphorus ion (P) has formed source electrode and drain region (Figure 35 (c)) of n channel TFT.
After making oxide film 15 growth of 90nm again, (μ-c-Si) 16 and tungsten silicon compound (WSi) 17 growths, pattern forms grid shapes (Figure 35 (d)) to make microcrystal silicon.
After silicon oxide film and silicon nitride film are grown continuously, open the hole (Figure 36 (f)) that connects usefulness, form aluminium and titanium, carry out pattern-forming (Figure 36 (g)) with sputtering method.
Then apply organic membrane, adopt and realize that substantially the mask of concaveconvex structure carries out pattern-forming at random.Open the hole that connects usefulness once more, form aluminium and titanium, carry out pattern-forming, as reflection pixel capacitors (reflecting plate) with sputtering method.
On the TFT substrate, spray the silicon dioxide spacers of 3.5 μ m.In addition, the encapsulant of using in the external coated ultraviolet curing of pixel area of relative substrate.With after TFT substrate and the relative substrate bonding, inject liquid crystal.Liquid crystal material uses nematic liquid crystal, adds chirality (chiral) material, and frictional direction is cooperated, and having made torsion angle is that 67 spiral fashions of spending are to row (TN) type.
In addition, the color filter on the relative substrate adopts the concentration that is suitable for reflection-type and constitutes, the material of tone.Also, contrast height, the reflection-type liquid-crystal display device that reflectivity is high have been realized by adopting correction plate, reaching the polarization plate of optimizing.
The circuit that uses constitutes the formation of the Figure 18 that is the 12nd embodiment in the present embodiment.In this constituted, the common electric power current potential (Vcom) of substrate was the type of drive of per 1 sweep trace counter-rotating relatively.The voltage that is added to like this on the liquid crystal is 5V amplitude (transistor of driving data lines is that 5V drives) to the maximum.
Present embodiment is owing to be reflective liquid crystal, so do not need the back backlight, can realize the liquid crystal indicator of low power consumption more than above-mentioned the 25th embodiment.
Embodiment 27
Organic EL is used as display device.After tft array and above-mentioned the 26th embodiment made equally, form element-isolating film, carry out pattern-forming.Form hole injecting layer, luminescent layer with the ink-jetting pattern manufacturing process successively then.In this operation, used and had and to carry out pattern-forming to the ink-jetting pattern building mortion of the control gear of optional position ink-jet to hole injecting layer and luminescent layer.Encapsulate after forming negative electrode.
The circuit that uses constitutes the formation of the Figure 23 that is the 16th embodiment in the present embodiment.In the present embodiment, can drive organic EL, obtain good demonstration.
Represented the formation of type scanner spare successively in the above-described embodiments.Also can adopt this by two storeies are set in pixel unit, the data of 2 fields of storage in two storeies scan successively to the screen of full frame single pass.
Action effect to the above embodiments describes below.
(1) the integral with drive circuit display device by the interior DAC of being equipped with circuit and in the controller IC of storer is housed, so can significantly reduce the IC cost.
Be not equipped with in the integral with drive circuit display device of DAC circuit in inside, do not need controller IC but need the driver IC of tape storage.In Fig. 3, represented for the driver IC of interior device, memory and in the controller IC of device, memory, the relation of the memory span of interior dress and IC cost.The cost of IC increases along with the increase of memory span.In relatively during the controller IC of the driver IC of device, memory and interior device, memory, the controller IC of the interior device, memory cost of half of only having an appointment as can be seen.Like this, by the present invention, can be easy to reduce cost.
(2) consumed power of reduction interface circuit.
The relation of having represented read frequency (MHz) and interface circuit consumed power among Fig. 4.As can be seen from Figure 4, when read frequency descends an order of magnitude, the consumed power order of magnitude that also descends substantially.
By increasing the highway width of drawing, reduced read frequency in the present invention from the interior controller IC that storer is housed.By the reduction of this frequency, can reduce consumed power significantly.
Embodiment 28
Below the 28th embodiment of the present invention is described.Following special concern consumes function, as a comparative example, when the circuit formation with existing display device compares, can reduce consumed power why to the present invention and be elaborated.At first, as a comparative example, the power consumption in the typical case of existing well-known multi-crystal TFT-LCD formation is investigated.
Figure 39 represents as a comparative example, uses the figure of structural design one example of the display device when having principle of compositionality now.The example that an element circuit of the shift register that uses in Figure 39 (66-bit Shift-Register), data register (DATA REGISTER), load lock storage (LOAD-LATCH), level shifter (Level-Shifter) constitutes is respectively as shown in Figure 40, Figure 41, Figure 42, Figure 44.Figure 43 is the sequential chart that the system of expression Figure 39 regularly moves.In order to illustrate and relatively, be set at consistent at the concrete numerical value shown in Figure 39 with the specification of the display device (with reference to Figure 45) of the 28th embodiment of the present invention that illustrates later on.
According to Figure 39, Digital Image Data DB0～DB5 (for example 0-3.0V), is exported from impact damper (Buffer) to for example 0-10V by level shift circuit (Level Shifter) level shift.In addition, the clock CLK that supplies with 66 shift register (66-bit Shift-Register) also carries out level shift by level shift circuit (Level Shifter).Supply with shift register (6-bit Shift-Register) from the signal of 4 bit widths of CLK, the XCLK of impact damper (Buffer) output, D1, D2.66 data registers (DATA REGISTER) are parallel to be provided with and to latch timing signal Rn (n=1～66) by 66 shift register (66-bit Shift-Register) output, be taken into the data-signal of data bus DB0～DB5 of 6, by the latch cicuit of its complementary signal XRn storage maintenance.
In the shift register (66-bit Shift-Register) of Figure 40, by the 1st clock phase inverter; Import the phase inverter in the output that is connected the 1st clock paraphase position; And input is connected in the output of phase inverter, and output is connected the 2nd clock phase inverter component unit latch cicuit in the output of the 1st clock phase inverter, and the shift register of Figure 40 has the latch of 66 grades of series connection forms of data register (6b-DATA REGISTER) number.2 grades of latchs and the clock signal complementation that is input to corresponding clock phase inverter (CLK and XCLK), per 2 sections latchs constitute the master-slave type latch.From 66 outputs of shift register, output data latch latch timing signal R1～R66.This latchs timing signal R1～R66 and controls (as shown in Figure 43, DST is that high level, D1 are high level, then R1 is a high level) by supply control signals of shift registers DST, D1, D2.In addition, load lock storage (LOAD-LATCH) is carried out the 1st clock phase inverter of break-make as shown in Figure 42 by clock DCL; Input is connected the phase inverter of the 1st clock phase inverter; And import the output that is connected phase inverter, and output is connected the 2nd clock phase inverter component unit latch cicuit that break-make was gone up, undertaken by the complementary clock XDCL of clock DCL in the output of the 1st clock phase inverter.
Level shift circuit (Level Shifler) as shown in Figure 44, connect the grid and the drain electrode of the interconnected 1 pair of P type MOS transistor of drain electrode at 10V one top-cross fork, and has 1 a pair of N type MOS transistor that between the drain electrode of 1 pair of P type MOS transistor and ground, connects, on the grid of 1 pair of N type MOS transistor, data (0-3V) and the input of complementary signal difference, taking out amplitude is the output signal of 0-10V.
In the formation shown in Figure 39, go up by desirable timing at 66 6b-DAC (6 figure place mode converter), the input digital image data during keeping necessarily, dispose 6 * 66bit load lock storage (LOAD-LATCH) simultaneously.On this load lock storage,, connect 6bit data register (6b-DATA-REGISTER) by shift register (66b-Shift-Regisler) addressing with 66 circuit, bus mode in order to write Digital Image Data.These logical circuits, promptly digital signal processing circuit is driven by 10V or the supply voltage more than the 10V.Therefore, the digital signal that connects 6 digital data buss of 6bit data register (6b-DATA-REGISTER) is also used level shifting circuit (Level-Shifter), by 10V or the amplitude driving more than the 10V.
And, this digital data bus, and the clock cable that drives shift register on display device substrate, at full throttle drive.Figure 43 represents to drive the sequential chart of the control line of this control device.
The back will be narrated, when display device being designed with this existing structure, and the flat-out pact half (remaining major part is consumed by DAC) that the digital signal processing circuit that is made of foregoing circuit will consume on the glass substrate to be consumed.Thereby the power of trying every possible means to reduce this digital signal processing circuit is useful.
Through investigation, the Elements Of Expense of following (a)～(c) is arranged to above-mentioned digital signal processing circuit power.
(a) digital data bus has very big stray capacitance.Its first reason is the connected causes of a lot of data registers.Second reason is to be connected to branch line on the data register from bus, on layout because bus is intersected the cause that produces a lot of mutual lines couplings.
1 element circuit and the bus D0～D5 that in Figure 41, have represented 6 bit data register (6b-DATA-REGISTER) of Figure 39.
(b) above-mentioned digital data bus on glass substrate with the highest frequency drives.In addition, drive the clock cable (CLK of Figure 39, XCLK) of shift register (66b-Shift-Regisler) too with the highest frequency drives.
(c) level shifting circuit (Lcvel-Shifler) (for example with reference to Figure 44) consumes a lot of power.
Thereby present inventors recognize by reducing these factors, can reduce consumed power.That is,, the structural design of new display device is proposed in view of above-mentioned power consumption factor.
Figure 45 represents to constitute the formation of the display device of the 28th embodiment of the present invention.The display device of in Figure 45, having represented parallel organization involved in the present invention.In addition, according to the design specification shown in the table 1, integratedly on glass substrate resembling the DAC that number is 176 * RGB * 234,6bit gray scale (260,000 look), is the LCD that 30Hz drives 3V digital interface (3.0V Interface) with frame frequency.
Table 1 display device specification of the present invention
| Project | Value |
| Number of picture elements | 176×RGB×234 |
| Frame frequency | 30fps |
| Grey | 6 (demonstration of 260,000 looks) |
The display device that the embodiment of the invention shown in Figure 45 is related, has the display unit viewing area (Display Area) that on the intersection point of multidata line (N bar) and multi-strip scanning line (M bar), has by the capable N row of rectangular configuration M pixel clusters at display device substrate (glass substrate among Figure 45 (Glass Substrate)), has control device (Cantroller FrameMemovy), comprising: storage (the pixel amount of M * N) (that is display-memory (FramcMemory) of B position (being 6 in Figure 45) the gray scale video data of (M * N * B) position); From display-memory sense data (Digital Image Data) and to the output buffer of above-mentioned display screen substrate (Glass Substrate) side output; And control above-mentioned display-memory and above-mentioned output buffer, and communicating by letter and the controller of control between management and epigyny device.In control device, the configuration of above-mentioned output buffer will be equivalent to above-mentioned storer (in the position of M * N * B) 1 row amount (quantity of cutting apart the position several S by piece of N * B) and P { (N * B)/(P * S) } cut apart mutually are individual.
In the example shown in Figure 45, N=176 * 3 (RGB amount)=528, M=234, S=8, P=2.The bar number of the data line (signal wire) of viewing area (Display Area) is that S001～S528 amounts to 528, the data number of lines of data bus (the output buffer number of control device) is { (N * B)/(P * S) }=528 * 6/ (8 * 2)=66 * 3=198, between controller IC (Coulroller Frame Memory) and glass substrate (GlassSubstrate), the data bus of Digital Image Data (Digital Image Data) transmission usefulness is provided with totally 198 of D001～D198, with the transfer rate driving of 125KHz.
On the data line drive circuit (Data Driver) that drives the viewing area data line on the glass substrate (Glass Substrate), by the data bus of { (N * B)/(P * S) } bit wide, transmitting and displaying data (Digital Image Data).In 1 horizontal period, the data image data of { (N * B)/(P * S) } bit wide are cut apart (P * S) inferior, the video data of transmission 1 row amount.In the example shown in Figure 45, the data of 198 bit wides (D001～D198) cut apart 2 * 8 times, the video data of transmission 1 row amount.
Data line drive circuit (Date Driver) on the glass substrate (Glass Substrate) comprising: level shift circuit, be to common P the level shift circuit (LS) that connects of 1 data line in the data bus, with the slave controller device output towards P phase signals amplitude device output, that obtain successively by data line respectively level shift arrive more high-amplitude signal; P phase demodulation circuit (SPC) has according to drive clock and respectively the output of P above-mentioned level shift circuit is latched, and the serial bit data of P phase is launched into parallel position, with the latch cicuit (LATS) of P bit parallel data latching output.Data bus for { (N * B)/(P * S) } bar data line, have (N * B)/(P * S) } individual this P phase demodulation circuit (SPC).Have (N/S) individual from { (N * B)/(P * S) } individual P phase demodulation circuit (SPC), and line output { (the digital to analog conversion circuit (being called " DAC circuit ") of the output of the data of N * B)/S} position, input B position wherein and output simulating signal, comprise the output of the individual above-mentioned DAC circuit of reception (N/S), output to the selector switch of the N bar data line of display unit.
In the formation shown in Figure 45, the parallel setting of 2 phase demodulation circuit (SPC) that constitutes by 2 level shift circuits (LS) and a plurality of latch cicuit (LATs) (N * B)/(P * S) } individual, promptly { (528 * 6)/(2 * 8) }=66 * 3=198.Certainly, this number equates with the bar number of data signal line D001～D198.From 198 2 phase demodulation circuit (SPC) output { (528 * 6)/8}=66 * 6=396 position (data of G001～G396).The DAC circuit (6b-DAC) that also has (N/S)=528/8=66 6, the output (66 aanalogvoltage output) of 66 DAC circuit (6b-DAC) is received as input, (selector switch of S001～S528) constitutes with 1 pair 8 demultiplexer to output to N bar (528) data line of display unit (Displey Area).1 pair 8 demultiplexer is divided into 8 outputs with 1 bars.This demultiplexer (1-to-8DEMUX) has (N/S)=66.Selector circuit (1-to-8DEMUX * 66) receives the output of 66 DAC circuit (6b-DAC), according to selector control signal, be divided into piece in output (66 aanalogvoltage output) and cut apart for several 8 time, successively 66 data line-groups are supplied with data-signal 66 DAC circuit.Also has the alive successively scan line drive circuit of multi-strip scanning line (Scan Line Drlver) to display unit (Display Area).
Control device is supplied with clock (CLK) (frequency is 62.5KHz), horizontal-drive signal (Hsymc), vertical synchronizing signal control signals such as (Vsync) to the level shift circuit on the glass substrate (Level Shifter (2)).With data bus, these clocks, control signal are comply with the interface in 3.0V.(among the Level Shifter (2), clock, control signal level conversion to the 10V system, are exported to timing circuit (Timing Circuit) at level shift circuit.Timing circuit (Timing Circuit) with the clock (CLK) of 10V amplitude, and the complementary clock XCLK of clock (CLK) supply with SPC etc.In addition, power circuit (Power) to glass substrate supply line voltage 10V ,-5V etc.
Like this, sampled level conversion and 2 phase demodulation circuit (SPC), 6bit DAC, 1 pair of 8 demultiplexer (1to 8DEMUX) that integrated data driver (DATA Driver) is used by the 3V interface on glass substrate constitute.
Figure 46 is the example of 1 element circuit (being connected the SPC on 1 data-signal D (n)) of the 2 phase demodulation circuit (SPC) of expression Figure 45.This 2 phase demodulation circuit (SPC) (1 bit serial data-switching being become the circuit of 2 bit parallel data), (2 sampled level shift circuits (LS) on 0～3v) and be connected a plurality of latch cicuits (LAT) in each output of 2 sampled level change-over circuits (LS), each latch cicuit is latched the input data by sampling clock CLK and complementary clock XCLK thereof to comprise the output D (n) that is connected data buffer jointly.
The 1st sampled level shift circuit (LS) of upside in the SPC of Figure 46, be included between high potential power (being 10V in this example) and the low potential power source (GND) with formation the 1st to the 3rd on-off element of series connection form connection the 1st to 3MOS transistor (P1, N3, N2); Be connected the 1st, the electric capacity (C2) on the tie point of 2MOS transistor (P1, N3); Between the gate terminal that is connected in input terminal on the D (n) and 3MOS transistor (N2), and constitute the 4MOS transistor (N1) of the 4th on-off element; And be connected capacitor C 1 on the grid of 3MOS transistor (N2).The 1st, on the grid of 2MOS transistor (P1, N3), import the 1st sampling clock (CLK) jointly (0-10V), on the grid of 4MOS transistor (N1), the 2nd sampling clock (XCLK) that input is complementary with the 1st sampling clock (CLK).
The following describes the action of this sampled level shift circuit (LS), when the 1st sampling clock (CLK) is low-voltage (during the initialization), constitute MOS transistor (P1) conducting of the 1st on-off element, and the MOS transistor (N3) that constitutes the 2nd on-off element is ended, and electric capacity (C2) is charged by the supply voltage of high potential power.When the 2nd sampling clock (XCLK) is high level, constitute MOS transistor (N1) conducting of the 4th on-off element, electric capacity (C1) is charged by applied signal voltage.
When the 1st sampling clock (CLK) is high level (between period of output), the MOS transistor (P1) that constitutes the 1st on-off element is ended, and constituting MOS transistor (N3) conducting of the 2nd on-off element, the terminal voltage of electric capacity at this moment (C2) takes out as output signal directly or indirectly.Sampled level shift circuit (LS) is contained on the glass substrate, and 1MOS transistor P1 is made of P type TFT, and the 2nd to 4MOS transistor N3, N2, N1, constitute by N type TFT (Thin Film Transistor).
The 2nd sampled level shift circuit (LS) of the SPC downside of Figure 46 constitutes too, and the connection of sampling clock is different with the 1st sampled level shift circuit (LS).Common input the 2nd sampling clock (XCLK) the 1st, on the grid of 2MOS transistor (P1, N3), input the 1st sampling clock (CLK) on the grid of 4MOS transistor (N1).(between period of output) constituted when (during the foundation) and the 2nd sampling clock (XCLK) were for high level when the 2nd sampled level shift circuit (LS) was low level by the 2nd sampling clock (XCLK), carried out the action complementary with the 1st sampled level shift circuit (LS).
Adopt the sampled level shift circuit of the present invention (LS) shown in Figure 46, desirable following action effect.
(a) owing to not flowing through steady current, so consumed power is low.
(b) owing to be single-phase input (=do not need reversal data), so number of terminals few (general level shifting circuit needs data and 2 inputs of reversal data).
(c) on input terminal, can not produce the current potential of high voltage end, the possibility of destroying the low-voltage end circuit is little.When latching the type sensor amplifier when being used for level shifter shown in Figure 44, on input terminal, can produce the current potential of high voltage end sometimes.
Under the situation of multi-crystal TFT, LCD, for example can have 200 data input terminals, when the purposes of multidata like this sampling of needs and level shift, the present invention is effective especially.
As shown in Figure 46, in 2 phase demodulation circuit (SPC), have the 1st, the 2nd sampled level shift circuit (LS), common input input signal D (n) on the 1st and the 2nd sampled level shift circuit, on the 2nd sampled level shift circuit, comprise: the 1st of the 1st sampled level shift circuit, the 2nd sampling clock signal (CLK, the signal of the value of value counter-rotating XCLK) (is XCLK, CLK), as the 1st, the 2nd sampling clock, be input to corresponding on-off element respectively, be taken into the 1st latch (LAT) of the output of the 1st sampled level shift circuit according to preceding the 1st sampling clock signal (CLK); Latch the 2nd latch (LAT) of the output of output the 1st latch (LAT) according to the 2nd sampling clock signal (XCLK); The 3rd latch (LAT) that latchs output according to the 1st sampling clock signal (CLK) output the 2nd latch (LAT); Be taken into the 4th latch (LAT) of the output of the 2nd sampled level shift circuit according to the 2nd sampling clock signal (XCLK); And the 5th latch (LAT) of exporting the output of the 4th latch according to the 1st sampling clock signal (CLK).1st, the 2nd latch constitutes the latch of the 1st master-slave type, and the 4th, the 5th latch constitutes the latch of the 2nd master-slave type.Each latch (LAT) comprising: activated by the clock signal control of being imported, input and output are connected the 1st clock phase inverter on latch input terminal and the lead-out terminal; Import the phase inverter in the output that is connected the 1st clock phase inverter; And input is connected in the output of phase inverter, and output is connected the 2nd clock phase inverter in the input of phase inverter.1st, the 2nd clock phase inverter is controlled activation/non-activation by clock CLK and complementary clock XCLK respectively.
Figure 47 is the figure of this action waveforms of expression Figure 46, odd number signal (G (2n-1)) in the output of the latch of 3 grades of series connection, and the latch output of 2 grades of series connection in even number signal (G (2n)), with the 1st sampling clock signal (CLK) output of running simultaneously.
In the display device shown in Figure 45, Digital Image Data (Digital Image Data) is imported from peripheral control unit IC with 3V amplitude, 198 bit widths, by digital signal processing appliance circuit (array of SPC), signal level is converted to the 10V amplitude, supplies with DAC by required timing.The output of 1 DAC drives 8 data lines that are connected on the cell array (Display Area) with demultiplexer (DEMUX) with timesharing.
The characteristics of this formation are through having the interface of big highway width (198 bit width), supply with data with low speed, and these data 2 phase demodulation circuit (SPC) with level conversion function with parallel drive on glass substrate are handled.Like this, owing to, carry out digital signal processing, so be called " parallel digital data drives structure " by a plurality of phase demodulation circuit of parallel drive.
In table 2, this parallel digital data drives structure and existing structure are compared, why consumed power is low to investigate this parallel organization.
The comparison of table 2 structure
| ? | Existing structure | The parallel drive structure |
| Digital Image Data interface bus width | 6bit (1) | 198bit (33) |
| Clock frequency | 2.1MHz (1) | 62.5kHz (1/33) |
| Be connected the number of transistors on the clock cable | 396 (1) | 5148 (13) |
| Crossing number between digital data bus and branch line thereof | 975 | 0 |
Expression ratio in ()
Parallel drive structure of the present invention, by widening the interface bus width of Digital Image Data, 198 2 phase demodulation circuit of parallel drive (SPC), thus under the constant situation of the appearance ability perhaps kept, make clock frequency be reduced to 62.5kHz from 2.1MHz.
The digital signal processing circuit of DAC front (input one side of DAC) configuration, in parallel drive structure of the present invention, on the clock cable that drives by 62.5kHz, connect 5148 transistors, and existing structure connects 396 transistors on the clock cable of the shift register that is driven by 2.1MHz.
When in calculating each structure, being connected number of transistors on the clock cable and clock frequency long-pending, parallel organization less.That is, along with the consumed power that discharges and recharges of clock cable, parallel organization is less.
In addition, in parallel organization, owing to do not exist the mutual line between digital data bus and its branch line to be coupled, so its power that discharges and recharges is 0.
To mutual line coupling, i.e. certain wiring of transmission of digital data describes at the electric capacity with certain the wiring place of intersecting generation of transmitting other numerical datas below.
In the example shown in Figure 39, the data-bus width of input is 6, and data-bus width that launch by the phase demodulation circuit by shift register (66-bit Shift-Register), data register (DATA-REGISTOR) and load lock storage (LOAD LATCH) formation, behind the phase demodulation is 6 * 66.
At this moment, to count be 975 intersecting between bus and its branch line.In general, the wide data bus of input is the n position, and when the highway width by phase demodulation circuit output was k * n position, the number C of mutual line coupling was expressed as
C＝n(n-1)(k-1)/2
N=6, k=66 in above-mentioned example.Under the situation of the phase demodulation circuit that constitutes by existing bus that constitutes and connected data latches, can not reduce the number of this mutual line coupling.
Relative therewith, in the present invention, because the number of this mutual line coupling is 0, so can realize low consumpting powerization.
In general, parallel organization will make circuit scale increase, (when making clock frequency reduce to 1/n, for obtaining the same appearance ability of being permitted, circuit scale need increase n doubly), do not increase but but have so during this digital interface circuit, number of transistors is about 8600 in the existing structure, and the parallel drive structure is 9900.
The consumed power of the digital signal processing circuit in Figure 50 in contrast expression parallel digital data drives structure of the present invention and the existing structure.
In removing the logical block of level shifting circuit, comprise discharging and recharging of stray capacitance, reduce to 0.82mW from 5.8mW.
As a result, the consumed power of digital signal processing circuit, by adopting parallel digital data activation configuration of the present invention, per 1 display screen can reduce to 1.08mW from 12.5mW.
The power of new level shifting circuit (LS) Unit 1 (level shift circuit (New Level Shifter) in Figure 49 dotted line) shown in Figure 46 as shown in figure 49.In new level shifting circuit, data rate is the number μ W orders of magnitude during for 200KHz.As among Figure 46 relatively shown in, in existing level shifting circuit shown in Figure 44, data rate is 47 μ W when being 35 μ W, 200kHz when being 25 μ W, 150kHz during for 100kHz.
In addition, structure of the present invention, the highest Action clock on the display base plate (Glass Substrate) is 62.5kHz, compares with existing 2MHz and significantly reduces.Like this, the margin of operation of circuit is very big.
Figure 48 is the figure that measures 2 phase demodulation circuit (SPC) maximum operation frequencies (maximum clock frequency) with level conversion function.As can be seen from Figure 48, applied signal voltage (Input Date Voltage) when being 3V, is worked more than 3MHz.Can find out that also supply voltage VDD also can further reduce from 10V, like this, because supply voltage is reduced, thus can realize low consumpting power.More than describe the present invention by the various embodiments described above, but the present invention is not limited to the formation of the foregoing description, is also included within the constructible various distortion of practitioner, modification in the invention scope of claim of patent claim certainly.The effect of invention
As mentioned above, can obtain Xiao fruit Xia the Yi according to the present invention.
The 1st Xiao of the present invention really is by the integral with drive circuit Xian showing device with in-built DAC circuit and the controller IC of in-built memory, can decrease IC cost.
The 2nd Xiao of the present invention really is by the Zong line width that goes out from the controller IC Yin of in-built memory being widened, can be reduced read frequency, and reduces the consumed power of interface circuit.
The 3rd Xiao of the present invention really is the Ying Xiang that can ignore EML. Its Yuan has reduced the frequency that data are processed because being utilization by thick Zong Xian. When processing the frequency reduction, EMI Zao sound Zhou subtracts, so can ignore the Ying Xiang of EMI.
The 4th Xiao of the present invention can make the same technology Zuo one-tenth of Yong in the substrate. When Xian You technology Zai Xing became various component, used various technologies according to the voltage that uses on each circuit. The frequency that Zai Zhong of the present invention, You Yu process is low, so the single technology Zuo of circuit group Yong of ceiling voltage becomes all circuit groups as required, and work that just can be without a doubt.
The 5th Xiao of the present invention really is the reliability that can improve the Xian showing device. Its Yuan is because being that Zai can make Zhong of the present invention the operating frequency control of circuit very low. When operating frequency is low, the Ya power of each Yuan spare is just diminished, so Reliability Enhancement. Merely estimate it is that frequency reduces ratio and the rising ratio of service time is proportional continuously. That is Reliability Enhancement when, frequency reduces. In addition, there is not above-mentioned EMI Ying Xiang that Reliability Enhancement is cut much ice yet.
The 6th Xiao of the present invention has current/charge-voltage convertor, can the drive current driving element. Can realize the Xian showing device of fine, many gray scales, low cost, low consumpting power by Zhe Xie Xiao fruit.
Claims (3)
1. a display device has the digital displaying data that reception is supplied with from epigyny device, will be added to the data line drive circuit on the data line corresponding to the signal of video data, it is characterized in that:
At least digital displaying data is being carried out in the circuit of phase demodulation, the wiring of any in the wiring of transmitting display signal therefor and other transmitting display signal therefors except this wiring does not intersect.
2. a display device has the video data that reception is supplied with from epigyny device, and this video data is carried out the circuit of phase demodulation, it is characterized in that:
Certain signal wire of the digital signal of transmission before the phase demodulation intersects to count and (k-1)/2 lack than C=n (n-1) with other signal wires intersect, and wherein, n represents the also line number of the video data supplied with, and k * n represents the also line number of the video data behind the phase demodulation.
3. a semiconductor device has the video data that reception is supplied with from epigyny device, and this video data is carried out the circuit of phase demodulation, it is characterized in that:
Certain signal wire of the digital signal of transmission before the phase demodulation intersects to count and (k-1)/2 lack than C=n (n-1) with other signal wires intersect, and wherein, n represents the also line number of the video data supplied with, and k * n represents the also line number of the video data behind the phase demodulation.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001307398 | 2001-10-03 | ||
| JP307398/2001 | 2001-10-03 | ||
| JP2002142536 | 2002-05-17 | ||
| JP142536/2002 | 2002-05-17 |
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| CNB021443270A Division CN100437717C (en) | 2001-10-03 | 2002-10-08 | Displaying device |
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| CN101312031A CN101312031A (en) | 2008-11-26 |
| CN101312031B true CN101312031B (en) | 2011-06-22 |
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| CN2008101251783A Expired - Lifetime CN101312032B (en) | 2001-10-03 | 2002-10-08 | Display device |
| CN 200810125179 Expired - Lifetime CN101312033B (en) | 2001-10-03 | 2002-10-08 | Display device |
| CN2008101251779A Expired - Lifetime CN101312031B (en) | 2001-10-03 | 2002-10-08 | Display device and semiconductor device |
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| CN 200810125179 Expired - Lifetime CN101312033B (en) | 2001-10-03 | 2002-10-08 | Display device |
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| CN106910455B (en) * | 2015-12-22 | 2019-04-19 | 比亚迪股份有限公司 | LED control system and control method for LED control system |
| CN110912549A (en) * | 2019-12-05 | 2020-03-24 | 京东方科技集团股份有限公司 | Serial-parallel conversion circuit, driving method thereof and display panel |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0921517A2 (en) * | 1997-12-08 | 1999-06-09 | Sel Semiconductor Energy Laboratory Co., Ltd. | Signal dividing circuit and semiconductor device |
| US6331844B1 (en) * | 1996-06-11 | 2001-12-18 | Kabushiki Kaisha Toshiba | Liquid crystal display apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87103505A (en) * | 1986-04-25 | 1987-11-04 | 精工电子工业株式会社 | The interfacing equipment of thin display |
| US6011533A (en) * | 1995-08-30 | 2000-01-04 | Seiko Epson Corporation | Image display device, image display method and display drive device, together with electronic equipment using the same |
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2002
- 2002-10-08 CN CN2008101251783A patent/CN101312032B/en not_active Expired - Lifetime
- 2002-10-08 CN CN 200810125179 patent/CN101312033B/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331844B1 (en) * | 1996-06-11 | 2001-12-18 | Kabushiki Kaisha Toshiba | Liquid crystal display apparatus |
| EP0921517A2 (en) * | 1997-12-08 | 1999-06-09 | Sel Semiconductor Energy Laboratory Co., Ltd. | Signal dividing circuit and semiconductor device |
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| CN101312032B (en) | 2011-02-16 |
| CN101312032A (en) | 2008-11-26 |
| CN101312033A (en) | 2008-11-26 |
| CN101312031A (en) | 2008-11-26 |
| CN101312033B (en) | 2013-09-18 |
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