CN101315948B - Spinning transistor - Google Patents
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- CN101315948B CN101315948B CN200710099739A CN200710099739A CN101315948B CN 101315948 B CN101315948 B CN 101315948B CN 200710099739 A CN200710099739 A CN 200710099739A CN 200710099739 A CN200710099739 A CN 200710099739A CN 101315948 B CN101315948 B CN 101315948B
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Abstract
The invention discloses a complete-metal PNP and NPN-typed spin transistor device. The spin transistor is a multi-layer film structure and comprises an emitter layer, a base layer, a collector layer, a first ferroelectrics layer which is formed between the emitter layer and the base layer and a second ferroelectrics layer which is formed between the base layer and the collector layer; the emitter layer, the base layer and the collector layer are made of metal or semi-metal material. The complete-metal PNP and NPN-typed spin transistor device of the invention overcomes the shortages that the existing spin transistor device is not easy to be operated and the magnification is low; furthermore, the complete-metal PNP and NPN-typed spin transistor device of the invention is a spin transistor which stably works in room temperature, has radio-resistance and is completely based on the working principle of PN-junction.
Description
Technical field
The present invention relates to a kind of and solid-state switch and amplifying device spin dependence, relate more specifically to PNP, the NPN type spin transistor device of all-metal or semimetal.
Background technology
Based on PNP, the NPN transistor of semiconductor PN is primary element in the semiconductor integrated circuit, has a wide range of applications in semiconductor electronic industry.Common semi-conducting material, its intrinsic crystal conductivity is very weak, is the N type semiconductor of main charge carrier or is the P type semiconductor of main charge carrier with the hole and make semi-conducting material become with electronics by the impurity element of introducing different valence state.Suitable P type and N type semiconductor are combined, and the charge carrier between P type semiconductor and the N type semiconductor causes near interface to form the free carrier depletion layer that exists with the internal electric field form owing to have the electron concentration difference and the phase counterdiffusion.The foundation of internal electric field will hinder the diffusion of the majority carrier in the semiconductor, when the applying bias electric field is identical with the internal electric field direction, will further hinder the diffusion of many sons, and PN junction presents high-resistance state; And the applying bias electric field is when opposite with the internal electric field direction, and internal electric field helps the diffusions of many sons with weakened or offset, and this moment, PN junction presented low resistance state.Based on this, in PNP transistor (collector electrode, base stage, emitter), electronics is entered by base stage, flows to emitter under the effect of voltage, and its principle is identical with PN junction, forms base current.Meanwhile, making alive between collector and emitter, because there is the conducting electric current in base stage, electronics is in nonequilibrium state, and base region very thin (several microns are to tens microns), nonequilibrium state electronics in the base region can be upset the space charge region between collector electrode and base stage, and it is mobile that electronics in this PN junction is taken advantage of a situation, and formed current paths.Because the collector area hole density manys hundreds of times than the base region, most electronics pass through thus, so its current ratio base current is much bigger, and are with the proportional increase of base current, have so just formed transistorized enlarge-effect.The operation principle of NPN transistor similarly.
Known spin transistor device, such as having proposed one by ferromagnetic metal emitter, " ferromagnetic metal/nonmagnetic metal/ferromagnetic metal " sandwich all-metal spin transistor that thickness is formed less than nonmagnetic metal base stage and another ferromagnetic metal collector electrode of spin diffusion length in the document 1 " M.Johnson; Science 260 (1993) 320 " of Johnson in 1993, but this structure does not have machinability; Because non-magnetic metal layer is if less than spin diffusion length, just must be less than 100 nanometers, and this structure is horizontal cooked mode, it is very difficult will covering a grid on the layer less than 100 nanometers again, in addition, since can not disposable film forming, the crystal growth structure of non-magnetic metal layer is uncontrollable, therefore the instability that can cause producing device.The IBM experimental group has proposed unipotential base MTJ spin transistor for another example, and its structure is: metal (emitter)/aluminium oxide/ferromagnetic metal (base stage)/semi-conducting material (collector electrode); Yet because the Schottky gesture between base stage and the collector electrode makes this transistorlike have following shortcoming: (1) lacks the effective control to base stage-inter-collector operating voltage; (2) hour there is bigger leakage current in the voltage between emitter-base stage; (3) collector electrode conducting electric current is too small, causes the enlargement ratio deficiency.Disclose in the document 2 of S.Yuasa in 2002 " S.Yuasa; Science297 (2002) 234 " for another example in the MTJ of unipotential base and found spin polarization resonance tunnel-through phenomenon, can utilize the resonance tunneling effect of bibarrier tunnel junction to make the resonance tunnel-through spin transistor.Though this method can overcome above-mentioned the problems of the prior art, but because the quantized level of the work that relies on depends on the thickness in bibarrier tunnel junction intermediate layer, the contact and the working temperature at each interface, thereby cause the extremely difficult control of quantized level, and processing is very difficult.
In view of the deficiencies in the prior art, just need a kind of new spin transistor, wish that this spin transistor is easy to control and the enlargement ratio height, preferably can also steady operation in room temperature environment, have radiation resistance.
Summary of the invention
The objective of the invention is to overcome the deficiency that existing spin transistor device is not easy to control, enlargement ratio is low, thus the spin transistor that providing a kind of is easy to control, enlargement ratio is high.
To achieve these goals, the invention provides a kind of spin transistor, comprise emitter layer, base layer and collector layer; It is characterized in that, also comprise: be formed on first ferroelectric layer between described emitter layer and the described base layer, be used to regulate the size of the space charge region between described emitter layer and the described base layer, be formed on second ferroelectric layer between described base layer and the described collector layer, be used to regulate the size of the space charge region between described base layer and the described collector layer, described emitter layer, described base layer and described collector layer adopt metallicity or semimetal material.
Because spin transistor of the present invention is fully based on the PN junction operation principle, so be easy to control; Utilize the insulating barrier of ferroelectric layer, regulate the size of the space charge region of metallicity or semimetal storeroom, effectively strengthened the intensity of The built-in electric field, thereby made spin transistor of the present invention have transistorized amplification of general semiconductor and rectification characteristic; And the conducting of spin transistor is consistent with semiconductor transistor with amplification principle.
Further, in order to form the positive-negative-positive spin transistor, the material of described emitter layer is cavity type magnetic metal or semimetal material, ferromagnetic perovskite type manganese oxide material, Fe such as preferred LaSrMnO
3O
4Or CrO
2Deng, layer thickness is 5nm to 1000nm; The material of described base layer is an electron type magnetic metal material, magnetic alloy material such as preferred Fe, Co, Ni, rare earth metal and Ni-Fe, Co-Fe, Co-Fe-B or Heussler alloy material etc., and layer thickness is 3nm to 100nm; The material of described collector electrode is cavity type magnetic metal or semimetal material, ferromagnetic perovskite type manganese oxide material, Fe such as preferred LaSrMnO
3O
4Or CrO
2Deng, thickness is 5nm to 1000nm; The material of described first ferroelectric layer, second ferroelectric layer is the ferroelectricity insulating material, preferred ferroelectric insulating material ScTiO
3, BaTiO
3Or PbTiO
3Deng, layer thickness is 5nm to 100nm.
Further, in order to form NPN type spin transistor, the composition material of described emitter layer is an electron type magnetic metal material, magnetic alloy material such as preferred Fe, Co, Ni, rare earth metal and Ni-Fe, Co-Fe, Co-Fe-B or Heussler alloy etc., and layer thickness is 3nm to 100nm; The material of described base layer is cavity type magnetic metal or semimetal material, ferromagnetic perovskite type manganese oxide material, Fe such as preferred LaSrMnO
3O
4Or CrO
2Deng, layer thickness is 5nm to 1000nm; The material of described collector layer is an electron type magnetic metal material, magnetic alloy material such as preferred Fe, Co, Ni, rare earth metal and Ni-Fe, Co-Fe, Co-Fe-B or Heussler alloy etc., and layer thickness is 5nm to 1000nm; The material of described first ferroelectric layer, second ferroelectric layer is the ferroelectricity insulating material, preferred ferroelectric insulating material ScTiO
3, BaTiO
3Or PbTiO
3Deng, layer thickness is 5nm to 1000nm.
Further, for above-mentioned positive-negative-positive or NPN type spin transistor, described emitter layer and described collector layer are formed at the both sides of described base layer respectively.
Further, can also be that for above-mentioned positive-negative-positive or NPN type spin transistor, described emitter layer and described collector layer are formed at the same side of described base layer.
Further, for above-mentioned positive-negative-positive or NPN type spin transistor, also comprise the emitter pinning layer and the collector electrode pinning layer that are respectively formed on described emitter layer, the described collector layer, the material of described pinning layer is antiferromagnetic materials, antiferromagnetic alloy material or the antiferromagnetic materials such as CoO, NiO, PtCr of Mn such as preferred Ir-Mn, Fe-Mn, Rh-Mn, Pt-Mn or Pd-Mn, described pinning layer thickness is 10nm to 100nm; Technical scheme as the front is described, and when selected emitter layer and collector layer had the big stupid power of sedan-chair, when promptly magnetic moment direction was difficult for by the change of outer place, this emitter pinning layer and collector electrode pinning layer can omit.
Further, for above-mentioned positive-negative-positive or NPN type spin transistor, the cross section of described emitter layer, base layer and collector layer is rectangle, ellipse or regular hexagon; Perhaps, the cross section of described base layer and collector layer has engraved structure, and the cross section of described engraved structure is straight-flanked ring, elliptical ring or regular hexagon ring; Or the cross section of described engraved structure is rectangle, ellipse or the regular hexagon that comprises rectangle hollow out, oval hollow out or regular hexagon hollow out.
Further, the minor face of the interior ring of described straight-flanked ring is 10nm to 100000nm, and the minor face of outer shroud is 20nm to 200000nm, and the ratio on minor face and long limit is 1: 1 to 1: 5, and ring width is 10nm to 100000nm;
The minor axis of the interior ring of described elliptical ring is 10nm to 100000nm, and the minor axis of outer shroud is 20nm to 200000nm, and the ratio of minor axis and major axis is 1: 1 to 1: 5, and ring width is 10nm to 100000nm;
The length of side of the interior ring of described regular hexagon ring is 10nm to 100000nm, and the length of side of outer shroud is 20nm to 200000nm, and ring width is 10nm to 100000nm;
The minor face of described rectangle is 10nm to 100000nm, and the ratio on minor face and long limit is 1: 1 to 1: 5;
Described oval-shaped minor axis is 10nm to 100000nm, and the ratio of minor axis and major axis is 1: 1 to 1: 5, and described ellipse comprises circle;
The described orthohexagonal length of side is 10nm to 100000nm.
Further, described spin transistor is the transistor of the multi-layer film structure that forms on substrate, and it also comprises described emitter layer, the base layer of the top that is arranged in described emitter layer, described base layer, described collector layer respectively, the metal lead wire of collector layer; Described substrate is the semiconductor monocrystal wafer, preferred SrTiO
3, MgO or LaAlO
3Single-crystal wafer; When described emitter layer and described collector layer are formed at the both sides of described base layer respectively, be positioned at outermost one deck in the multilayer film and directly link to each other with described substrate, the metal lead wire of described emitter layer, base layer and collector layer is parallel to each other; When described emitter layer and described collector layer were formed at the homonymy of described base layer, described base layer directly linked to each other with described substrate, and the metal lead wire of described emitter layer, base layer and collector layer is parallel to each other.
Further, described substrate can also be a SOI CMOS transistor substrate, also is formed with bit line on this substrate, the metal lead wire of word line and described emitter layer, base layer and collector layer; When described emitter layer and described collector layer are formed at the both sides of described base layer respectively, being positioned at outermost one deck in the multilayer film directly links to each other with described SOI COMS transistor drain, described bit line is connected with the transistorized source electrode of described SOI COMS, described word line is connected with the transistorized grid of described SOI COMS, the metal lead wire of described emitter is connected with described SOI COMS transistor drain, described emitter metal lead-in wire is arranged in the below of emitter layer, described base stage, the collector electrode metal lead-in wire is arranged in described base stage, the top of collector electrode, described emitter, the metal lead wire of base stage and collector electrode is parallel to each other; When described emitter layer and described collector layer are formed at the homonymy of described base layer, described bit line is connected with the transistorized source electrode of described SOI COMS, described word line is connected with the transistorized grid of described SOI COMS, described base metal lead-in wire is connected with described SOI COMS transistor drain, described base metal lead-in wire is arranged in the below of described base layer, and described emitter, collector electrode metal lead-in wire are arranged in the top of described emitter layer, collector layer.
Described SOI CMOS transistor substrate comprises: first semiconductor material layer, and thereon the buried oxidation layer and second semiconductor material layer of growth successively; This second semiconductor material layer is made of SOI CMOS transistor drain, grid and source electrode; According to employed environment difference, can select polytype SOI CMOS transistor substrate such as complete depletion type, double grid type, high temperature resistance type, anti-impulse type, anti-high-pressure type for use.
Compared with prior art, the present invention has following beneficial effect:
The invention provides NPN or positive-negative-positive spin transistor, thereby have following advantage with no hollow out or engraved structure:
This spin transistor utilization has ferroelectric insulating barrier, regulates the size of the space charge region between magnetic electron type metallic alloy and magnetic cavity type metallic alloy, has effectively strengthened the intensity of The built-in electric field; Thereby make the NPN, the positive-negative-positive spin transistor that make up by magnetic electron type metallic alloy and magnetic cavity type metallic alloy have transistorized amplification of general semiconductor and rectification characteristic; And the conducting of spin transistor is consistent with semiconductor transistor with amplification principle.In addition, described spin transistor is owing to use magnetic material, and its device performance can be modulated by external magnetic field, and can use under radiation environment and hot environment, has very strong flexibility and applicability.
Specifically, in existing ordinary semiconductor material transistor, the amplified current of output is irrelevant with spin information; And because in the semi-conducting material, carrier concentration is less than metal material, so carrier moving speed is lower, it is slow a lot of that the spin information that the speed of process information is carried than metal is wanted.In addition, because the semiconductor device carrier concentration is little, thus can not export bigger amplified current, otherwise cause the puncture of device easily, do not have overload protection function physically; Therefore, do not have the radioresistance characteristic yet.In existing diluted magnetic semiconductor material transistors, though output current and spin dependence are the inherent shortcoming that semi-conducting material can not effectively solve above-mentioned other semiconductor transistor eventually; And the type device can only be operated under the low temperature environment.In existing spin transistor based on resonance tunneling effect, owing to utilize quantum effect to regulate and control, the processing technology of the type device is very complicated; Transition between quantum level is relevant with temperature and external environment, so effective working temperature interval of such device is very narrow, and does not have the radioresistance characteristic.
So compared with prior art, the present invention is owing to the spin transistor unit that has adopted based on ferroelectric full magnetic metal PN junction framework, thoroughly solved with metallic alloy on the principle and made up a transistorized difficult problem, eliminated leakage current greatly, and in transistor, introduced spin correlation, guaranteed effective amplification of stable operation at ambient temperature of spin crystal and spin information; In addition, because metallic alloy itself has the radioresistance characteristic, so this design can be widely used in various environment.This spin transistor has used Openworks shape and no Openworks shape nanofabrication technique from processing technology, thereby can effectively reduce operating current, reduces power consumption, is convenient to be integrated in the large-scale circuit; And because the current drives effect of nano magnetic material, under big electric current, the base layer of this device can realize the magnetic moment counter-rotating, form high-impedance state, automatically reduce the output current size, by reverse current or externally-applied magnetic field initialization, can return original normal operating state again, have the automatic overload protection function of realization; At last, spin transistor of the present invention uses from material has the metallic alloy of magnetic, thereby can obtain bigger amplified current, and the enlargement ratio that the outside magnetic field effect down can trim has further guaranteed the stability and the flexibility of device.This spin transistor can adopt SOI CMOS (silicon-on-insulator CMOS transistor) substrate-like to become functional unit, because described SOI CMOS substrate has, radioresistance little to environmental factor dependence, characteristic such as high temperature resistant, more strengthen the environmental suitability of spin transistor of the present invention, expanded its range of application.
Description of drawings
Figure 1A is formed at the core texture profile of spin transistor of the both sides of base layer respectively for a kind of emitter layer provided by the invention and collector layer;
Figure 1B is formed at the core texture profile of spin transistor of the same side of base layer for a kind of emitter layer provided by the invention and collector layer;
Fig. 2 A is the operation principle schematic diagram of spin transistor core texture shown in Figure 1A;
Fig. 2 B is the operation principle schematic diagram of spin transistor core texture shown in Figure 1B;
Fig. 3 is the equivalent circuit diagram of a kind of spin transistor functional unit provided by the invention;
Fig. 4 A be provided by the invention a kind of be implemented on the general substrate, emitter layer and collector layer be formed at the profile of no hollow out spin transistor device of the both sides of base layer respectively;
Fig. 4 B be provided by the invention a kind of be implemented on the general substrate, emitter layer and collector layer be formed at the profile of Openworks shape spin transistor device of the both sides of base layer respectively;
Fig. 5 A be provided by the invention a kind of be implemented on the general substrate, emitter layer and collector layer be formed at the profile of no hollow out spin transistor device of the same side of base layer;
Fig. 5 B be provided by the invention a kind of be implemented on the general substrate, emitter layer and collector layer be formed at the profile of Openworks shape spin transistor device of the same side of base layer;
Fig. 6 A be on a kind of SOI of being implemented in CMOS provided by the invention, emitter layer and collector layer be formed at the profile of no hollow out spin transistor device of the both sides of base layer respectively;
Fig. 6 B be on a kind of SOI of being implemented in CMOS provided by the invention, emitter layer and collector layer be formed at the profile of Openworks shape spin transistor device of the both sides of base layer respectively;
Fig. 7 A be on a kind of SOI of being implemented in CMOS provided by the invention, emitter layer and collector layer be formed at the profile of no hollow out spin transistor device of the same side of base layer;
Fig. 7 B be on a kind of SOICMOS of being implemented in provided by the invention, emitter layer and collector layer be formed at the profile of Openworks shape spin transistor device of the same side of base layer;
Wherein,
The 0----general substrate, the 11----emitter layer, the 2----base layer, the 12----collector layer,
31----first ferroelectric layer, 32----second ferroelectric layer, 41----emitter metal lead-in wire,
42----base metal lead-in wire, 43----collector electrode metal lead-in wire, 51----emitter pinning layer,
52----collector electrode pinning layer;
101----body silicon layer;
The 102----buried oxidation layer;
201----SOI CMOS source transistor polar region (N type);
202----SOI CMOS transistor gate area (P type);
203----SOI CMOS transistor drain district (N type; )
300----SOI CMOS transistor gate insulating medium layer;
401----SOI CMOS transistor source trace layer;
402----SOI CMOS transistor gate trace layer;
E represents emitter
B represents base stage
C represents collector electrode
Embodiment
Shown in Figure 1A and Figure 1B, it is the profile of spin transistor provided by the invention, this spin transistor is a multi-layer film structure, it comprises emitter layer 11, base layer 2 and collector layer 12, be formed on first ferroelectric layer 31 between described emitter layer 11 and the base layer 2, be formed on second ferroelectric layer 32 between described base layer 2 and the described collector layer 12, described emitter layer 11, base layer 2 and collector layer 12 adopt metallicity or semimetal material.According to spin transistor provided by the invention a variety of embodiments can be arranged, such as adopting dissimilar materials can make NPN type or positive-negative-positive spin transistor according to emitter layer 11, base layer 2 and collector layer 12; Emitter layer and the collector layer the same side that can be formed at base layer also can be formed at the both sides of base layer respectively for another example; According to the size of the stupid power of sedan-chair of emitter layer 11 and collector layer 12, can determine whether need on emitter layer 11 or collector layer 12, form pinning layer for another example; Can also take non-hollow out or hollow out to circularize formed spin transistor for some rete in the multilayer film for another example; Also such as for the formed basis of this multilayer film is substrate, this substrate can adopt general substrate such as semiconductor monocrystal wafer, also can adopt SOI COMOS substrate etc.These different embodiments will come no technique effect of correspondence or application scenarios the present invention is described in detail below by different embodiment, those skilled in the art should know that also content of the present invention is not limited to following these embodiment.
Embodiment 1
Shown in Fig. 4 A, a kind of spin transistor comprises a general substrate 0, and be integrated in emitter layer 11 on this substrate 0, base layer 2 and collector layer 12, be formed on first ferroelectric layer 31 between described emitter layer 11 and the base layer 2, be formed on second ferroelectric layer 32 between described base layer 2 and the described collector layer 12, emitter metal lead-in wire 41, base metal lead-in wire 42 and collector electrode metal lead-in wire 43, be formed at the emitter pinning layer 51 between substrate 0 and the emitter 11, be formed at the collector electrode pinning layer 52 between collector electrode 12 and the collector electrode metal lead-in wire 43.The emitter layer of present embodiment spin transistor and collector layer are formed at the both sides of base layer respectively.
This embodiment is the positive-negative-positive spin transistor of no pierced pattern, and its multi-layer film structure is at SrTiO
3The thickness that is deposited as successively on the substrate 0 is the emitter pinning layer IrMn of 20nm, and thickness is the emitter LaSrMnO of 50nm, the first ferroelectric layer ScTiO of thickness 20nm
3, thickness is the base stage Fe of 20nm, thickness is the second ferroelectric layer ScTiO of 20nm
3, thickness is the collector electrode LaSrMnO of 50nm, thickness is the collector electrode pinning layer IrMn of 20nm; Shown in Fig. 4 A, by depositing emitter metal lead-in wire 41, base metal lead-in wire 42 and collector electrode metal lead-in wire 43 after adopting known technology to the multi-layer film structure photoetching again; This spin transistor adopts insulation class material such as SiO
2Fill, to shield.
The chemical wet etching of this spin transistor multi-layer film structure is shaped as: observe from the top of Fig. 4 A, the emitter cross section is a rectangular configuration, and the long length of side is 1000nm, and minor face is long to be 500nm; The base stage cross section is a rectangular configuration, and the long length of side is 800nm, and minor face is long to be 500nm; The collector electrode cross section is an ellipsoidal structure, the long 400nm of major axis, the long 200nm of minor axis.
The material that general substrate 0 herein adopts is SrTiO
3Substrate, emitter metal lead-in wire 41, base metal lead-in wire 42, collector electrode metal lead-in wire 43 directly link to each other with emitter layer 11, base layer 2 and collector electrode 12.
It is identical with common PNP transistor amplifier working method, the principle of prior art at the spin signal amplifying function for spin transistor based on said structure provided by the invention, as Fig. 2 A and shown in Figure 3.Its particularity is, the amplified current of being exported is a spin polarized current, this spin transistor device provides the automatic overload protection function by current drives, promptly when breakdown current passes through base stage, since nano magnetic material exclusive current drives effect, in this layer originally with emitter, the parallel magnetic moment of collector electrode, because of no pinning effect can be inverted in emitter, the antiparallel state of collector electrode, thereby produce bigger resistance, and then reducing output current automatically, this moment, device was in automatic guard mode; After breakdown current disappears, can add certain magnetic field the base stage magnetic moment is placed and emitter, the parallel state of collector electrode, i.e. normal operating conditions again.
Shown in Fig. 4 B, the spin transistor of present embodiment is identical with embodiment 1 substantially on multi-layer film structure, and difference is that present embodiment adopts pierced pattern in membrane structure, specifically describes below:
The etching of this pierced pattern spin transistor multi-layer film structure is shaped as: the emitter cross section is a rectangular configuration, and the long length of side is 1000nm, and minor face is long to be 500nm; The base stage cross section is a rectangular configuration, the long length of side is 800nm, minor face is long to be 500nm, and contain oval engraved structure in rectangular configuration, this ellipse engraved structure extends through collector electrode pinning layer 52 from base layer 2, and the long 300nm of interior transverse that should the ellipse engraved structure forms, the long 200nm of interior ellipse short shaft; The cross section of collector electrode pinning layer, collector layer, second ferroelectric layer is the oval ring structure, can think to form outer ellipse, the long 400nm of outer transverse, the long 300nm of outer ellipse short shaft, inside and outside oval ring width 100nm accordingly with oval engraved structure.
Other is with embodiment 1.Its operation principle of spin transistor based on said structure provided by the invention is with described in the embodiment 1.
Present embodiment provides a kind of emitter layer and collector layer to be formed at the same side of base layer and does not have the positive-negative-positive spin transistor of pierced pattern.
Shown in Fig. 5 A, the multi-layer film structure of this spin transistor is at SrTiO
3Depositing the thickness that forms successively on the substrate 0 is the Fe base layer 2 of 20nm, the ScTiO of thickness 20nm
3Ferroelectric layer, thickness are the LaSrMnO layer of 50nm, and thickness is the IrMn pinning layer of 20nm; Through chemical wet etching, and plated metal lead-in wire back forms the ScTiO of thickness 20nm naturally
3First ferroelectric layer 31, thickness are the ScTiO of 20nm
3Second ferroelectric layer 31, thickness are the LaSrMnO emitter layer 11 of 50nm, and thickness is the LaSrMnO collector layer 12 of 50nm, and thickness is the IrMn emitter pinning layer 51 of 20nm, and thickness is the IrMn collector electrode pinning layer 52 of 20nm; Emitter metal lead-in wire 41, base metal lead-in wire 42 and collector electrode metal lead-in wire 43; This spin transistor adopts insulation class material such as SiO
2Filling shields.
Chemical wet etching is shaped as: the top is observed from Fig. 5 A, and the base layer cross section is a rectangular configuration, and the long length of side is 1000nm, and minor face is long to be 500nm; The emitter layer cross section is a rectangular configuration, and the long length of side is 300nm, and minor face is long to be 200nm; The collector layer cross section is a rectangular configuration, and the long length of side is 300nm, and minor face is long to be 200nm; Emitter layer 11 and collector layer 12 lay respectively at the relative two ends of base layer 2, form base metal lead-in wire 42 on the base layer between them.
Adopt SrTiO in the present embodiment
3Substrate, and emitter metal lead-in wire 41, base metal lead-in wire 42, collector electrode metal lead-in wire 43 directly link to each other with emitter layer, base layer and collector layer.
Its operation principle of spin transistor based on said structure provided by the invention is with described in the embodiment 1.
Embodiment 4
Present embodiment 4 provides a kind of emitter layer and collector layer to be formed at the same side of base layer and has the positive-negative-positive spin transistor of pierced pattern.Present embodiment and embodiment 3 is identical substantially, and difference is, has engraved structure in a side of collector layer, specifies as follows:
Shown in Fig. 5 B, this etching with spin transistor multi-layer film structure of pierced pattern is shaped as: the base layer cross section is a rectangular configuration, the long length of side is 1000nm, minor face is long to be 500nm, and has engraved structure, and this engraved structure upwards extends through collector electrode pinning layer 52 from base layer 2, this engraved structure is oval-shaped, can think interior ellipse, major axis length is 200nm in it, and interior minor axis is long to be 100nm; The cross section of first ferroelectric layer 31, emitter layer 11, emitter pinning layer 51 is a rectangular configuration, and the long length of side is 300nm, and minor face is long to be 200nm; The cross section of second ferroelectric layer 32, collector layer 12, collector electrode pinning layer 52 is oval engraved structure, and foreign minister's axial length is 300nm, and outer minor axis is long to be 200nm, and interior major axis is long to be 200nm, and interior minor axis length is 100nm, ring width 100nm.
Other is with embodiment 3.Its operation principle of spin transistor based on said structure provided by the invention is with described in the embodiment 1.
Embodiment 5
Present embodiment provides a kind of that form on SOI CMOS substrate, emitter layer and collector layer to be formed at the positive-negative-positive spin transistor of the both sides of base layer respectively.
As shown in Figure 6A, spin transistor comprises a SOI CMOS substrate, and be integrated in emitter layer 11 on this substrate, base layer 2 and collector layer 12, be formed on first ferroelectric layer 31 between described emitter layer 11 and the base layer 2, be formed on second ferroelectric layer 32 between described base layer 2 and the described collector layer 12, the emitter pinning layer 51 that is connected with described emitter layer, be formed at the collector electrode pinning layer 52 between collector electrode 12 and the collector electrode metal lead-in wire 43, be formed at the emitter metal lead-in wire 41 between emitter pinning layer 51 and the substrate, the base metal lead-in wire 42 that is connected with base layer, with the collector electrode metal lead-in wire 43 that is connected with the collector electrode pinning layer, and bit line 401 that is connected with substrate and word line 402.
The SOI CMOS substrate of present embodiment comprises: first semiconductor material layer 101, and such as the body silicon layer, and thereon the buried oxidation layer 102 and second semiconductor material layer of growth successively; This second semiconductor material layer is made of SOI CMOS transistor drain 203, grid 202 and source electrode 201, and SOI CMOS source transistor polar region is the N type herein, and gate regions is the P type, and the drain region is the N type; Be gate insulator dielectric layer 300 and grid lead layer 402 (being word line) successively on grid 202, source electrode trace layer 401 (being bit line) is arranged on source electrode 201.According to employed environment difference, can select polytype SOI CMOS substrates such as complete depletion type, double grid type, high temperature resistance type, anti-impulse type, anti-high-pressure type for use;
The multi-layer film structure of this spin transistor on SOI CMOS drain electrode 203 (be emitter metal lead-in wire 41) successively deposit thickness be the IrMn emitter pinning layer 51 of 20nm, thickness is the LaSrMnO emitter 11 of 50nm, the ScTiO of thickness 20nm
3First ferroelectric layer 31, thickness are the Fe base stage 2 of 20nm, and thickness is the ScTiO of 20nm
3Second ferroelectric layer 32, thickness are the LaSrMnO collector layer 12 of 50nm, and thickness is the IrMn collector electrode pinning layer 52 of 20nm; Photoetching forms as shown in Figure 6A, and figure also deposits base metal lead-in wire 42 and the collector electrode metal lead-in wire 43 that forms simultaneously; This spin transistor adopts insulation class material such as SiO
2Filling shields.
The etching of the multi-layer film structure of this spin transistor is shaped as: the top is observed from Fig. 6 A, and the emitter layer cross section is a rectangular configuration, and the long length of side is 1000nm, and minor face is long to be 500nm; The base layer cross section is a rectangular configuration, and the long length of side is 800nm, and minor face is long to be 500nm; The collector electrode cross section is an ellipsoidal structure, the long 400nm of major axis, the long 200nm of minor axis.The shape of other layer is to form naturally after the lithography process.
It is identical in spin signal amplifying function and common PNP transistor amplifier working method, principle for spin transistor based on said structure provided by the invention, as Fig. 2 A and shown in Figure 3.Its particularity is that described structure can utilize the word line of SOI CMOS and bit line to select corresponding spin transistor to apply the spin signal of telecommunication in the spin transistor array; The amplified current of being exported is a spin polarized current; Described spin transistor device provides the automatic overload protection function by current drives, promptly when breakdown current passes through base stage, since nano magnetic material exclusive current drives effect, in this layer originally with emitter, the parallel magnetic moment of collector electrode, because of no pinning effect can be inverted in emitter, the antiparallel state of collector electrode, thereby produce bigger resistance, and then reduce output current automatically, this moment, device was in automatic guard mode; After breakdown current disappears, can add certain magnetic field the base stage magnetic moment is placed and emitter, the parallel state of collector electrode, i.e. normal operating conditions again.
Embodiment 6
Present embodiment provides a kind of that form on SOI CMOS substrate, emitter layer and collector layer to be formed at both sides and the positive-negative-positive spin transistor have hollow out mechanism in multilayer film of base layer respectively.Present embodiment is identical substantially with embodiment 5, and difference is to have engraved structure in the multilayer film, specifically describes as follows:
The etching of the spin transistor of this engraved structure is shaped as: observe from the top of device shown in Fig. 6 b, the emitter layer cross section is a rectangular configuration, and the long length of side is 1000nm, and minor face is long to be 500nm; The base layer cross section is a rectangular configuration, and the long length of side is 800nm, and minor face is long to be 500nm; The collector layer cross section is the inner elliptical annular structure that oval engraved structure is arranged, this ellipse engraved structure upwards extends through collector electrode pinning layer 52 inside from described base layer 2, foreign minister's axial length 400nm of elliptical annular structure, the long 200nm of outer minor axis, the long 300nm of interior major axis, the long 100nm of interior minor axis, ring width 100nm.
Other is with embodiment 5.Its operation principle of spin transistor based on said structure provided by the invention is with described in the embodiment 5.
Embodiment 7
Present embodiment provides a kind of that form on SOI CMOS substrate, emitter layer and collector layer to be formed at the positive-negative-positive spin transistor of the same side of base layer.
Shown in Fig. 7 A, spin transistor comprises a SOI CMOS substrate, and lead-in wire 42 of the base metal on this substrate and base layer 2, first ferroelectric layer 31, emitter layer 11, emitter pinning layer 51 and emitter metal lead-in wire 41 are arranged on an end of base layer 2 successively, second ferroelectric layer 32, collector layer 12, collector electrode pinning layer 52 and collector electrode metal lead-in wire 43 are arranged on the other end of base layer 2 successively, on this SOI CMOS substrate, also be formed with bit line 401 and word line 402.
The SOI CMOS substrate of present embodiment comprises: first semiconductor material layer 101, and such as the body silicon layer, and thereon the buried oxidation layer 102 and second semiconductor material layer of growth successively; This second semiconductor material layer is made of SOICMOS transistor drain 203, grid 202 and source electrode 201, and SOI CMOS source transistor polar region is the N type herein, and gate regions is the P type, and the drain region is the N type; Be gate insulator dielectric layer 300 and grid lead layer 402 (being word line) successively on grid 202, source electrode trace layer 401 (being bit line) is arranged on source electrode 201.According to employed environment difference, can select polytype SOI CMOS substrates such as complete depletion type, double grid type, high temperature resistance type, anti-impulse type, anti-high-pressure type for use.
The multi-layer film structure of this positive-negative-positive spin transistor is that the thickness that is deposited as successively on SOI CMOS drain electrode (being base metal lead-in wire 42) is the Fe base layer 2 of 20nm, the ScTiO of thickness 20nm
3Ferroelectric layer, thickness are the LaSrMnO of 50nm, and thickness is the IrMn pinning layer of 20nm; Through etching, and plated metal lead-in wire back forms the ScTiO of thickness 20nm naturally
3First ferroelectric layer 31, thickness are the ScTiO of 20nm
3Second ferroelectric layer 32, thickness are the LaSrMnO emitter layer 11 of 50nm, and thickness is the LaSrMnO collector layer 12 of 50nm, and thickness is the IrMn emitter pinning layer 51 of 20nm, and thickness is the IrMn collector electrode pinning layer 52 of 20nm; Emitter metal lead-in wire 41 and collector electrode metal lead-in wire 43; This spin transistor adopts insulation class material such as SiO
2Filling shields.
The etching of this spin transistor multi-layer film structure is shaped as: from device shown in Fig. 7 A the top observe, the base layer cross section is a rectangular configuration, the long length of side is 1000nm, minor face is long to be 500nm; The emitter cross section is a rectangular configuration, and the long length of side is 300nm, and minor face is long to be 200nm; The collector electrode cross section is a rectangular configuration, and the long length of side is 300nm, and minor face is long to be 200nm.
Its operation principle of spin transistor based on said structure provided by the invention is with described in the embodiment 5.
Embodiment 8
Present embodiment provides the same side that a kind of that form, emitter layer and collector layer be formed at base layer on SOI CMOS substrate, and multilayer film has the positive-negative-positive spin transistor of engraved structure.Present embodiment is identical substantially with embodiment 7, and difference is to have engraved structure in the multi-layer film structure in the present embodiment, specifically describes as follows:
This etching with spin transistor of engraved structure is shaped as: observe from the top of device shown in Fig. 7 B, the base layer cross section is a rectangle, and the long length of side is 1000nm, and minor face is long to be 500nm; The cross section of the first iron electrode layer 31, emitter layer 11, emitter pinning layer 51 and emitter metal lead-in wire 41 is a rectangular configuration, and the long length of side is 300nm, and minor face is long to be 200nm; The collector layer cross section is the elliptical annular structure with oval engraved structure, foreign minister's axial length 300nm, the long 200nm of outer minor axis, the long 200nm of interior major axis, the long 100nm of interior minor axis, ring width 100nm, and should upwards extend through in the collector layer 12 from base layer 2 by the ellipse engraved structure.
Its operation principle of spin transistor based on said structure provided by the invention is with described in the embodiment 5.
Be that spin transistor with positive-negative-positive is that example is introduced content of the present invention in detail above, if make the spin transistor of NPN type, then can not change based on the multi-layer film structure of the various embodiments described above device, and change corresponding film material, such as in embodiment 1, emitter layer and collector layer being adopted metal Fe material, base layer adopts LaSrMnO, just can make the NPN type spin transistor of same structure, in other embodiments too, this is that those skilled in the art accomplish easily, does not repeat them here.
Though described some embodiments of the present invention here, ability should be realized that in the technical staff, and other possible changes of the present invention and distortion are not broken away from the more summary of the invention of broad range and the scope of claims.
Claims (16)
1. a spin transistor comprises emitter layer, base layer and collector layer; It is characterized in that, also comprise: be formed on first ferroelectric layer between described emitter layer and the described base layer, be used to regulate the size of the space charge region between described emitter layer and the described base layer, be formed on second ferroelectric layer between described base layer and the described collector layer, be used to regulate the size of the space charge region between described base layer and the described collector layer, described emitter layer, described base layer and described collector layer adopt metallicity or semimetal material; Wherein, the material of described emitter layer is cavity type magnetic metal or semimetal material, and thickness is 5nm to 1000nm; The material of described base layer is an electron type magnetic metal material, and thickness is 3nm to 100nm; The material of described collector electrode is cavity type magnetic metal or semimetal material, and thickness is 5nm to 1000nm; The material of described first ferroelectric layer, second ferroelectric layer is the ferroelectricity insulating material, and thickness is 5nm to 100nm.
2. spin transistor according to claim 1 is characterized in that, described emitter layer and described collector layer are formed at the both sides of described base layer respectively.
3. spin transistor according to claim 1 is characterized in that, described emitter layer and described collector layer are formed at the same side of described base layer.
4. spin transistor according to claim 1, it is characterized in that, also comprise the emitter pinning layer and the collector electrode pinning layer that are respectively formed on described emitter layer, the described collector layer, the material of described pinning layer is antiferromagnetic materials, and layer thickness is 10nm to 100nm.
5. spin transistor according to claim 1 is characterized in that, the cross section of described emitter layer, base layer and collector layer is rectangle, ellipse or regular hexagon; Perhaps, described base layer and collector layer have the cross section of engraved structure, and the cross section of described engraved structure is straight-flanked ring, elliptical ring or regular hexagon ring; Or the cross section of described engraved structure is rectangle, ellipse or the regular hexagon that comprises rectangle hollow out, oval hollow out or regular hexagon hollow out.
6. spin transistor according to claim 5 is characterized in that, the minor face of ring is 10nm to 100000nm in the described straight-flanked ring, and the minor face of outer shroud is 20nm to 200000nm, and the ratio on minor face and long limit is 1: 1 to 1: 5, and ring width is 10nm to 100000nm;
The minor axis of ring is 10nm to 100000nm in the described elliptical ring, and the minor axis of outer shroud is 20nm to 200000nm, and the ratio of minor axis and major axis is 1: 1 to 1: 5, and ring width is 10nm to nm 100000nm;
The length of side of ring is 10nm to 100000nm in the described regular hexagon ring, and the length of side of outer shroud is 20nm to 200000nm, and ring width is 10nm to 100000nm;
The minor face of described rectangle is 10nm to 100000nm, and the ratio on minor face and long limit is 1: 1 to 1: 5;
Described oval-shaped minor axis is 10nm to 100000nm, and the ratio of minor axis and major axis is 1: 1 to 1: 5, and described ellipse comprises circle;
The described orthohexagonal length of side is 10nm to 100000nm.
7. according to the described spin transistor of claim 1, it is characterized in that described spin transistor forms on substrate, described substrate is the semiconductor monocrystal wafer.
8. according to the described spin transistor of claim 1, it is characterized in that described spin transistor forms on substrate, described substrate is a SOI CMOS substrate.
9. a spin transistor is characterized in that, comprises emitter layer, base layer and collector layer; It is characterized in that, also comprise: be formed on first ferroelectric layer between described emitter layer and the described base layer, be used to regulate the size of the space charge region between described emitter layer and the described base layer, be formed on second ferroelectric layer between described base layer and the described collector layer, be used to regulate the size of the space charge region between described base layer and the described collector layer, described emitter layer, described base layer and described collector layer adopt metallicity or semimetal material; Wherein, the composition material of described emitter layer is an electron type magnetic metal material, and thickness is 3nm to 100nm; The material of described base layer is cavity type magnetic metal or semimetal material, and thickness is 5nm to 1000nm; The material of described collector layer is an electron type magnetic metal material, and thickness is 5nm to 1000nm; The composition material of described first ferroelectric layer, second ferroelectric layer is the ferroelectricity insulating material, and thickness is 5nm to 1000nm.
10. spin transistor according to claim 9 is characterized in that, described emitter layer and described collector layer are formed at the both sides of described base layer respectively.
11. spin transistor according to claim 9 is characterized in that, described emitter layer and described collector layer are formed at the same side of described base layer.
12. spin transistor according to claim 9, it is characterized in that, also comprise the emitter pinning layer and the collector electrode pinning layer that are respectively formed on described emitter layer, the described collector layer, the material of described pinning layer is antiferromagnetic materials, and layer thickness is 10nm to 100nm.
13. spin transistor according to claim 9 is characterized in that, the cross section of described emitter layer, base layer and collector layer is rectangle, ellipse or regular hexagon; Perhaps, described base layer and collector layer have the cross section of engraved structure, and the cross section of described engraved structure is straight-flanked ring, elliptical ring or regular hexagon ring; Or the cross section of described engraved structure is rectangle, ellipse or the regular hexagon that comprises rectangle hollow out, oval hollow out or regular hexagon hollow out.
14. spin transistor according to claim 13 is characterized in that, the minor face of ring is 10nm to 100000nm in the described straight-flanked ring, and the minor face of outer shroud is 20nm to 200000nm, and the ratio on minor face and long limit is 1: 1 to 1: 5, and ring width is 10nm to 100000nm;
The minor axis of ring is 10nm to 100000nm in the described elliptical ring, and the minor axis of outer shroud is 20nm to 200000nm, and the ratio of minor axis and major axis is 1: 1 to 1: 5, and ring width is 10nm to nm 100000nm;
The length of side of ring is 10nm to 100000nm in the described regular hexagon ring, and the length of side of outer shroud is 20nm to 200000nm, and ring width is 10nm to 100000nm;
The minor face of described rectangle is 10nm to 100000nm, and the ratio on minor face and long limit is 1: 1 to 1: 5;
Described oval-shaped minor axis is 10nm to 100000nm, and the ratio of minor axis and major axis is 1: 1 to 1: 5, and described ellipse comprises circle;
The described orthohexagonal length of side is 10nm to 100000nm.
15., it is characterized in that described spin transistor forms on substrate according to the described spin transistor of claim 9, described substrate is the semiconductor monocrystal wafer.
16., it is characterized in that described spin transistor forms on substrate according to the described spin transistor of claim 9, described substrate is a SOI CMOS substrate.
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| KR101598542B1 (en) * | 2009-01-13 | 2016-02-29 | 삼성전자주식회사 | Logic circuit device using spin field effect transistor |
| CN103515426A (en) * | 2012-06-20 | 2014-01-15 | 中国科学院物理研究所 | Spin transistor based on multiferroic or ferroelectric material |
| CN103022343B (en) * | 2012-11-27 | 2015-05-13 | 复旦大学 | Self-spinning rectifying apparatus for enhancing surface plasma antenna coupling |
| CN105449097B (en) * | 2015-11-27 | 2018-07-17 | 中国科学院物理研究所 | Double magnetism potential barrier tunnel knots and the spintronics devices including it |
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| CN1376312A (en) * | 1999-09-30 | 2002-10-23 | 因芬尼昂技术股份公司 | Ferroelectric transistor and use thereof in a memory cell arrangement |
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