CN101322230B - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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CN101322230B
CN101322230B CN2006800457415A CN200680045741A CN101322230B CN 101322230 B CN101322230 B CN 101322230B CN 2006800457415 A CN2006800457415 A CN 2006800457415A CN 200680045741 A CN200680045741 A CN 200680045741A CN 101322230 B CN101322230 B CN 101322230B
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photoresist pattern
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CN101322230A (zh
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白寅福
李诚宰
梁钟宪
安昌根
刘汉泳
林基主
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Electronics and Telecommunications Research Institute ETRI
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Abstract

提供一种通过光刻工艺改变光致抗蚀剂的性质以形成虚拟结构并且将该结构应用于栅电极形成工艺的半导体器件制造方法。该方法包括步骤：在半导体衬底的顶部上形成缓冲层；在缓冲层上应用无机光致抗蚀剂，并通过光刻工艺形成光致抗蚀剂图案；用预定气体来热处理光致抗蚀剂图案；在热处理后的结构上均匀沉积绝缘层，并将所沉积的层蚀刻所沉积的厚度以露出热处理后的光致抗蚀剂图案；在蚀刻后的结构上沉积绝缘层，并且蚀刻所沉积的绝缘层以露出热处理后的光致抗蚀剂图案；使用蚀刻工艺去除所露出的光致抗蚀剂图案；在光致抗蚀剂图案被去除的部分形成栅极氧化层；以及在栅极氧化层上形成栅电极。因此，在形成用于制造纳米尺寸器件的结构中，通过光刻工艺形成的层的限制通过热处理得到改善，且因此用于制造各种器件的结构可以容易形成。

Description

半导体器件制造方法
技术领域
本发明涉及一种半导体器件制造方法，更准确地说涉及一种通过光刻工艺改变光致抗蚀剂的性质来形成虚拟结构且然后将该虚拟结构用于形成栅电极的工艺的半导体器件制造方法。
背景技术
美国专利公开No.6,033,963揭示了一种使用虚拟结构的传统的半导体器件制造方法。
图1A和1B说明了根据传统工艺的半导体器件制造方法中去除虚拟结构之前和之后的工艺。
参考图1A，通过准备具备隔离层2的硅衬底1，在硅衬底1上形成虚拟栅极氧化层3A，在虚拟栅极氧化层3A上形成虚拟栅电极3B，在虚拟栅极的侧壁上形成间隔物(spacer)4，通过将杂质注入硅衬底1的表面形成源极区和漏极区5，形成选择性钨层6，以及形成绝缘层7，由此形成该结构。在这里，虚拟栅极氧化层3A和虚拟栅电极3B用做虚拟结构3。
参考图1B，虚拟结构3从图1A所示结构中去除之后，孔洞8形成，然后金属栅电极形成于孔洞8中。
然而，这种虚拟结构形成方法工艺复杂，该工艺沉积了两种材料，并且通过上述方法形成的虚拟结构没有被完全去除。
发明内容
技术问题
本发明涉及一种使用虚拟结构的半导体器件制造方法，其中，通过使用预定气体对使用光致抗蚀剂通过光刻工艺形成的图案进行热处理而形成具有改善性能的图案，且使用该图案形成虚拟结构。
技术解决方案
本发明的一个方面是提供一种半导体器件制造方法，包括以下步骤：在半导体衬底的顶部上形成缓冲层；在缓冲层上应用无机光致抗蚀剂，并且使用光刻工艺形成光致抗蚀剂图案；用预定气体来热处理光致抗蚀剂图案；在热处理后的结构上均匀沉积绝缘层，并且将所沉积的层蚀刻所沉积的厚度以便露出热处理的光致抗蚀剂图案；在蚀刻后的结构上沉积绝缘层，并且蚀刻所沉积的绝缘层以露出热处理的光致抗蚀剂图案；使用蚀刻工艺去除所露出的光致抗蚀剂图案；在光致抗蚀剂图案被去除的部分形成栅极氧化层；以及在栅极氧化层上形成栅电极。
该方法进一步包括修整(trimming)光致抗蚀剂图案以减少光致抗蚀剂图案的线宽的步骤，并且修整步骤可以通过使用CF4或CHF3气体的干法蚀刻或者使用氢氟酸(HF)的湿法蚀刻来进行。
该预定气体可以是O2气体。
该热处理可以通过快速热退火(RTA)来进行或者在熔炉中进行。
有利效果
如上所述根据本发明，传统的虚拟结构形成工艺可以被简化，因此与传统图案化工艺相比可以容易地形成微小图案。因此，通过使用无机光致抗蚀剂的虚拟结构形成方法，可以制造包括纳米尺寸器件的不同类型器件，而且由于简化的工艺而可以降低生产成本。
附图说明
图1A和1B为示出了传统的半导体器件制造方法的截面图；
图2A至2N为示出了根据本发明示例性实施例的半导体器件制造方法的截面图；
图3为示出了根据本发明制造的器件的截面图，其中侧栅极(side gate)形成于栅电极的两侧；
图4为示出了根据本发明制造的器件的截面图，其中典型的硅衬底作为半导体衬底；
图5为示出了根据本发明制造的单电子器件的截面图；
图6为示出了根据本发明制造的器件的基本结构的扫描电子显微镜(SEM)照片；以及
图7为示出了使用本发明的光致抗蚀剂修整工艺的结果的SEM照片。
上述附图中主要符号的说明：
10：半导体衬底
12：第一单晶硅层
14：掩埋绝缘层
16：第二单晶硅层
18：源极区和漏极区
20：缓冲层
30：光致抗蚀剂
32：经光刻工艺的光致抗蚀剂
34：经修整工艺的光致抗蚀剂
36：经热处理工艺的光致抗蚀剂
40、42、50：绝缘层
44：侧壁间隔物
60：栅极氧化层
70：栅电极
72、74：金属线
具体实施方式
在下文中，将详细描述本发明的示例性实施例。然而，本发明不限于下述示例性实施方案，而是可以实施为不同类型。因此，这些示例性实施例被提供用于完整公开本发明，并且将本发明的范围充分传达给本领域技术人员。
图2A至2N为示出了根据本发明的半导体器件制造方法的截面图。
参考图2A，示出了绝缘体上硅(SOI)衬底10，该衬底为将应用本发明的半导体衬底。
SOI衬底10包括在第一单晶硅层12上形成的掩埋绝缘层14，和在绝缘层14上形成的第二单晶硅层16。SOI衬底具有掩埋在衬底表面和下层之间的薄绝缘层，这可以减少寄生电容并改善器件性能。除了SOI衬底10，普通硅衬底或化合物衬底例如GaAs衬底也可以用作该半导体衬底。
参考图2B，缓冲层20形成于SOI衬底10的顶部。
缓冲层20用于防止由后续工艺的光致抗蚀剂修整工艺或离子注入工艺引起的衬底损伤，且该缓冲层20可以依据工艺而去除。
参考图2C，无机光致抗蚀剂30施加于缓冲层20的顶部。
无机光致抗蚀剂30可以是负或正光致抗蚀剂。当负光致抗蚀剂曝光时，曝光部分没有被去除，而未曝光部分在显影时被去除。反之，正光致抗蚀剂曝光时，曝光部分在显影时被去除。
光致抗蚀剂使用无机光致抗蚀剂材料，例如氢硅倍半氧化物(hydrogensilsesquioxane，HSQ)。这是因为有机光致抗蚀剂在高温工艺中可能损坏。
参考图2D，通过对光致抗蚀剂30进行光刻工艺形成光致抗蚀剂图案32。
通过使用光束、电子束或离子束能够形成图案的设备来进行光刻工艺。值得注意的是现有光刻工艺可以形成的图案的最小线宽约为60nm。
参考图2E，通过修整工艺以减小光致抗蚀剂图案32的线宽，形成光致抗蚀剂图案34。
修整工艺用于实现比现有光刻工艺更小的线宽。修整工艺不是本发明的关键要素，而且可以据步骤而省略。
光致抗蚀剂的修整工艺一般通过使用稀释氢氟酸(HF)的湿法蚀刻来实行。在这种情况下，取决于缓冲层20的材料，缓冲层20可以无损耗地被蚀刻。在图2E中，缓冲层20的一部分在修整工艺中被蚀刻掉。
另一方面，使用CF4或CHF3气体的干法蚀刻工艺可以在将光致抗蚀剂图案32缩小到纳米尺寸的工艺中用来防止光致抗蚀剂图案32坍塌(collapse)，而且与湿法蚀刻相比可以更准确地控制线宽。
根据本发明，修整工艺施加到光致抗蚀剂图案，这样容易控制线宽而且容易实现小于传统虚拟结构的线宽。将参考图7详细描述该结果。
参考图2F，示出了光致抗蚀剂图案36，该光致抗蚀剂图案的性能通过使用预定气体热处理修整过的光致抗蚀剂图案34而得到改变。
热处理可以通过快速热退火(RTA)工艺或通过熔炉来进行，O2或N2气体可以用作该预定气体。如果RTA工艺使用另一种气体代替O2，虽然光致抗蚀剂图案的截面轮廓没有大幅变形，但是图案线宽增加。如果熔炉工艺使用另一种气体代替O2，光致抗蚀剂图案的截面轮廓大幅变形。
由于光致抗蚀剂图案36被热处理，性质变得更硬，而且如此可以防止光致抗蚀剂图案36在高温下进行的后续工艺中变形或坍塌。
参考图2G，在热处理过的结构上沉积均匀厚度的绝缘层40。
在后续工艺中，绝缘层40用作侧壁间隔物。除了绝缘层40，可以沉积导电层来形成侧电极。图3示出了通过沉积导电层形成的结构。
参考图2H，所沉积的层被蚀刻所沉积的厚度，以便露出热处理过的光致抗蚀剂图案36。
也可以通过蚀刻工艺露出缓冲层20。
参考图2I，通过缓冲层20注入杂质离子以在图2H中的第二单晶硅层16中形成源极区和漏极区。
例如硼(B)，镓(Ga)或铟(In)的受主离子被注入用于p型掺杂，或者例如锑(Sb)，砷(As)，磷(P)或铋(Bi)的杂质被注入用于n型掺杂。通过注入杂质离子形成源极区和漏极区18。
参考图2J，绝缘层50沉积在图2I的结构上。
绝缘层50可以由氮化硅、旋涂玻璃(SOG)或HSQ形成。在HSQ用作无机光致抗蚀剂30的情况下，当绝缘层50由HSQ形成时，绝缘层50可以和光致抗蚀剂图案36一起被蚀刻，光致抗蚀剂36将在后续工艺中被去除。因此，在沉积绝缘层时应该考虑光致抗蚀剂的材料。
参考图2K，图2J中的绝缘层50被蚀刻，以露出热处理过的光致抗蚀剂图案36。
可以通过化学机械抛光(CMP)工艺蚀刻绝缘层50，从而形成侧壁间隔物44。
侧壁间隔物44用作相对于栅电极层的侧壁的绝缘层，并在用于形成接触孔的蚀刻工艺中用作栅电极层的蚀刻阻挡层，其中该栅电极层将形成于热处理后的光致抗蚀剂图案36在后续工艺中被去除而留下的部分。
参考图2L，在图2K中露出的热处理后的光致抗蚀剂图案36被蚀刻而去除。
蚀刻工艺可以是湿法或干法蚀刻工艺。这里，位于热处理后的光致抗蚀剂图案36下的缓冲层20也可被去除。
参考图2M，在光致抗蚀剂图案36被去除的部分形成栅极氧化层60。
栅极氧化层60形成为使将在后续工艺中形成的栅电极与该半导体衬底10及侧壁间隔物44分离，并且也形成在绝缘层50上。可以通过沉积或生长来形成栅极氧化层60。
参考图2N，该图为通过本发明的半导体器件制造方法形成的器件的最终截面图，在去除光致抗蚀剂图案36后形成的栅极氧化层60的部分形成栅极金属层70。
为了在形成金属层70的同时形成源极区域和漏极区域上的金属线，形成接触孔，并且金属线通过接触孔连接到源极区域和漏极区域。
因此，不同于传统的虚拟结构形成方法，在根据本发明的半导体器件制造方法中，仅使用光致抗蚀剂图案来形成虚拟结构。由于与传统虚拟结构相比，通过修整工艺容易控制光致抗蚀剂图案的线宽，因此在需要微小线宽的纳米尺寸器件的制作工艺中应执行修整工艺。同时，由于光致抗蚀剂图案在高温工艺中会变形，因此需要通过使用预定气体进行热处理来改变光致抗蚀剂图案的性质。
图3至5是根据本发明的半导体器件制造方法所制作器件的截面图。
参考图3，侧栅极46形成于栅电极70的两侧。
总之，图2A到2N的工艺被使用，但侧电极46是通过沉积导电层来形成，而不是如图2G的步骤中用于形成侧壁间隔物的绝缘层40。
参考图4，在该工艺中使用普通硅衬底10，代替图2A到2N的工艺中使用的SOI衬底。并且，与图2A到2N的工艺相比，首先形成栅极氧化层60于硅衬底10上，形成源电极区域和漏电极区域18，且形成光致抗蚀剂图案于栅极氧化层60上用作虚拟结构。形成虚拟结构之后，绝缘层50被沉积，且在去除虚拟结构之后，形成栅电极70、金属线72和74，这与图2A到2N中一样。
参考图5，根据本发明的半导体器件制造方法应用于单电子器件的制造工艺。侧栅极46形成在光致抗蚀剂图案36的两侧，量子点根据侧栅极46形成的场而形成在光致抗蚀剂图案36下的衬底上，且最上面的栅电极70控制单电子器件的运行。
图6是扫描电子显微镜(SEM)照片，示出根据本发明的半导体器件制造方法所制造的基本结构。参考图6，线宽为20nm以下的光致抗蚀剂图案36使用HSQ来形成，该HSQ是对光束或电子束反应的高分辨无机电子束光致抗蚀剂。层的性质通过使用O2气体的RTA来改善，多晶硅在650℃的高温下沉积，且侧栅极46通过干法蚀刻在图案两侧形成为具有11nm的线宽。
实验结果显示，当使用本发明的光致抗蚀剂通过虚拟结构制造半导体器件时，可以制造线宽为20nm以下的栅电极和线宽为11nm的侧栅极。
图7是SEM照片，示出在本发明的半导体器件制造工艺中使用的光致抗蚀剂图案的修整工艺的结果。参考图7，示出通过使用CF4气体的干法蚀刻，可再现地将图案的线宽从21nm(初始线宽)(a)减小到5nm(e)。这里，修整速率被优化在4nm/min，且相应线宽分别是(a)21nm，(b)17nm，(c)13nm，(d)9nm和(e)5nm。
实验结果显示，通过应用修整工艺可以形成具有约5nm的微小线宽的虚拟结构，并且因此值得注意的是，根据本发明的半导体器件制造方法对于制作纳米尺寸器件是实用的技术。这是因为，与传统虚拟结构相比，光致抗蚀剂图案更容易修整。
尽管参照本发明的特定实施方式对本发明进行了上述图示和描述，但本领域技术人员应当理解，在不脱离由所附权利要求书所限定的本发明的精神和范围的情况下，可以对本发明进行形式和细节上的各种修改。

Claims (9)

1.一种半导体器件制造方法，包括以下步骤：
在半导体衬底的顶部上形成缓冲层；
在所述缓冲层上应用无机光致抗蚀剂，并且使用光刻工艺形成光致抗蚀剂图案；
用预定气体来热处理所述光致抗蚀剂图案；
在热处理后的结构上均匀沉积第一绝缘层，并且将所沉积的第一绝缘层蚀刻所沉积的厚度以便露出热处理后的光致抗蚀剂图案，从而形成侧壁间隔物；
在蚀刻后的结构上沉积第二绝缘层，并且蚀刻所沉积的第二绝缘层以露出热处理后的光致抗蚀剂图案且在所述侧壁间隔物的侧壁上保留部分所述第二绝缘层；
使用蚀刻工艺去除所露出的光致抗蚀剂图案；
在所述光致抗蚀剂图案被去除的部分形成栅极氧化层；以及
在所述栅极氧化层上形成栅电极。
2.如权利要求1所述的方法，其中所述半导体衬底是绝缘体上硅衬底或者化合物衬底。
3.如权利要求1所述的方法，其中用光刻工艺形成图案的步骤使用光束、电子束或者离子束。
4.如权利要求1所述的方法，进一步包括以下步骤：
修整所述光致抗蚀剂图案以减小所述光致抗蚀剂图案的线宽。
5.如权利要求4所述的方法，其中所述修整步骤是通过使用CF4或CHF3气体的干法蚀刻工艺来进行，或通过使用氢氟酸的湿法蚀刻工艺来进行。
6.如权利要求1所述的半导体器件制造方法，其中所述预定气体是O2气体。
7.如权利要求1所述的半导体器件制造方法，其中所述热处理是通过快速热退火工艺来进行或者在熔炉中进行。
8.如权利要求1所述的半导体器件制造方法，其中所述光致抗蚀剂图案通过所述热处理被硬化。
9.如权利要求1所述的半导体器件制造方法，其中蚀刻所露出的光致抗蚀剂图案的步骤包括如下步骤：通过蚀刻将热处理的光致抗蚀剂图案下的缓冲层一起去除。
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