CN101329852B - Common voltage drive circuit of LCD - Google Patents
Common voltage drive circuit of LCD Download PDFInfo
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- CN101329852B CN101329852B CN2008101271325A CN200810127132A CN101329852B CN 101329852 B CN101329852 B CN 101329852B CN 2008101271325 A CN2008101271325 A CN 2008101271325A CN 200810127132 A CN200810127132 A CN 200810127132A CN 101329852 B CN101329852 B CN 101329852B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
- G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
Abstract
The present invention relates to a common voltage driving circuit of a liquid crystal display, which includes: a clock signal output unit that comprises first to sixth transistors and outputs first and second clock signals input from external system according to the control of any one gate output voltage of first to third gate output voltages; an output node voltage controller that comprises seventh to thirteenth transistors and a first to a fourth condensers and changes voltages of positive and negative polarity output nodes by the first and second clock signals and first to third gate output voltages; an initialization voltage supply unit that comprises fourteenth to twentieth transistors and supplies an initialization voltage of the output node voltage controller; and a common voltage output unit that comprises twenty-second to twenty-third transistors and a fifth condenser and prevents the voltages of the positive and negative polarity output nodes from being changed by using the fifth condenser in alternately outputting higher and lower common voltages according to the voltages of the positive and negative polarity output nodes.
Description
Technical field
The present invention relates to a kind of device, relate in particular to a kind of common voltage drive circuit that can prevent the LCD of common electric voltage drift (float) in the liquid crystal panel to LCD (LCD) supply common electric voltage.
Background technology
Along with the development of infotech (IT), the demand of flat-panel display device is increased sharply.LCD is a kind of traditional flat-panel display device.
LCD is a kind of display device, shows required image thereby its image information offers the pixel of arranging with matrix form respectively with the transmittance of controlling pixel.For this reason, LCD comprises liquid crystal panel and drives the drive IC (integrated circuit) (driver) of liquid crystal panel, wherein, is used for being arranged in liquid crystal panel as the pixel of the minimum unit of realizing image with matrix form.In addition, because LCD self is not luminous, LCD comprises the back light unit that light is provided.
Usually, if liquid crystal panel comprises common voltage drive circuit (drive IC), then by this common voltage drive circuit, the common electric voltage of positive polarity or negative polarity is applied on the liquid crystal panel.In this case, because the stray capacitance or the leakage current that occur near driving circuit or the peripheral circuit, the common electric voltage of required level (predetermined level) can not stably provide.
For example, when the common electric voltage of negative polarity was applied to liquid crystal panel by common voltage drive circuit, the voltage of output node (Q node) did not maintain predetermined original levels, but the existence owing to stray capacitance or leakage current gradually changes shown in Fig. 1.
In other words, positive polarity and negative polarity output node (Q node, Q node) are kept " low " level alternating voltage, but can't maintain that predetermined original levels (Q node ideally or Q node ideally) goes up but raise gradually.
This has caused the utility voltage sags phenomenon, produces defective screen picture as shown in Figure 2.
Therefore, the LCD with correlation technique of common voltage drive circuit can not suitably be handled the variation of the common electric voltage of lower or higher level, has caused deterioration of image.
Summary of the invention
Therefore, in order to handle the problems referred to above various features as described below have been proposed here.An aspect of illustrative examples is when common electric voltage is applied on the liquid crystal panel by common voltage drive circuit, prevents that higher or lower common electric voltage from changing owing to stray capacitance or leakage current.
Illustrative examples be the variation that prevents common electric voltage by the capacitor that uses minimum capacity on the other hand.
The invention provides a kind of common voltage drive circuit of LCD, comprise: the clock signal output unit, form and according to first to the 3rd grid output voltage V GOUT1 to M6 by first to the 6th transistor M1, VGOUT2, the control of at least one grid output voltage output is by the first clock signal VCLK1 and the second clock signal VCLK2 of external system input among the VGOUT3; The output node voltage controller, comprise the 7th to the 13 transistor and first to the 4th capacitor, and by the first clock signal VCLK1 and the second clock signal VCLK2 and first to the 3rd grid output voltage V GOUT1, VGOUT2, VGOUT3 changes the voltage of positive polarity output node Q node and negative polarity output node Q node; The initialization voltage feeding unit comprises that the 14 to the 21 transistor M14 provides initialization voltage to M21 and to the output node voltage controller; And common electric voltage output unit, comprise the 22 and the 23 transistor M22, M23 and the 5th capacitor C5, and when according to higher common electric voltage of the alternating voltage of positive polarity output node and negative polarity output node output and lower common electric voltage, prevent the change in voltage of positive polarity output node Q node and negative polarity output node Q node by described the 5th capacitor C5.
With reference to the accompanying drawings with following detailed description of the present invention, aforementioned and other purpose, feature and advantage of the present invention will be more obvious.
Description of drawings
Fig. 1 is the oscillogram of the output node voltage of correlation technique;
Fig. 2 shows in the correlation technique because the synoptic diagram of the defective screen picture of utility voltage sags phenomenon;
Fig. 3 is the circuit diagram according to the common voltage drive circuit of LCD of the present invention (LCD);
Fig. 4 a shows among Fig. 3 each several part at the waveform of first frame; And
Fig. 4 b shows among Fig. 3 each several part at the waveform of second frame.
Embodiment
With reference now to accompanying drawing, describes illustrative examples of the present invention in detail.
Fig. 3 is the circuit diagram according to the common voltage drive circuit of LCD of the present invention (LCD).
As shown in Figure 3, common voltage drive circuit comprises: clock signal input block 31 comprises first to the 6th MOS transistor M1 to M6, and imports first and second clock signal VCLK1 and the VCLK2 according to the grid output voltage; Output node voltage controller 32, comprise the 7th to the 13 MOS transistor M7 to M13 and first to the 4th capacitor C1 to C4, and by the first and second clock signal VCLK1 and VCLK2 and first to the 3rd grid output voltage V GOUT1 voltage to VGOUT3 change positive polarity output node (Q node) and negative polarity output node (Q node); Initialization voltage feeding unit 33 comprises the 14 to the 21 MOS transistor M14 to M21, and the initialization voltage of output node voltage controller 32 is provided; And common electric voltage output unit 34, comprise the 22 and the 23 MOS transistor M22 and M23 and the 5th capacitor C5, and by using voltage that the 5th capacitor C5 prevents positive polarity output node (Q node) and negative polarity output node (Q node) to change, thereby according to higher common electric voltage VCOMH of the alternating voltage ground output of positive polarity output node (Q node) and negative polarity output node (Q node) or lower common electric voltage VCOML from their original levels.
In clock signal input block 31, the end of second clock signal VCLK2 sequentially is connected to positive polarity output node (Q node) via (or by) the diode-type first and second MOS transistor M1, M2 and the 3rd MOS transistor M3, and the end of the first clock signal VCLK1 sequentially is connected to negative polarity output node (Q node) via diode-type the 4th and the 5th MOS transistor M4, M5 and the 6th MOS transistor M6.Equally, the end of the second grid output voltage V GOUT2 is connected to the grid of the 3rd and the 6th MOS transistor M3, M6 simultaneously.
Here, import terminal and the diode-type first and second MOS transistor M1 between the positive polarity output node (Q node) and M2 and the 3rd MOS transistor M3 that second clock signal VCLK2 is arranged about being connected in series in, input has the terminal of second clock signal VCLK2 to be connected to the drain electrode of the diode-type first MOS transistor M1, the source electrode of the first MOS transistor M1 is connected to the drain electrode of the second MOS transistor M2, and the source electrode of the diode-type second MOS transistor M2 is connected to the drain electrode of the 3rd MOS transistor M3.The source electrode of the 3rd MOS transistor M3 is connected to positive polarity output node (Q-node).The grid of diode-type first and second MOS transistor M1 and M2 is connected to the terminal that input has second clock signal VCLK2.
Import terminal and the diode-type the 4th between the negative polarity output node Q node and the 5th MOS transistor M4 and M5 and the 6th MOS transistor M6 that the first clock signal VCLK1 is arranged about being connected, input has the terminal of the first clock clock signal VCLK1 to be connected to the drain electrode of the 4th MOS transistor M4, the source electrode of the 4th MOS transistor M4 is connected to the drain electrode of diode-type the 5th MOS transistor M5, and the source electrode of diode-type the 5th MOS transistor M5 is connected to the drain electrode of the 6th MOS transistor M6.The source electrode of the 6th MOS transistor M6 is connected to negative polarity output node (Q node).In addition, the grid of diode-type the 4th and the 5th MOS transistor M4 and M5 is connected to the terminal that input has the first clock signal VCLK1.
In output node voltage controller 32, a plurality of first to the 4th capacitor C1 are connected in series between positive polarity output node (Q node) and the negative polarity output node (Q node) to C4, and at a plurality of first to the 4th capacitor C1 in C4, connected node N1 and power voltage terminal VSS in the middle of first points of common connection (or node) of the first and second capacitor C1 and C2 is connected to via the tenth and the 12 MOS transistor M10 and M12 respectively, connected node N1 is the common connection node of the second and the 3rd capacitor C2 and C3 wherein, and on power voltage terminal VSS by external electric be applied with voltage.This first intermediate connection point N1 is electrically connected to second points of common connection between the third and fourth capacitor C3, the C4 via the 11 and the 13 MOS transistor M11, M13 usually.
In addition, first grid output voltage V GOUT1 jointly is connected to the 12 and the grid of the 13 MOS transistor M12-M13, wherein the 12 is one another in series with the 13 MOS transistor M12-M13 and is connected.Input has the end of the second grid output voltage V GOUT2 to be connected to the tenth and the grid of the 11 MOS transistor M10-M11, wherein the tenth is one another in series with the 11 MOS transistor M10-M11 and is connected.Input is electrically connected to first common connection node between the first and second capacitor C1 and the C2 and second common connection node between the third and fourth capacitor C3, the C4 by the 8th and the 9th MOS transistor M8, M9 by the end of the 3rd grid output voltage V GOUT3 respectively after via diode-type the 7th MOS transistor M7.
About the tenth and the 11 MOS transistor M10 and M11 and the 12 and the 13 MOS transistor M12 and the M13 between second points of common connection of first points of common connection that is connected in series in the first and second capacitor C1 and C2 and the third and fourth capacitor C3 and C4, the source electrode of the tenth and the 12 MOS transistor M10 and M12 is connected to first points of common connection, and the source electrode of the 11 and the 13 MOS transistor M11 and M13 is connected to second points of common connection.The tenth is connected to each other together having the terminal of the second grid output voltage V GOUT2 to be connected with input with the grid of the 11 MOS transistor M10 and M11, and the tenth is connected to each other together to be connected with connected node N1 in the middle of first with the drain electrode of the 11 MOS transistor M10 and M11.In addition, the 12 is connected to each other together having the terminal of first grid output voltage V GOUT1 to be connected with input with the grid of the 13 MOS transistor M12 and M13, and the 12 is connected to each other together to be connected with connected node N1 in the middle of first with the drain electrode of the 13 MOS transistor M12 and M13.
The drain and gate of diode-type the 7th MOS transistor M7 jointly is connected to the terminal that input has the 3rd grid output voltage V GOUT3, and the source electrode of diode-type the 7th MOS transistor M7 jointly is connected to the drain electrode of the 8th and the 9th MOS transistor M8 and M9.The source electrode of the 8th MOS transistor M8 is connected to first points of common connection, and the source electrode of the 9th MOS transistor M9 is connected to second points of common connection.The grid of the 8th MOS transistor M8 is connected to positive polarity output node (Q-node), and the grid of the 9th MOS transistor M9 is connected to negative polarity output node (Q node).
In initialization voltage feeding unit 33, input has the end of first grid output voltage V GOUT1 jointly to be connected to the 14 to the 17 MOS transistor M14 each grid to M17.Equally, power voltage terminal VSS jointly is connected to connected node N2 in the middle of second, and ten five and ten seven MOS transistor M15 and the source electrode of M17 of the 14 to the 17 MOS transistor M14 in the M17 is connected to this connected node N2 in the middle of second jointly.This second middle connected node N2 is connected to positive polarity output node (Q node) via the 14 and the 15 MOS transistor M14, M15, also is connected to negative polarity output node (Q node) via the 16 and the 17 MOS transistor M16, M17.In addition, the second middle connected node N2 is connected to negative polarity output node (Q node) via the 18 and the 19 MOS transistor M18, M19, and is connected to positive polarity output node (Q node) via the 20 and the 21 MOS transistor M20, M21.Described positive polarity output node (Q node) is connected to the grid of the 18 and the 19 MOS transistor M18, M19 and the grid that negative polarity output node (Q node) is connected to the 20 and the 21 MOS transistor M20, M21.
In other words, between positive polarity output node (Q-node) and negative polarity output node (Q node), the 14 is one another in series with M19 with the 19 MOS transistor M18 with the 15 MOS transistor M14 and M15 and the 18 is connected, and the 16 is one another in series with M21 with the 21 MOS transistor M20 with the 17 MOS transistor M16 and M17 and the 20 and is connected.
In this case, the 14 to the 17 MOS transistor M14 jointly is connected to the terminal that input has first grid output voltage V GOUT1 to the grid of M17, the grid of the 18 and the 19 MOS transistor M18 and M19 and the drain electrode of the 14 MOS transistor M14 are connected to positive polarity output node (Q-node), and the drain electrode of the grid of the 20 and the 21 MOS transistor M20 and M21 and the 16 MOS transistor M16 is connected to negative polarity output node (Q-node).Be connected with points of common connection between the drain electrode of the source electrode of points of common connection between the drain electrode of the source electrode of the 15 MOS transistor M15 and the 18 MOS transistor M18 and the 17 MOS transistor M17 and the 20 MOS transistor M20 second in the middle of connected node N2 be connected with power voltage terminal VSS.
In common electric voltage output unit 34, positive polarity output node (Q node) and negative polarity output node (Q node) are connected to the grid of the 22 and the 23 MOS transistor M22 and M23.The 5th capacitor C5 is connected between the grid of the 22 and the 23 MOS transistor M22 and M23, and input has the end of lower common electric voltage VCOML and higher common electric voltage VCOMH jointly to be connected to common electric voltage output terminal VCOMOUT via the 22 and the 23 MOS transistor M22, M23 respectively.
That is, positive polarity output node (Q node) is connected to the grid of the 22 MOS transistor M22, and negative polarity output node (Q node) is connected to the grid of the 23 MOS transistor M23.In this case, the 5th capacitor C5 is connected between the grid of the grid of the 22 MOS transistor M22 and the 23 MOS transistor M23.In addition, input has the end of high common electric voltage VCOMH to be connected with the source electrode of the 22 MOS transistor M22, and input has the end of low common electric voltage VCOML to be connected with the source electrode of the 23 MOS transistor M23.The drain electrode of the 22 and the 23 MOS transistor M22 and M23 is connected to each other to form the output terminal of common electric voltage.
With reference now to Fig. 4 a and 4b, describe the principle of work of the present invention of structure as mentioned above in detail.
In the original state of first frame, the terminal voltage VSS of 10V is transferred to first to the 4th capacitor C1 that is connected in series to the first intermediate connection point N1 of C4.Connected node N1 jointly is connected to the points of common connection between the drain electrode of the tenth and the 11 MOS transistor M10 and M11 and is connected to points of common connection between the drain electrode of the 12 and the 13 MOS transistor M12 and M13 in the middle of first.
Under this state, shown in (a) among Fig. 4 a, at first frame, (8V) input, therefore, the 12 to the 17 MOS transistor M12 is to the M17 conducting with low level for first grid output voltage V GOUT1.Then, the two ends of the second capacitor C2 connect by the 12 MOS transistor M12, and the two ends of the 3rd capacitor C3 connect by the 13 MOS transistor M13.
Like this, terminal voltage VSS is transferred to the end of the positive polarity output node (Q node) and the first capacitor C1 jointly by the 14 and the 15 MOS transistor M14, M15.In addition, terminal voltage VSS is transferred to the other end of negative polarity output node (Q node) and the 4th capacitor C4 usually by the 16 and the 17 MOS transistor M16 and M17.
Therefore, (when 8V) importing, first to the 4th capacitor C1 that is connected in series is initialized as 10V to each intermediate connection point and two output nodes (Q node) (Q node) of C4 with low level as first grid output voltage V GOUT1 in first frame.
Subsequently, shown in (b) among Fig. 4 a, when the second grid output voltage V GOUT2 with low level (8V) when input, the 3rd MOS transistor M3 conducting.Therefore, shown in (f) among Fig. 4 a-the second clock signal VCLK2 of 8V order is transferred to positive polarity output node Q node via the diode-type first and second MOS transistor M1 and M2 and the 3rd MOS transistor M3.
Next, from positive polarity output node output shown in (h) Fig. 4 a-voltage transmission of 8V is to the grid of the 22 MOS transistor M22 of output terminal, thereby make the 22 MOS transistor M22 conducting.
At this moment, the 6th MOS transistor M6 is also by the second grid output voltage V GOUT2 conducting of-8V, and because the first clock signal VCLK1 is 10V, the 4th and the 5th MOS transistor M4 and not conducting of M5, therefore the voltage level of negative polarity output node Q node maintains 10V, shown in (i) among Fig. 4 a.
Subsequently, shown in (c) among Fig. 4 a, the 3rd grid output voltage V GOUT3 (8V) imports, and is transferred to the points of common connection of the first and second capacitor C1, C2 via diode-type the 7th MOS transistor M7 and the 8th MOS transistor M8 with low level.Therefore, the voltage of the points of common connection of the first and second capacitor C1, C2 is converted into-8V from 10V.So the voltage of positive polarity output node Q node is converted into-26V from-8V by bootstrapping (bootstrapping), shown in (h) among Fig. 4 a.
The 22 MOS transistor M22 is by the output voltage (26V) conducting fully from positive polarity output node (Q node) output.
Here, the 22 MOS transistor M22 by the complete conducting of Bootstrap from-8V to-26V carries out stable transition and drives (transition driving).That is, because the variation of transition causes noise phenomenon to occur fast, so stable pulse can not offer liquid crystal panel.
Therefore, the higher common electric voltage VCOMH shown in (d) stably outputs to common electric voltage output terminal VCOMOUT by the 22 MOS transistor M22 among Fig. 4 a.That is, higher common electric voltage VCOMH exports from common electric voltage output terminal VCOMOUT.Here, higher common electric voltage VCOMH can be, for example, and 5V.
Like this, when higher common electric voltage VCOMH exported by said process, usually, positive polarity output node Q voltages at nodes can't maintain predetermined original levels, but shown in Fig. 1 since around stray capacitance or leakage current and increase gradually.
Yet, among the present invention, because be connected the existence of the capacitor (C5) between positive polarity output node Q node and the negative polarity output node Q node, positive polarity output node Q voltages at nodes is not subjected to stray capacitance or influence of leakage current on every side, so this voltage does not increase gradually.Therefore, this higher common electric voltage VCOMH can export with stable form, shown in Fig. 4 a.
When beginning second frame after first frame, (8V) input shown in (a) among Fig. 4 b, thereby makes the 12 to the 17 MOS transistor M12 to the M17 conducting to first grid output voltage V GOUT1 with low level.Thereafter, the two ends of the second capacitor C2 connect by the 12 MOS transistor M12, and the two ends of the 3rd capacitor C3 connect by the 13 MOS transistor M13.
At this moment, the terminal voltage VSS of 10V jointly is transferred to the end of the positive polarity output node Q node and the first capacitor C1 through the 14 and the 15 MOS transistor M14 and M15.Equally, terminal voltage VSS jointly is transferred to the other end of negative polarity output node Q node and the 4th capacitor C4 via the 17 and the 16 MOS transistor M17 and M16.
Therefore, at second frame, when first grid output voltage V GOUT1 with low level (8V) when input, the voltage that positive polarity output node (Q node) is located is converted to 10V from-26V, shown in (h) among Fig. 4 b, the voltage that negative polarity output node (Q node) is located is from equally maintaining 10V with first frame.
Thereafter, shown in (b) among Fig. 4 b, the second grid output voltage V GOUT2 (8V) imports, thereby makes the 3rd MOS transistor M3 conducting with low level.Then, shown in (f) among Fig. 4 b, the second clock signal VCLK2 of 10V order is transferred to positive polarity output node Q node by the diode-type first and second MOS transistor M1 and M2 and the 3rd MOS transistor M3.Like this, be applied to positive polarity output node Q node by said process because electromotive force is the voltage of 10V, the electromotive force at positive polarity output node Q node place does not change, shown in (h) among Fig. 4 b.
At this moment, the 6th MOS transistor M6 is by the second grid output voltage V GOUT2 conducting of-8V.Therefore, shown in (g) among Fig. 4 b, the first clock signal VCLK1 of-8V is transferred to negative polarity output node Q node by diode-type the 4th and the 5th MOS transistor M4 and M5 and the 6th MOS transistor M6.Therefore, the electromotive force of negative polarity output node Q node is converted to-8V from 10V, shown in (i) among Fig. 4 b.
At last, from negative polarity output node Q node output-voltage transmission of 8V is to the grid of the 23 MOS transistor M23 of common electric voltage output unit 34, thereby make the 23 MOS transistor M23 begin conducting.
Afterwards, (8V) input shown in (c) among Fig. 4 b, is transferred to the points of common connection of the third and fourth capacitor C3 and C4 to the 3rd grid output voltage V GOUT3 then by diode-type the 7th MOS transistor M7 and the 9th MOS transistor M9 with low level.Therefore, the voltage at the points of common connection place of the third and fourth capacitor C3, C4 is converted to-8V from 10V.And then, negative polarity output node Q voltages at nodes since bootstrapping be converted to-26V from-8V, shown in (i) among Fig. 4 b.
The 23 MOS transistor M23 by from negative polarity output node Q node output-the complete conducting of output voltage of 26V.
Here, the 23 MOS transistor M23 by the complete conducting of Bootstrap from-8V to-26V carries out stable transition and drives (transition driving).That is, because the variation of transition causes noise phenomenon to occur fast, so stable pulse can not offer liquid crystal panel.
Therefore, shown in (e) among Fig. 4 b, lower common electric voltage VCOML stably outputs to common electric voltage output terminal VCOMOUT by the 23 MOS transistor M23.That is, the lower common electric voltage VCOML of this 0 level exports from common electric voltage output terminal VCOMOUT.Here, for example, lower common electric voltage VCOML can be 0V.
Like this, when exporting lower common electric voltage VCOML by said process, usually, negative polarity output node Q voltages at nodes can't maintain predetermined original levels, but shown in Fig. 1, owing to the existence of stray capacitance and leakage current on every side increases gradually.
Yet in the present invention, owing to be connected the existence of the capacitor (C5) between positive and negative polarity output node Q node and the Q node, negative polarity output node Q voltages at nodes is not subjected to stray capacitance or influence of leakage current on every side, and therefore, this voltage does not increase gradually.
Therefore, this lower common electric voltage VCOML can be with stable form output, shown in Fig. 4 b.
Equally, if the 5th capacitor C5 in the omission common electric voltage output unit 34, the present invention can replace the effect of the 5th capacitor C5 by first to the 4th capacitor C1 in the increase output node voltage controller 32 to the electric capacity of C4.
Yet, like this, because first to the 4th capacitor C1 increases the electric capacity of the 5th capacitor C5 to the electric capacity of C4, so compare with the situation of using the 5th capacitor C5, the total capacitance value of capacitor doubles, and therefore, does not have effect (ineffective).
In addition, because first to the 4th capacitor C1 of output node voltage controller 32 has accounted for the entire circuit area to C4 about 30%, the first to the 4th capacitor C1 needs more installation space to the increase of the electric capacity of C4.
Experimental result shows, when the electric capacity of the 5th capacitor C5 surpasses 0.1pF, can stably keep the original levels of the voltage of positive polarity output node Q node and negative polarity output node Q node.
As previously shown, among the present invention, via the common voltage drive circuit of LCD during to liquid crystal panel supply common electric voltage, capacitor is installed in output terminal and changes because of stray capacitance or leakage current to prevent common electric voltage.Therefore, stably drive liquid crystal panel, thereby prevent deterioration of image.
Equally, it is more effective than capacitor is installed in the output node voltage controller at the common electric voltage output unit capacitor to be installed, thereby utilizes the capacitor of little electric capacity to stablize common electric voltage.
The present invention can implement with various forms in the scope that does not depart from its feature, should understand any details that the foregoing description is not limited to aforementioned description except as otherwise noted, and should be considered as in the claims restricted portion structure widely, and therefore claims are intended to cover all and fall into all variants and modifications in the claims spirit and scope or the equivalent of these spirit and scope.
Claims (14)
1. the common voltage drive circuit of a LCD comprises:
The clock signal output unit, comprise first to the 6th transistor (M1 is to M6) and according to first to the 3rd grid output voltage (VGOUT1, VGOUT2, VGOUT3) in the control output of at least one grid output voltage by first clock signal (VCLK1) and the second clock signal (VCLK2) of external system input;
The output node voltage controller, comprise the 7th to the 13 transistor (M7-M13) and first to the 4th capacitor (C1-C4), and by first clock signal (VCLK1) and the second clock signal (VCLK2) and first to the 3rd grid output voltage (VGOUT1, VGOUT2, VGOUT3) change positive polarity output node (Q node) and negative polarity output node (
Node) voltage;
The initialization voltage feeding unit comprises the 14 to the 21 transistor (M14-M21) and provides initialization voltage to the output node voltage controller; And
The common electric voltage output unit, comprise the 22 and the 23 transistor (M22, M23) and the 5th capacitor (C5), the 5th capacitor (C5) be connected positive polarity output node (Q node) and negative polarity output node (
Node) between, and when according to positive polarity output node (Q node) and negative polarity output node (
When common electric voltage that the output of node) alternating voltage is higher and lower common electric voltage by described the 5th capacitor (C5) prevent positive polarity output node (Q node) and negative polarity output node (
Node) change in voltage,
Wherein, in the clock signal output unit, end by the second clock signal (VCLK2) of outside input jointly is connected to the diode-type first and second MOS transistor (M1, the drain electrode of grid M2) and diode-type first MOS transistor (M1), the drain electrode of the source electrode of diode-type first MOS transistor (M1) and diode-type second MOS transistor (M2) is connected to each other and is in the same place, the drain electrode of the source electrode of diode-type second MOS transistor (M2) and the 3rd MOS transistor (M3) is connected to each other and is in the same place, end by first clock signal (VCLK1) of outside input jointly is connected to diode-type the 4th and the 5th MOS transistor (M4, the drain electrode of grid M5) and diode-type the 4th MOS transistor (M4), the drain electrode of the source electrode of diode-type the 4th MOS transistor (M4) and diode-type the 5th MOS transistor (M5) is connected to each other, the drain electrode of the source electrode of diode-type the 5th MOS transistor (M5) and the 6th MOS transistor (M6) is connected to each other and is in the same place, end from the second grid output voltage (VGOUT2) of outside jointly is connected to the 3rd and the 6th MOS transistor (M3, M6) grid, the source electrode of the 3rd MOS transistor (M3) is connected to positive polarity output node (Q node), and the source electrode of the 6th MOS transistor (M6) be connected to the negative polarity output node (
Node),
Wherein, in the output node voltage controller, first to the 4th capacitor C1 to C4 be connected in series in positive polarity output node (Q node) and negative polarity output node (
Node) between, first and second capacitor (the C1, C2) points of common connection is connected to the 8th, the the tenth and the 12 MOS transistor (M8, M10, M12) source electrode, third and fourth capacitor (the C3, C4) points of common connection is connected to the 9th, the the 11 and the 13 MOS transistor (M9, M11, M13) source electrode, the second and the 3rd capacitor (C2, C3) connected node (N1) jointly is connected to the drain electrode and the power voltage terminal (VSS) of the tenth to the 13 MOS transistor (M10-M13) in the middle of first between, the end of first grid output voltage (VGOUT1) jointly is connected to the 12 and the 13 MOS transistor (M12, M13) grid, the end of the second grid output voltage (VGOUT2) jointly is connected to the tenth and the 11 MOS transistor (M10, M11) grid, the end of the 3rd grid output voltage (VGOUT3) jointly is connected to the grid and the drain electrode of diode-type the 7th MOS transistor (M7), the the 8th and the 9th MOS transistor (M8, the source electrode of drain electrode M9) and diode-type the 7th MOS transistor (M7) is connected to each other, the grid of the 8th MOS transistor (M8) is connected to positive polarity output node (Q node), the grid of the 9th MOS transistor (M9) be connected to the negative polarity output node (
Node),
Wherein, in described initialization voltage feeding unit, jointly be connected to the grid of the 14 to the 17 MOS transistor (M14 is to M17) by the end of the first grid output voltage (VGOUT1) of outside input, positive polarity output node (Q node) is connected to drain electrode, the 18 and the 19 MOS transistor (M18 of the 14 MOS transistor (M14), the source electrode of grid M19) and the 21 MOS transistor (M21), the negative polarity output node (
Node) is connected to the drain electrode of the 16 MOS transistor (M16), the the 20 and the 21 MOS transistor (M20, the source electrode of grid M21) and the 19 MOS transistor (M19), connected node (N2) in the middle of power voltage terminal (VSS) is connected to second, wherein the second middle connected node (N2) jointly is connected to the 15 and the 17 MOS transistor (M15, M17) source electrode and the 18 and the 20 MOS transistor (M18, M20) drain electrode, the source electrode of the 14 MOS transistor (M14) is connected to each other with the drain electrode of the 15 MOS transistor (M15) and is in the same place, the source electrode of the 16 MOS transistor (M16) is connected to each other with the drain electrode of the 17 MOS transistor (M17) and is in the same place, the source electrode of the 18 MOS transistor (M18) is connected to each other with the drain electrode of the 19 MOS transistor (M19) and is in the same place, and the source electrode of the 20 MOS transistor (M20) is connected to each other with the drain electrode of the 21 MOS transistor (M21) and is in the same place
Wherein, in described common electric voltage output unit, positive polarity output node (Q node) is connected to the grid of the 22 MOS transistor (M22), the negative polarity output node (
Node) is connected to the grid of the 23 MOS transistor (M23), the 5th capacitor (C5) is connected the 22 and the 23 MOS transistor (M22, M23) between the grid, the end of higher common electric voltage (VCOMH) is connected to the source electrode of the 22 MOS transistor (M22), the end of lower common electric voltage (VCOML) is connected to the source electrode of the 23 MOS transistor (M23), and (M22, drain electrode M23) jointly is connected to common electric voltage output terminal (VCOMOUT) to the 22 and the 23 MOS transistor.
2. driving circuit according to claim 1 is characterized in that, described the first to the 23 transistor is a MOS transistor.
3. driving circuit according to claim 1 is characterized in that, (VCLK1 VCLK2) has phases opposite to described first and second clock signals.
4. driving circuit according to claim 1 is characterized in that, (VCLK1, " low " level VCLK2) are-8V that (VCLK1, " height " level VCLK2) is 10V to described first and second clock signals to described first and second clock signals.
5. driving circuit according to claim 1 is characterized in that, (VGOUT1, VGOUT2 VGOUT3) sequentially are transformed into low level from high level at every predetermined period of time to described first to the 3rd grid output voltage.
6. driving circuit according to claim 1 is characterized in that, described first to the 3rd grid output voltage (VGOUT1, VGOUT2, VGOUT3) be maintained 10V or-8V.
7. driving circuit according to claim 1 is characterized in that, described positive and negative polarity output node (the Q node,
Node) with first to the 3rd grid output voltage (VGOUT1, VGOUT2, VGOUT3) synchronously with 10V ,-8V and-order of 26V changes successively.
8. driving circuit according to claim 1 is characterized in that, described higher common electric voltage (VCOMH) is 5V.
9. driving circuit according to claim 1 is characterized in that, described lower common electric voltage (VCOML) is 0V.
10. driving circuit according to claim 1, it is characterized in that, when higher common electric voltage (VCOMH) was exported by the 22 MOS transistor (M22), described the 5th capacitor (C5) prevented that the gate voltage of the 22 MOS transistor (M22) from changing.
11. driving circuit according to claim 1, it is characterized in that, when lower common electric voltage (VCOML) was exported by the 23 MOS transistor (M23), described the 5th capacitor (C5) prevented that the gate voltage of the 23 MOS transistor (M23) from changing.
12. driving circuit according to claim 1 is characterized in that, the described 22 and the 23 MOS transistor (M22, M23) by positive and negative polarity output node (the Q node,
Node) alternating voltage conducting.
13. driving circuit according to claim 1 is characterized in that, described the 5th capacitor (C5) has 0.1pF or bigger electric capacity.
14. driving circuit according to claim 1 is characterized in that, described LCD comprises the liquid crystal panel that common voltage drive circuit is installed in it.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070060705 | 2007-06-20 | ||
| KR10-2007-0060705 | 2007-06-20 | ||
| KR20070060705 | 2007-06-20 | ||
| KR1020080035339A KR101349780B1 (en) | 2007-06-20 | 2008-04-16 | Common voltage generation circuit of liquid crystal display |
| KR10-2008-0035339 | 2008-04-16 | ||
| KR1020080035339 | 2008-04-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101329852A CN101329852A (en) | 2008-12-24 |
| CN101329852B true CN101329852B (en) | 2011-05-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101271325A Active CN101329852B (en) | 2007-06-20 | 2008-06-19 | Common voltage drive circuit of LCD |
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| KR (1) | KR101349780B1 (en) |
| CN (1) | CN101329852B (en) |
Families Citing this family (5)
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| KR101773576B1 (en) | 2010-10-22 | 2017-09-13 | 삼성디스플레이 주식회사 | Liquid crystal display and driving method thereof |
| TWI443626B (en) * | 2012-04-12 | 2014-07-01 | Au Optronics Corp | Common voltage supply circuit of display |
| US9224324B2 (en) * | 2014-01-03 | 2015-12-29 | Pixtronix, Inc. | Cascode driver circuit |
| KR102567324B1 (en) * | 2017-08-30 | 2023-08-16 | 엘지디스플레이 주식회사 | Gate driver and display device including the same |
| TWI663587B (en) * | 2018-05-24 | 2019-06-21 | 友達光電股份有限公司 | Common voltage generating circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5774099A (en) * | 1995-04-25 | 1998-06-30 | Hitachi, Ltd. | Liquid crystal device with wide viewing angle characteristics |
| CN1637835A (en) * | 2003-12-30 | 2005-07-13 | Lg.菲利浦Lcd株式会社 | Circuit for driving common voltage of in-plane switching mode liquid crystal display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4743570B2 (en) * | 2001-04-10 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit with built-in power supply circuit, liquid crystal display control device, and portable electronic device |
| US6900672B2 (en) | 2003-03-28 | 2005-05-31 | Stmicroelectronics, Inc. | Driver circuit having a slew rate control system with improved linear ramp generator including ground |
| JP4858250B2 (en) | 2004-03-04 | 2012-01-18 | セイコーエプソン株式会社 | Common voltage generation circuit, power supply circuit, display driver, and common voltage generation method |
| KR100699829B1 (en) * | 2004-12-09 | 2007-03-27 | 삼성전자주식회사 | Output buffer of source driver in liquid crystal display device having high slew rate and method for controlling the output buffer |
-
2008
- 2008-04-16 KR KR1020080035339A patent/KR101349780B1/en active IP Right Grant
- 2008-06-19 CN CN2008101271325A patent/CN101329852B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5774099A (en) * | 1995-04-25 | 1998-06-30 | Hitachi, Ltd. | Liquid crystal device with wide viewing angle characteristics |
| CN1637835A (en) * | 2003-12-30 | 2005-07-13 | Lg.菲利浦Lcd株式会社 | Circuit for driving common voltage of in-plane switching mode liquid crystal display device |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平8-313867A 1996.11.29 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20080112095A (en) | 2008-12-24 |
| KR101349780B1 (en) | 2014-01-15 |
| CN101329852A (en) | 2008-12-24 |
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