CN101351885A - 快闪存储器卡上的测试垫 - Google Patents

快闪存储器卡上的测试垫 Download PDF

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Publication number
CN101351885A
CN101351885A CNA2006800499456A CN200680049945A CN101351885A CN 101351885 A CN101351885 A CN 101351885A CN A2006800499456 A CNA2006800499456 A CN A2006800499456A CN 200680049945 A CN200680049945 A CN 200680049945A CN 101351885 A CN101351885 A CN 101351885A
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semiconductor packages
semiconductor die
semiconductor
joint sheet
scolder
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CN101351885B (zh
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赫姆·塔基阿尔
什里卡尔·巴加特
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SanDisk Technologies LLC
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SanDisk Corp
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Abstract

本发明揭示一种半导体封装，其包含由在制造期间贴附到所述半导体封装的焊料凸块形成的测试垫。当囊封所述封装时，由于在所述囊封工艺期间施加于所述封装上的压力，所述焊料凸块的若干部分变得平坦从而大体上与所述半导体封装的表面齐平且暴露于所述表面上。所述焊料凸块的这些暴露部分形成测试垫，可通过所述测试垫测试成品封装。

Description

快闪存储器卡上的测试垫
技术领域
本发明的实施例涉及一种包含具有测试垫的集成电路封装的快闪存储器卡。
背景技术
随着电子装置的大小持续减小，操作电子装置的相关联半导体封装正设计成更小的形式因数、更低的功率需要及更高的功能。目前，半导体制造中的次微米特征对封装技术提出了更高需求，包含更高的引线数、减少的引线间距、最小的焊盘面积及明显总体积减少。
半导体封装的一个分支涉及引线框架的使用，引线框架是其上安装及支撑一个或一个以上半导体电路小片的薄金属层。引线框架包含用于将电信号从一个或一个以上半导体传送到印刷电路板或其它外部电装置的电引线。图1显示在附接半导体电路小片22之前的引线框架20。典型的引线框架20可包含一定数目的引线24，所述引线24具有用于附接到半导体电路小片22的第一末端24a，及用于贴附到印刷电路板或其它电组件的第二末端(未显示)。引线框架20可进一步包含电路小片附接垫26，其用于以结构方式将半导体电路小片22支撑在引线框架20上。尽管电路小片附接垫26可提供到接地的路径，但传统上其不将信号携载到半导体电路小片22或从半导体电路小片22携载信号。在某些引线框架配置中，已知省略了电路小片附接垫26，而是改为以所谓的引线上芯片(COL)配置将半导体电路小片直接附接到引线框架的引线。
如图2中所示，可使用电路小片附接化合物将半导体引线24安装到电路小片附接垫26。传统上，半导体电路小片22经形成而在半导体电路小片的顶部侧上的至少第一及第二相对边缘上具有多个电路小片接合垫28形成。一旦将半导体电路小片安装到引线框架，便执行线接合工艺，借此使用专用导线30将接合垫28电耦合到相应电引线24。接合垫28到特定电引线24的指派是由工业标准规格界定的。图2为清晰起见而并未显示用导线连接到引线24的所有接合垫28，但是在常规设计中可用导线将每一接合垫连接到其相应的电引线。如图2中所示，也已知并非所有的接合垫都导线连接到电引线。
通常，引线框架20最初是由包含多个此类引线框架的面板形成的。半导体电路小片22安装且电连接到面板中的每一引线框架，且将由此形成的集成电路囊封于模制化合物中。此后，从面板切割个别囊封的集成电路，或将其单个化成多个半导体封装。
已知在半导体封装内形成测试垫。测试垫通常暴露到封装外部且内部电连接到封装中的一个或一个以上半导体电路小片。在制造半导体封装之后，可将所述封装插入到测试卡上的插座中，在其上通过探针来接触所述测试垫以测试半导体封装的电特性及功能，以确定成品半导体封装是否执行每一规格。
通常，在衬底制造步骤期间，在引线框架或其它衬底(例如，印刷电路板)中形成用于测试垫的图案。所述图案可例如在化学蚀刻或机械冲压工艺中形成。在形成后，测试垫在形成所述封装的模制囊封步骤期间保持暴露，以允许在封装形成后接近所述测试垫。一旦制造且经由测试垫测试了封装，便可将封装包封于覆盖测试垫的一对配对盖中，且防止在使用半导体封装时接近测试垫。
发明内容
已略述的本发明涉及一种半导体封装，其包含由在制造期间贴附到所述半导体封装的焊料凸块形成的测试垫。可在引线框架上形成半导体封装。可在已知制造工艺中(例如，化学蚀刻)或在使用级进模(progressive die)的机械冲压工艺中在面板上批次处理多个引线框架。
在所述封装制造工艺期间，将一个或一个以上半导体电路小片安装到且电连接到所述引线框架以形成集成电路。此后，将集成电路囊封于模制化合物中。在囊封后，可通过从所述引线框架面板将所述集成电路切割成多个个别集成电路来单个化所述集成电路。
所述半导体电路小片可形成有多个接合垫。在将所述半导体电路小片安装到所述引线框架后，在已知的焊料凸块化工艺中每一接合垫可接纳焊料凸块。在替代实施例中，可使用其它导电的可变形材料来取代焊料。所述引线框架中包含接触指状件的一部分可位于参考平面中。所述焊料凸块的大小经选择，以便一旦回流到所述半导体电路小片接合垫上，参考平面150便穿过所述焊料凸块且所述焊料凸块的一小部分延伸超过所述参考平面。
囊封所述封装以使得所述封装的底部表面大体上位于所述参考平面中。由于在囊封工艺期间施加到所述封装上的压力，所述焊料凸块中延伸通过所述参考平面的部分变得大致平坦而与所述参考平面及所述半导体封装的底部表面齐平。因此，所述部分地平坦的焊料凸块与所述封装的外部齐平且暴露在外。所述焊料凸块的这些暴露部分形成测试垫，而可通过所述测试垫测试成品封装。
附图说明
图1是常规引线框架及半导体电路小片的分解透视图。
图2是线接合到常规引线框架的常规半导体电路小片的透视图。
图3是包含多个引线框架的面板。
图4是来自图5中所示面板的单个引线框架俯视图。
图5是包含安装于其上的半导体电路小片的引线框架的俯视图。
图6是包含用于根据本发明的实施例形成测试垫的焊料凸块的引线框架的俯视图。
图7是沿图6中的线7-7穿过一平面的剖视图。
图8是根据本发明的实施例的成品半导体封装的俯视图。
图9是根据本发明的实施例的成品半导体封装的仰视图。
图10是沿图8中的线10-10穿过一平面的剖视图。
具体实施方式
现在将参考图3到10来描述本发明的实施例，所述实施例通常涉及包含由贴附到半导体封装的焊料凸块形成的测试垫的半导体封装。应理解，本发明可以许多不同形式来具体化，且不应视为受限于本文所陈述的实施例。而是提供这些实施例使得此揭示内容将是透彻和完整的且将本发明的实施例完全传达给所属领域的技术人员。的确，本发明打算涵盖这些实施例的替代形式、修改及等效形式，所述替代形式、修改及等效形式包含于由随附权利要求书所界定的本发明的范围及精神内。此外，在以下对本发明的实施例的详细说明中，陈述了众多具体细节以提供对本发明的透彻理解。然而，所属领域的技术人员将了解可在没有所述具体细节的情况下实施本发明。
一般而言，本发明中使用的引线框架将从引线框架的面板(例如，图3中所示的面板90)批次处理。在图3中所示的实施例中，面板90包含线框架100的2×6阵列。应理解在替代实施例中，面板90可以变化的列及行的各式阵列形成。如以下所解释，将集成电路形成于面板90中的多个引线框架100上，将集成电路囊封于保护模制化合物中，且接着从所述面板将经囊封的集成电路单个化以形成多个半导体封装。
现参考图4，其显示来自面板90的单个引线框架100。引线框架100包含用于支撑一个或一个以上半导体电路小片的电路小片踏板102。引线框架100进一步包含：电引线104，其用于将电信号传送到一个或一个以上半导体电路小片或从所述半导体电路小片传送电信号；及接触指状件106，其用于在一个或一个以上半导体电路小片与外部电子装置之间传输电信号。
引线框架100可由平面或大致平面的金属件形成，所述金属可以是例如铜或铜合金、镀敷铜或镀敷铜合金、合金42(42Fe/58Ni)、或镀铜的钢。引线框架100可由其它金属及已知用于引线框架的材料形成。在实施例中，引线框架100还可用银、金、镍钯或铜来镀敷。
引线框架100可通过已知制造工艺(例如，化学蚀刻)形成。在化学蚀刻中，可将光致抗蚀剂膜施加到引线框架。接着可将含有电路小片踏板102的轮廓的图案光掩模、电引线104及接触指状件106置于光致抗蚀剂膜上。接着，可使光致抗蚀剂膜曝光及显影，以从导电层上的待蚀刻区域移除所述光致抗蚀剂。接下来，使用例如氯化铁或类似物的蚀刻剂蚀刻掉经曝光的区域，以界定引线框架100中的图案。接着可将光致抗蚀剂移除。其它已知化学蚀刻工艺是已知的。
另一选择是，可在使用级进模的机械冲压工艺中形成引线框架100。如已知，机械冲压使用成组的模以便以连续步骤将金属以机械性方式从金属条移除。
尽管本发明的实施例是使用上述引线框架100来实施，但应理解可使用其它媒介实施本发明，例如，印刷电路板及其它衬底或各种聚合物带。
现参考图5，在引线框架形成后，可将一个或一个以上半导体电路小片120安装到引线框架100的电路小片踏板102，以形成集成电路。在其中引线框架100用于Transflash快闪存储器卡的实施例中，半导体电路小片120可包含快闪存储器芯片(NOR/NAND)120a及/或例如ASIC的控制器芯片120b。然而，应理解，引线框架100可用于具有不规则形状边缘的各种半导体封装中，且各种不同的半导体芯片及装置可包含在完成的半导体封装内。可使用介电质电路小片附接化合物、膜或带以已知方式将一个或一个以上半导体电路小片120安装到引线框架100。一旦将半导体电路小片120固定到引线框架100，便可在已知的线接合工艺中使用导线122将所述电路小片线接合到引线框架的引线104。
例如，在其中电路小片120b是控制器芯片的实施例中，芯片120b可包含用于测试完成的半导体封装的操作的多个接合垫124。接合垫124可与线接合122贴附到其以将电路小片120b连接到集成电路的接合垫分离或与所述接合垫相同。应理解在替代实施例中，接合垫124的数目可变化。可使用导电迹线(未显示)将接合垫124重新分布到芯片120b上的任何所需位置。垫124的重新分布允许所述垫之间的间隔足以接纳焊料凸块，如下文所解释。应理解在替代实施例中，接合垫124无须重新分布。
现参考图6及7，一旦将半导体电路小片120安装到引线框架100上，一个或一个以上接合垫124便可接纳焊料块，例如焊料凸块132。焊料凸块132可以是已知的焊料材料，例如铅/锡(Pb/Sn)或类似物。其它可能性包含镍/金凸块、环氧树脂凸块及金凸块。也可能使用具有聚合物核心的焊料凸块。应理解，在替代实施例中，可使用其它导电的可变形材料来取代焊料。
可使用已知的焊料凸块化工艺将焊料凸块132附接至接合垫124，例如用于将焊料凸块附接于倒装芯片及球栅格阵列(BGA)中的工艺。在所述工艺中，如此项技术中已知，可首先在底凸块冶金(UBM)步骤中预调节接合垫124，以消除非导电氧化铝。UBM步骤在凸块接合垫接口处提供低且稳定的接触电阻，但在替代实施例中可省略UBM步骤。接着，可以许多工艺将焊料凸块附接到接合垫124，包含蒸镀、电镀、印刷、喷射、柱形凸点及直接放置的工艺，所述工艺的每一者在此项技术中已知。在另一实施例中，如此项技术中已知，可将焊料凸块预成形为焊料球，使用力及/或热将所述焊料球贴附到接合垫124。
如在图7的剖视图中所见，引线框架100可形成于两个平面中。引线框架100的包含接触指状件106的第一部分可位于平面150中。所述引线框架的支撑一个或一个以上半导体电路小片120的第二部分可与平面150间隔开。焊料凸块的大小经选择以使得一旦回流到电路小片120上，平面150便穿过焊料凸块132且焊料凸块132的一小部分延伸超过平面150。在实施例中，焊料凸块可具有在半导体电路小片120以上的约0.5毫米到1毫米的直径，且更明确地说，是0.7毫米到0.8毫米。应理解在替代实施例中，焊料凸块的直径可在此范围外变化。焊料凸块可延伸超过平面150约10微米到100微米，且更明确地说，是50微米到80微米。应理解，在替代实施例中，焊料凸块延伸超过平面150的程度可达到大于或小于以上所陈述的程度。在实施例中，焊料凸块中的每一者可具有近似相同的大小。
一旦焊料凸块132已附接到面板90，便可如图8到10中所示用模制化合物126来囊封集成电路的每一者。图8到10显示在从面板90单个化之后个别囊封的半导体封装142，如以下所述。模制化合物126可为例如可从住友(Sumitomo)公司及日东电工(Nitto Denko)公司购得的环氧树脂，所述二公司的总部在日本。本发明还预期来自其它制造商的其它模制化合物。可根据各种工艺来应用模制化合物，包含通过转移模制、注射模制，且在实施例中，溢流模制，以在面板90上形成含纳所有集成电路的囊封。
在所述工艺中，可将面板90置入具有上下模或模具帽的模具中。在某些实施例中，可使引线框架的多个部分保持无模制化合物。此模制化合物图案可通过在上模具帽中形成镜图案来实现。即，上模具帽经形成而具有一图案，所述图案具有在囊封工艺期间在待保持无模制化合物的部分处接触面板90的区域。应理解在替代实施例中，可将整个面板90囊封在模制化合物中。
所述封装经囊封以使得所述封装的底部表面大体上位于平面150中。在实施例中，实施囊封工艺的模制机器可输出约0.8吨的注射力以将模制化合物驱动到模腔中。由于此压力，焊料凸块132的延伸通过平面150的部分变得相对于平面150及半导体封装得底部表面大致平坦。因此，部分平坦的焊料凸块132与所述封装的外部齐平及暴露于所述封装的外部，如图9的仰视图及图10的侧剖视图所示。焊料凸块132的这些暴露部分形成测试垫，可通过所述测试垫测试成品封装。
在上述囊封工艺期间，优选地使焊料凸块132与半导体封装142的表面齐平。然而，在囊封工艺期间，替代或除平坦化所述焊料凸块之外，可执行一个或一个以上额外工艺，以在焊料凸块或其它导电的可变形块中界定表面，所述表面与半导体封装142的表面齐平。所述额外工艺可在囊封工艺之前及/或之后执行。所述额外工艺可包含向焊料凸块132施加热、压力或剪切力，以在焊料凸块中界定是或将与半导体封装142的表面齐平的表面。
尽管对本发明并非至关重要，但在模制步骤后，可将一标记施加到模制化合物126。所述标记可以是例如针对每一集成电路而印刷在模制化合物的表面上的图标其它信息。所述标记可例如指示制造商及/或装置类型。进行标记的步骤对本发明并非至关重要且在替代实施例中可加以省略。
在囊封及进行标记之后，可接着通过将面板90中的集成电路切割成多个单个集成电路封装142来单个化面板90中的每一经囊封集成电路。已知切割装置包含例如，水喷射切割、激光切割、水导引激光切割、干媒介切割、及钻石涂覆导线。水喷射切割因其小的切割宽度及快速切割速率而可为优选的切割装置。也可将水与激光切割一起使用，以帮助补充或集中其效应。对从面板切割集成电路及可由此实现的形状的进一步说明揭示于已公告的美国专利申请案第2004/0259291号中，其标题为“用于高效生产可拆卸外围卡的方法(Method For Efficiently Producing Removable PeripheralCards)”，所述申请案已让予本发明所有者且所述申请案的全文已以引用的方式并入本文中。应理解，在替代实施例中，可通过除上述以外的其它工艺来形成经单个化的集成电路。
在所示的实施例中，封装142可例如用于Transflash快闪存储器装置或MicroSD卡中。然而，应理解，在进一步实施例中，可将封装142切割成包含矩形在内的各种形状及大小。
在实施例中，提供二十一个测试垫。应理解，另一选择是，封装142可包含形成测试垫的二十七个焊料凸块132，且另一选择是可包含多于或少于二十一或二十七个，例如一个或一个以上测试垫。此外，尽管以上将焊料凸块132揭示为直接安装到控制器芯片120b上的接合垫124上，但应理解，可将在成品封装中形成测试垫的焊料凸块132提供在存储器芯片120a上或引线框架100上，且借助使用导电迹线及/或接合线而连接到适当的接合垫。
一旦制造且经由测试垫测试了封装，便可将封装包封于覆盖测试垫的一对配对盖中，且防止在使用半导体封装时接近测试垫。在进一步实施例中，所述封装可在无盖情况下操作。在所述实施例中，测试垫可使用(例如)掩膜标签、环氧树脂或墨水来覆盖。也可预想到使测试垫保持不覆盖。
已出于图解及说明目的呈现了本发明的前面详细说明。但此并不打算包罗无遗或将本发明限于所揭示的精确形式。根据以上教示内容，可进行许多修改及变更。选择所述实施例是为了最佳地解释本发明的原理及其实际应用，从而使所属领域的技术人员能够在各种实施例中最佳地利用本发明，并作出适用于所预期特定用途的各种修改。本发明的范围打算由本文随附权利要求书加以界定。

Claims (17)

1、一种形成包含半导体电路小片的半导体封装的方法，所述半导体电路小片具有用于测试所述半导体封装的电操作的测试垫，所述方法包括以下步骤：
(a)将焊料块耦合到所述半导体电路小片上的接合垫；
(b)将所述半导体电路小片囊封于模制化合物中；及
(c)使所述焊料块的至少一部分变形，以将所述接合垫上的所述焊料块成形为所述用于测试所述半导体封装的电操作的测试垫。
2、如权利要求1所述的形成半导体封装的方法，其中在所述囊封所述半导体电路小片的步骤(b)期间执行所述使所述焊料块的至少一部分变形的步骤(c)。
3、如权利要求1所述的形成半导体封装的方法，其中在所述囊封所述半导体电路小片的步骤(b)之前执行所述使所述焊料块的至少一部分变形的步骤(c)。
4、如权利要求1所述的形成半导体封装的方法，其中在所述囊封所述半导体电路小片的步骤(b)之后执行所述使所述焊料块的至少一部分变形的步骤(c)。
5、如权利要求1所述的形成半导体封装的方法，其中所述焊料块是焊料凸块。
6、如权利要求1所述的形成半导体封装的方法，其中通过以下工艺中的至少一者执行所述将焊料块耦合到接合垫的步骤(a)：蒸镀、电镀、印刷、喷射、柱形凸点及直接放置。
7、如权利要求1所述的形成半导体封装的方法，其中所述焊料块是焊料球，所述焊料球是通过施加热及压力中的至少一者而施加到所述接合垫。
8、如权利要求1所述的形成半导体封装的方法，其进一步包括在底凸块冶金步骤中预调节所述焊料块以消除非导电氧化铝的步骤。
9、一种半导体封装，其包括：
衬底；
半导体电路小片，其贴附到所述衬底；
接合垫，其形成于所述半导体电路小片中；
焊料，其提供在所述接合垫上，所述接合垫能够用作用于测试所述半导体电路小片的电特性的测试垫；及
模制化合物，其用于囊封至少所述半导体电路小片；
所述半导体封装是通过以下步骤形成的：
(a)将焊料耦合到所述接合垫；
(b)将所述半导体电路小片囊封于模制化合物中，所述囊封步骤(b)导致界定所述半导体封装的表面；及
(c)在所述将所述半导体电路小片囊封于所述模制化合物中的步骤(b)期间，使所述焊料的至少一部分变形以界定所述焊料的与在所述步骤(b)中界定的所述半导体封装的所述表面大致齐平的表面。
10、如权利要求9所述的半导体封装，其中所述衬底是引线框架。
11、如权利要求9所述的半导体封装，其中所述衬底是印刷电路板。
12、如权利要求9所述的半导体封装，其中所述半导体电路小片是快闪存储器装置中使用的控制器芯片。
13、如权利要求9所述的半导体封装，其中所述半导体封装被配置用作快闪存储器装置。
14、如权利要求9所述的半导体封装，其中所述焊料是焊料凸块。
15、如权利要求9所述的半导体封装，其中所述焊料是焊料球。
16、如权利要求9所述的半导体封装，其中所述将焊料耦合到所述接合垫的步骤(a)是通过以下工艺中的至少一者执行的：蒸镀、电镀、印刷、喷射、柱形凸点及直接放置。
17、如权利要求9所述的半导体封装，其中所述焊料是焊料球，且所述将焊料耦合到所述接合垫的步骤(a)包括通过至少施加热及压力的步骤来耦合所述焊料球的步骤。
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