CN101388381B - Multi-chip stacking construction having metal spacer - Google Patents

Multi-chip stacking construction having metal spacer Download PDF

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Publication number
CN101388381B
CN101388381B CN2007101454887A CN200710145488A CN101388381B CN 101388381 B CN101388381 B CN 101388381B CN 2007101454887 A CN2007101454887 A CN 2007101454887A CN 200710145488 A CN200710145488 A CN 200710145488A CN 101388381 B CN101388381 B CN 101388381B
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China
Prior art keywords
chip
metal
metal pads
pads
interior pin
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Expired - Fee Related
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CN2007101454887A
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Chinese (zh)
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CN101388381A (en
Inventor
林鸿村
吴政庭
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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Priority to CN2007101454887A priority Critical patent/CN101388381B/en
Publication of CN101388381A publication Critical patent/CN101388381A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A package structure stacked with a plurality of chips comprises a base plate, a first chip and a second chip, wherein the base plate is provided with a plurality of metal contacts which are mutually connected, the first surface of the first chip is fixed on the base plate through an adhesion coating, and the second surface thereof is provided with a plurality of first metal bonding pads and a plurality of second metal bonding pads, and a plurality of metal protrusions are formed on the second metal bonding pads of the first chip. The first surface of the second chip is fixed with the metal protrusions through an adhesive coating, and a plurality of metal pads are arranged on the second surface thereof, and a plurality of metal wires are used to electrically connect the first metal bonding pads on the first chip and the first metal pads on the second chip with the metal contacts on the base plate, wherein the height of the metal protrusions is larger than the largest height of the bank of the metal wires.

Description

Multi-chip stacking structure with metal spacer
Technical field
The present invention relates to the encapsulating structure of integrated circuit and the method for encapsulation thereof, particularly a kind of metal ridge that uses on chip is used as the support in the multi-chip stacking structure and the encapsulating structure of heat radiation.
Background technology
In recent years, semi-conductive post phase manufacturing technique is all being carried out three dimensions (Three Dimension; Encapsulation 3D) reaches higher density or capacity of memory etc. in the hope of utilizing minimum area.In order to reach this purpose, the mode that present stage has been developed use chip-stacked (chip stacked) is reached three dimensions (Three Dimension; Encapsulation 3D).
In known technology, for example No. 6333562 United States Patent (USP) promptly discloses a kind of structure 300 of using metal frame 350 and resin bed 340 to form multi-chip stacking, as shown in Figure 1.Clearly; in the encapsulating structure of Fig. 1; for the plain conductor 360 of avoiding lower floor's chip 310 contacts with the back side of upper strata stacked chips 320, so produce and use resin bed 340 formed differences in height to protect the plain conductor 360 of lower floor's chip 310 metal frame 350.Yet,, cause follow-up chip to be difficult for aiming at through metal frame 350 easy deformation that produce.In addition, resin bed 340 crawlings can make multi-chip structure be uneven and be loose, and increase manufacturing cost and cause and can't dwindle encapsulation volume.In addition, because plain conductor 360 has been done significantly bending, so each chip and metal pad 320a, the adhesion area deficiency of 350a in annotating membrane process, causes chip to break away from easily.
And for example in known technology, for example in the I255020 TaiWan, China patent patent, promptly disclose a kind of stacked multi-chip encapsulation 100, as shown in Figure 2, it has the bearing base 102 that comprises top side 108 and bottom side, bottom integrated circuit crystal grain 104, it has the bottom surface 112 of the top side 108 that is attached to this bearing base, and relative end face 114.End face 114 has the neighboring area that comprises a plurality of first weld pads and middle section.Between this neighboring area and this middle section, bead 124 is formed on the end face 114 of bottom die 104.This bead 124 can be kept the pre-fixed gap between 106 of this bottom die 104 and top crystal grain, so that when adhering to this top crystal grain 106 to this bottom die 104, when connecting this bottom die 104, connect this bottom die 104 to the wire bonds of first lead 122 of this bearing base 102 and can not damage to this bottom die 104.This bead there is no the function that weld pad is provided 124 times, makes whole chip area to be dwindled.
Above-mentioned prior art still has undesirable part when reality is used, therefore still have the space of improvement.
Summary of the invention
Because the shortcoming and the problem of the chip-stacked mode described in the background technology, the invention provides a kind of use and replace the structure that resin is similar to sphere (ball spacer), and the akin chip stack of a plurality of sizes is built up a kind of three-dimensional multi-chip stacking encapsulating structure by the metal ridge on weld pad.
Main purpose of the present invention is providing a kind of multi-chip stacking encapsulating structure with heat sinking function, can increase the reliability of product.
In view of the above, the present invention at first provides a kind of encapsulating structure of multi-chip stacking, comprises substrate, first chip and second chip.Substrate, its upper surface and lower surface are provided with a plurality of interconnective metallic contacts and connect use for plain conductor.First of first chip is fixed in the upper surface of this substrate by first adhesion coating, and this first chip, second face is provided with a plurality of first metal pads and a plurality of second metal pad; First of second chip is affixed by second adhesion coating and these a plurality of metal ridges, and second face of this second chip is provided with a plurality of first metal pads.A plurality of metal ridges are formed on these a plurality of second metal pads of this first chip; Many strip metals lead is in order to be electrically connected these a plurality of first metal pads on this first chip and these a plurality of first metal pads on this second chip with a plurality of metallic contacts of this upper surface of base plate.This packaging body, in order to coat the upper surface of this first chip, this second chip and this substrate, wherein the height of these a plurality of metal ridges is greater than the bank maximum height of this many strip metals lead.
The present invention then provides a kind of encapsulating structure of multi-chip stacking, comprises substrate, first chip and second chip.Substrate, its upper surface and lower surface are provided with a plurality of interconnective metallic contacts and connect use for plain conductor.First of first chip is fixed in the upper surface of this substrate by first adhesion coating, and this first chip, second face is provided with a plurality of first metal pads and a plurality of second metal pad; First of second chip is affixed by second adhesion coating and these a plurality of metal ridges, and second face of this second chip is provided with a plurality of first metal pads.A plurality of metal ridges are formed on these a plurality of second metal pads of this first chip; Many strip metals lead, in order to these a plurality of first metal pads on this first chip and these a plurality of first metal pads on this second chip are electrically connected with a plurality of metallic contacts of this upper surface of base plate, and at least one the second plain conductors are in order to be electrically connected these a plurality of second metal pads on this first chip with a plurality of metallic contacts of this upper surface of base plate.This packaging body, in order to coat the upper surface of this first chip, this second chip and this substrate, wherein the height of these a plurality of metal ridges is greater than the bank maximum height of this many strip metals lead.
The present invention then provides a kind of encapsulating structure of multi-chip stacking again, comprises lead frame, first chip and second chip.Lead frame is made up of interior pin and chip bearing that a plurality of one-tenth are arranged relatively, and this chip bearing is between the interior pin of these a plurality of relative arrangements.First of first chip is fixed in the upper surface of this substrate by first adhesion coating, and second face of this first chip is provided with a plurality of first metal pads and a plurality of second metal pad.A plurality of metal ridges are formed on these a plurality of second metal pads of this first chip.First of second chip is affixed by second adhesion coating and these a plurality of metal ridges, and second face of this second chip is provided with a plurality of first metal pads.Many strip metals lead is in order to be electrically connected these a plurality of first metal pads on this first chip and these a plurality of first metal pads on this second chip with the relative interior pin of arranging of a plurality of one-tenth of this lead frame.Packaging body, in order to coating this first chip, this second chip and this lead frame, and wherein the height of these a plurality of metal ridges greater than the bank maximum height of this many strip metals lead.
The present invention continues to provide a kind of encapsulating structure of multi-chip stacking, comprises lead frame, first chip and second chip.Lead frame is made up of interior pin and chip bearing that a plurality of one-tenth are relatively arranged, and this chip bearing is between the interior pin of these a plurality of relative arrangements, and this chip bearing has upper surface and reaches lower surface with respect to this upper surface.First multi-chip stacking structure and second multi-chip stacking structure are fixed in the upper surface and the lower surface of this chip bearing respectively.Many strip metals lead is in order to be electrically connected this first multi-chip stacking structure and this second multi-chip stacking structure with the relative interior pin of arranging of a plurality of one-tenth of this lead frame.Packaging body, in order to coat a plurality of interior pin of this first multi-chip stacking structure, this second multi-chip stacking structure and this lead frame, wherein this first multi-chip stacking structure and this second multi-chip stacking structure comprise at least one lower floor's chip, a plurality of metal ridge and upper strata chip.At least one lower floor's chip, the active surface of each this lower floor's chip are provided with a plurality of first metal pads and a plurality of second metal pad.A plurality of metal ridges are formed on these a plurality of second metal pads of this lower floor's chip.The upper strata chip, this upper strata chip affixed by second adhesion coating and these a plurality of metal ridges with respect to the back side of active surface, and wherein the height of these a plurality of metal ridges greater than the bank maximum height of this many strip metals lead.
Description of drawings
Fig. 1 is the cutaway view of known multi-chip stacking encapsulation;
Fig. 2 is the cutaway view of another known multi-chip stacking encapsulation;
Fig. 3 A is the vertical view according to first chip, first embodiment of the present invention;
Fig. 3 B is the end view according to first chip of the present invention;
Fig. 4 A is the vertical view according to first chip, second embodiment of the present invention;
Fig. 4 B is the end view according to first chip of the present invention;
Fig. 5 is the cutaway view according to multi-chip stacking encapsulating structure of the present invention;
Fig. 6 is the vertical view behind the bonding and routing according to substrate of the present invention and first chip, first embodiment;
Fig. 7 is the vertical view behind the bonding and routing according to substrate of the present invention and first chip, second embodiment;
Fig. 8 is the cutaway view according to another multi-chip stacking encapsulating structure of the present invention;
Fig. 9 is according to the cutaway view of a multi-chip stacking encapsulating structure more of the present invention;
Figure 10 is the cutaway view according to another multi-chip stacking encapsulating structure of the present invention; And
Figure 11 is according to the cutaway view of a multi-chip stacking encapsulating structure more of the present invention.
The main element description of symbols
100 stacked multi-chips encapsulate 102 bottom sides
104 bottom integrated circuit crystal grain, 106 top crystal grain
110 bottom sides, top side of 108 bearing bases
112 bottom surfaces, 114 end faces
120 middle sections, 122 first leads
124 beads, 200 chips
The 200a first chip 200b second chip
200c the 3rd chip 200d four-core sheet
The back side of 210 active surfaces, 220 chips
230 first adhesion coatings, 240 first metal pads
250 second metal pads 252 the 3rd metal pad
270 second adhesion coatings, 30 substrates
The structure of 32,34 metallic contacts, 300 multi-chip stackings
310 lower floor's chips, 320 upper strata stacked chips
320a metal pad 340 resin beds
350 metal frame 350a metal pads
360 plain conductors, 400 metal ridges
Pin in 600 lead frames 610
620 chip bearings, 640 first plain conductors
642 second plain conductors, 70 packaging bodies
Embodiment
Because principle is made in some integrated circuit encapsulation that the present invention used, and discloses in detail in prior art, so in following explanation, make principle for encapsulation, does not do complete description.And the accompanying drawing in the literary composition in following, also not according to the actual complete drafting of relative dimensions, its effect is only being expressed the schematic diagram relevant with feature of the present invention.
The present invention is a kind of three-dimensional encapsulating structure in this direction of inquiring into.In order to understand the present invention up hill and dale, detailed encapsulating structure design will be proposed in following description.Apparently, execution of the present invention does not limit the specific details that the technical staff had the knack of of chip-stacked mode.On the other hand, the detailed step of post phase manufacturing technique such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet, for preferred embodiment of the present invention, can be described in detail as follows, yet except these were described in detail, the present invention can also be implemented among other the embodiment widely, and scope of the present invention not limited, it is as the criterion with claim.
At first, please refer to Fig. 3 A, Fig. 3 B, form the vertical view and the end view of the chip in the multi-chip stacking structure for the present invention.As shown in Figure 3A, a plurality of first metal pads 240 have been provided with on the active surface 210 of chip 200, simultaneously near near chip 200 middle sections, a plurality of second metal pads 250 are set again, wherein the area of second metal pad 250 can be selected the area greater than first metal pad 240.In addition, in another embodiment of chip structure, chip 200 active surfaces 210 are provided with a plurality of first metal pads 240, simultaneously near near chip 200 middle sections, a plurality of second metal pads 250 and a plurality of the 3rd metal pad 252 are set again, wherein the distance between second metal pad 250 and the 3rd metal pad 252 is very little, for example: 1～20mil, shown in Fig. 4 A.To emphasize that at this second metal pad 250 and the 3rd metal pad 252 can be after finishing the leading portion manufacturing process of chip, grow up on the active surface of chip 200, shown in Fig. 3 B in addition again.In addition, second metal pad 250 and the 3rd metal pad 252 also can be to finish in the process of leading portion manufacturing process at chip 200 just to be arranged on the active surface, shown in Fig. 4 A and Fig. 4 B.To this, the present invention is not limited, and it is embodiments of the present invention.In addition, in the present embodiment, can also on the back side 220 with respect to active surface 210 of chip 200, optionally add adhesion coating 230 (this adhesion coating also can be used as a kind of insulating barrier 230) again.
Then, please refer to Fig. 5, be the cutaway view of the specific embodiment of multi-chip stacking of the present invention.As shown in Figure 5, multi-chip stacking structure is by substrate 30, first chip (or being called lower floor's chip) 200a, second chip (or being called the upper strata chip) 200b and many strip metals lead (640; 642) form, wherein substrate 30 is provided with a plurality of metallic contacts (32; 34).
The first chip 200a is fixed on the substrate 30 by adhesion coating 230, and the active surface of the first chip 200a is provided with a plurality of first metal pads 240 and a plurality of second metal pad 250, wherein adhesion coating 230 can be attached on the substrate 30 in advance or earlier adhesion coating 230 is attached on the back side of the first chip 200a, and the present invention is not limited.In addition, therefore the purpose of adhesion coating 230 of the present invention, so long as have the sticky material of this function, is embodiments of the present invention, for example: adhesive tape (tape) or B-Stage material etc. engaging with substrate 30 or first chip 200a formation; The purpose of substrate 30 of the present invention is to provide carrying simultaneously, therefore, so long as have this materials with function, is embodiments of the present invention, for example: circuit board or BGA circuit board material etc.
Then, on a plurality of second metal pads 250, form metal ridge 400 respectively, wherein metal ridge 400 can use tin ball (solder bump) to pile up to form, it also can be to use the routing manufacturing process to form with metal coupling (stump bump), therefore metal ridge 400 also can be a kind of gold or copper product, simultaneously, metal ridge 400 can by a plurality of tin balls pile up or a plurality of metal coupling pile up form, the present invention is not limited.Follow again, use the routing manufacturing process second metal pad 250 on the first chip 200a to be connected with metallic contact 34 on the substrate 30 with many second plain conductors 642; Then, first metal pad 240 of chip 200a is connected with metallic contact 32 on the substrate 30 with many first plain conductors 640 with another routing manufacturing process again.
Then, carry out piling up of chip 200b, with second adhesion coating 270 that the first chip 200a and the second chip 200b is affixed.In the process of piling up, second adhesion coating 270 can be formed on the active surface of the first chip 200a or on the back side of the second chip 200b, simultaneously, this second adhesion coating 270 can be the B-Stage material, therefore second adhesion coating 270 also can be used as a kind of insulating material, to this, the present invention is not limited yet.In addition, on the back side of the second chip 200b, also can select optionally to attach earlier insulating barrier 230.After the second chip 200b is fixed on the first chip 200a, can optionally toast manufacturing process, to solidify second adhesion coating 270.Then, first metal pad 240 of the second chip 200b is connected with metallic contact 32 on the substrate 30 with many first plain conductors 640 with the routing manufacturing process again.At last, again with the sealing manufacturing process with substrate 30, the first chip 200a, the second chip 200b and many strip metals lead (640; 642) coat, to finish encapsulating structure.
Be stressed that at this, in the present embodiment, the area of second metal pad 250 is bigger than first metal pad 240 on the first chip 200a, so,, can also provide second plain conductor 642 to form area required when connecting again except can on second metal pad 250, forming the metal ridge 400, as shown in Figure 6, wherein, the line of second plain conductor 642 footpath can be thicker than first plain conductor 640, so that can be as the heat radiation lead of the first chip 200a and the second chip 200b.
In addition, when if the area of second metal pad 250 can only form metal ridge 400, the next door that also can be chosen in second metal pad 250 forms one the 3rd metal pad 252 again, wherein the distance between second metal pad 250 and the 3rd metal pad 252 is very little, for example: 1～20mil, as shown in Figure 7.Because second metal pad 250 and the 3rd metal pad 252 are very approaching, therefore when the 3rd metal pad 252 with another strip metal lead 642 with after metallic contact 34 on the substrate 30 is connected, also can be used as the heat radiation lead of chip chamber.To emphasize that at this metallic contact 32 on substrate 30 and metallic contact 34 can be as two row that are divided into of Figure 6 and Figure 7; But also can be the arrangement of row, this present invention is not limited.Simultaneously, the area size that metallic contact 32 on the substrate 30 and metallic contact are 34 can be identical, but also can select with metallic contact 34 do bigger, so that the second thicker plain conductor 642 can connect effectively, so that can be as the heat radiation lead of the first chip 200a and the second chip 200b.
Then, referring again to Fig. 8, be the cutaway view of another specific embodiment of multi-chip stacking structure of the present invention.Present embodiment only in the embodiment of Fig. 5, another chip of multiple pileup 200c again on the second chip 200b.At this moment, just must be provided with second metal pad 250 or the 3rd metal pad 252 on the second chip 200b, and on second metal pad 250, form the metal ridge 400 and second plain conductor 642.Clearly, in an embodiment of the present invention, all chips in lower floor all need be arranged to Fig. 5 in the identical structure of the first chip 200a, so the first chip 200a in Fig. 8 and the second chip 200b then must have identical structure with the first chip 200a among Fig. 5.Because between the 3rd chip 200c and the second chip 200b also is affixed by second adhesion coating 270, all the other connection procedures all connection procedure with Fig. 5 are identical, so detailed process does not repeat them here.
Please continue with reference to Fig. 9, be the cutaway view of an embodiment again of multi-chip stacking encapsulating structure of the present invention.Clearly, Fig. 9 is that with difference between Fig. 5 the structure replacing of substrate 30 becomes lead frame 600, and interior pin 610 and chip bearing 620 that lead frame 600 is arranged relatively by a plurality of one-tenth are formed, and its chips bearing 620 is between the interior pin 610 of a plurality of relative arrangements.The first chip 200a is fixed on the chip bearing 620 by adhesion coating 230, and the active surface of the first chip 200a is provided with a plurality of first metal pads 240 and a plurality of second metal pad 250, wherein adhesion coating 230 can be attached on the chip bearing 620 in advance or earlier adhesion coating 230 is attached on the back side of the first chip 200a, and the present invention is not limited.Then, on a plurality of second metal pads 250, form metal ridge 400 respectively, wherein metal ridge 400 can use tin ball (solder bump) to pile up to form, it also can be to use the routing manufacturing process to form wherein with metal coupling (stump bump), metal ridge 400 can by a plurality of metal couplings pile up form.Follow again, use the routing manufacturing process second metal pad 250 on the first chip 200a to be connected with interior pin 610 with many second plain conductors 642; Then, be connected with interior pin 610 with first metal pad 240 of many first plain conductors 640 with another routing manufacturing process again the first chip 200a.Then, the second chip 200b is stacked on the first chip 200a.Because the process of piling up of the second chip 200b, identical with the embodiment of Fig. 5, so its detailed process repeats no more, at last, re-use the sealing manufacturing process with adhesive material 700 with the interior pin 610 in the lead frame 600, chip bearing 620, the first chip 200a, the second chip 200b and many strip metals lead (640; 642) coat, to finish encapsulating structure.
Be stressed that at this, in the present embodiment, similarly, the area of second metal pad 250 is bigger than the metal pad 240 on the first chip 200a, so, except can on second metal pad 250, forming the metal ridge 400, can also provide second plain conductor 642 to form area required when connecting again, as shown in Figure 6, wherein, the line footpath of second plain conductor 642 can be thicker than first plain conductor 640, so that can be as the heat radiation lead of the first chip 200a and the second chip 200b.In addition, when if the area of second metal pad 250 can only form ridge 400, the next door that also can be chosen in second metal pad 250 forms one the 3rd metal pad 252 again, wherein the distance between second metal pad 250 and the 3rd metal pad 252 is very little, for example: 1～20mil, as shown in Figure 7.Because second metal pad 250 and the 3rd metal pad 252 are very approaching, therefore when the 3rd metal pad 252 with another strip metal lead 642 with after metallic contact 34 on the substrate 30 is connected, also can be used as the heat radiation lead between the first chip 200a and the second chip 200b.
Then, please continue, be cutaway view according to another multi-chip stacking encapsulating structure of the present invention with reference to Figure 10.Clearly, the difference of Figure 10 and Fig. 9 is to form difference in height between chip bearing 620 in the lead frame 600 and the interior pin 610, and at the first chip 200a and the second chip 200b process of piling up and the sealing process on lead frame 600, then all identical with Fig. 9, so detailed process repeats no more.
Then, please continue with reference to Figure 11, for form the cutaway view of multi-chip stacking encapsulating structure on lead frame 600, wherein lead frame 600 is made up of relative interior pin 610 and the chip bearing 620 of arranging of a plurality of one-tenth, and chip bearing 620 is between the interior pin 610 of a plurality of relative arrangements.As shown in figure 11, the first chip 200a, formed first multi-chip stacking structure of the second chip 200b and the 3rd chip 200c, formed second multi-chip stacking structure of four-core sheet 200d are fixed in the upper surface and the lower surface of chip bearing 620 respectively, wherein are positioned at first chip 200a of lower floor and the active surface of the second chip 200c and are provided with a plurality of first metal pads 240 and a plurality of second metal pad 250.As previously mentioned, identical by the chip stack structure among the first chip 200a, formed first multi-chip stacking structure of the second chip 200b and the 3rd chip 200c, formed second multi-chip stacking structure of four-core sheet 200d and Fig. 9 and Figure 10, so the connection procedure of its detailed chip-stacked process, the first chip 200a, the second chip 200b, the 3rd chip 200c and four-core sheet 200d and first plain conductor 640, second plain conductor 642 repeats no more.
Be stressed that, first multi-chip stacking structure in the present embodiment and second multi-chip stacking structure, a plurality of second metal pads 250 on first chip 200a of its lower floor and the active surface of the 3rd chip 200c can further be provided with a plurality of metal ridges 400, in order to the second chip 200b and the four-core sheet 200d on contact and support upper strata.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need be understood in the scope of its additional claim item, except above-mentioned detailed description, the present invention can also implement in other embodiment widely.Above-mentioned is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; For example, the invention is not restricted to have the encapsulation of two stack crystal grain, but can be applied to the encapsulation of a plurality of stack crystal grain, i.e. the present invention can be applicable to the encapsulation pattern of all wire bonds.In addition, the size in grain size and the step can be changed to meet the requirement of package design.Therefore, should be appreciated that to the invention is not restricted to certain specific embodiments that all other do not break away from the equivalence change of being finished under the disclosed spirit or improve, and all should comprise in the claims.

Claims (9)

1. the encapsulating structure of a multi-chip stacking comprises:
Substrate, its upper surface and lower surface are provided with a plurality of interconnective metallic contacts;
First chip, first of this first chip is fixed in the upper surface of this substrate by first adhesion coating, and second face of this first chip is provided with a plurality of first metal pads and a plurality of second metal pad;
A plurality of metal ridges are formed on these a plurality of second metal pads of this first chip;
Second chip, first of this second chip is affixed by second adhesion coating and these a plurality of metal ridges, and second face of this second chip is provided with a plurality of first metal pads;
Many first plain conductors are in order to be electrically connected these a plurality of first metal pads on this first chip and these a plurality of first metal pads on this a plurality of second metal pads and this second chip with a plurality of metallic contacts of this upper surface of base plate;
At least one the second plain conductors, in order to these a plurality of second metal pads on this first chip are electrically connected with a plurality of metallic contacts of this upper surface of base plate, wherein, above-mentioned second plain conductor line footpath is thick than first plain conductor; And
Packaging body is in order to coat the upper surface of this first chip, this second chip and this substrate;
Wherein the height of these a plurality of metal ridges is greater than the bank maximum height of this many strip metals lead.
2. encapsulating structure according to claim 1 is characterized in that this substrate can be the circuit board of BGA.
3. encapsulating structure according to claim 1, the area that it is characterized in that each first metal pad on this second of this first chip are all less than the area of each second metal pad.
4. encapsulating structure according to claim 1, it is characterized in that each this metal ridge can by a plurality of tin balls pile up form.
5. encapsulating structure according to claim 1, it is characterized in that each this metal ridge can by a plurality of metal couplings pile up form.
6. the encapsulating structure of a multi-chip stacking comprises:
Lead frame is made up of interior pin and chip bearing that a plurality of one-tenth are arranged relatively, and this chip bearing is between the interior pin of these a plurality of relative arrangements;
First chip, first of this first chip is fixed in the upper surface of this chip bearing by first adhesion coating, and second face of this first chip is provided with a plurality of first metal pads and a plurality of second metal pad;
A plurality of metal ridges are formed on these a plurality of second metal pads of this first chip;
Second chip, first of this second chip is affixed by second adhesion coating and these a plurality of metal ridges, and second face of this second chip is provided with a plurality of first metal pads;
Many strip metals lead, in order to these a plurality of first metal pads on this first chip and these a plurality of first metal pads on this a plurality of second metal pads and this second chip are electrically connected with the relative interior pin of arranging of a plurality of one-tenth of this lead frame, in wherein above-mentioned many strip metals lead in order to this a plurality of second metal pads on this lower floor's chip are directly thicker with the plain conductor line of the interior pin electrical connection of the relative arrangement of a plurality of one-tenth of this lead frame; And
Packaging body is in order to coat this first chip, this second chip and this lead frame;
Wherein the height of these a plurality of metal ridges is greater than the bank maximum height of this many strip metals lead.
7. the encapsulating structure of a multi-chip stacking comprises:
Lead frame is made up of interior pin and chip bearing that a plurality of one-tenth are relatively arranged, and this chip bearing is between the interior pin of these a plurality of relative arrangements, and this chip bearing has upper surface and reaches lower surface with respect to this upper surface;
First multi-chip stacking structure and second multi-chip stacking structure are fixed in the upper surface and the lower surface of this chip bearing respectively;
Many strip metals lead is in order to be electrically connected this first multi-chip stacking structure and this second multi-chip stacking structure with the relative interior pin of arranging of a plurality of one-tenth of this lead frame; And
Packaging body is in order to coat a plurality of interior pin of this first multi-chip stacking structure, this second multi-chip stacking structure and this lead frame;
Wherein this first multi-chip stacking structure and this second multi-chip stacking structure comprise:
At least one lower floor's chip, the active face of each this lower floor's chip are provided with a plurality of first metal pads and a plurality of second metal pad;
A plurality of metal ridges are formed on these a plurality of second metal pads of this lower floor's chip;
The upper strata chip, the back side with respect to active face of this upper strata chip is affixed by second adhesion coating and these a plurality of metal ridges; And
Many strip metals lead is in order to be electrically connected these a plurality of first metal pads on this lower floor's chip and these a plurality of first metal pads on this a plurality of second metal pads and this upper strata chip with the relative interior pin of arranging of a plurality of one-tenth of this lead frame; And in above-mentioned many strip metals lead in order to the plain conductor line footpath of these a plurality of second metal pads on this lower floor's chip and the interior pin electrical connection of the relative arrangement of a plurality of one-tenth of this lead frame is thicker;
Wherein the height of these a plurality of metal ridges is greater than the bank maximum height of this many strip metals lead.
8. according to claim 6 or 7 described encapsulating structures, it is characterized in that each this metal ridge can by a plurality of tin balls pile up form.
9. according to claim 6 or 7 described encapsulating structures, it is characterized in that each this metal ridge can by a plurality of metal couplings pile up form.
CN2007101454887A 2007-09-14 2007-09-14 Multi-chip stacking construction having metal spacer Expired - Fee Related CN101388381B (en)

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Citations (3)

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Publication number Priority date Publication date Assignee Title
US6593662B1 (en) * 2000-06-16 2003-07-15 Siliconware Precision Industries Co., Ltd. Stacked-die package structure
US6706557B2 (en) * 2001-09-21 2004-03-16 Micron Technology, Inc. Method of fabricating stacked die configurations utilizing redistribution bond pads
CN1561545A (en) * 2001-09-28 2005-01-05 摩托罗拉公司 Semiconductor with multiple rows of bond pads

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6593662B1 (en) * 2000-06-16 2003-07-15 Siliconware Precision Industries Co., Ltd. Stacked-die package structure
US6706557B2 (en) * 2001-09-21 2004-03-16 Micron Technology, Inc. Method of fabricating stacked die configurations utilizing redistribution bond pads
CN1561545A (en) * 2001-09-28 2005-01-05 摩托罗拉公司 Semiconductor with multiple rows of bond pads

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