CN101395573A - 乱序处理器中的分布式记分板调度 - Google Patents
乱序处理器中的分布式记分板调度 Download PDFInfo
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- CN101395573A CN101395573A CN200780007020.XA CN200780007020A CN101395573A CN 101395573 A CN101395573 A CN 101395573A CN 200780007020 A CN200780007020 A CN 200780007020A CN 101395573 A CN101395573 A CN 101395573A
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
Abstract
Description
Avail | inRF | BP | 操作数状态描述 | 操作数可用性 |
0 | 0 | 0 | 不可能 | N/A |
0 | 0 | 1 | 生产者可能为加载失败 | 否 |
0 | 1 | 1 | 生产者可能为加载失败,它从主存储器或者硬盘读取数据 | 否 |
0 | 1 | 0 | 不可能 | N/A |
1 | 0 | 0 | 生产者被发送,计数器已经启动但是生产者还没有到达可设旁路的级 | 否 |
1 | 0 | 1 | 生产者被发送并且已经到达可设旁路的级 | 是 |
1 | 1 | 0 | 不可能 | N/A |
1 | 1 | 1 | 生产者已经完成写寄存器文件 | 是 |
指令类型 | Wakeup_en |
加 | 01 |
乘 | 10 |
除 | 11 |
Claims (27)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/362,764 US7721071B2 (en) | 2006-02-28 | 2006-02-28 | System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor |
US11/362,764 | 2006-02-28 | ||
PCT/US2007/003752 WO2007100487A2 (en) | 2006-02-28 | 2007-02-12 | Distributive scoreboard scheduling in an out-of-order processor |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101395573A true CN101395573A (zh) | 2009-03-25 |
CN101395573B CN101395573B (zh) | 2012-06-06 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN200780007020.XA Expired - Fee Related CN101395573B (zh) | 2006-02-28 | 2007-02-12 | 乱序处理器中的分布式记分板调度 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7721071B2 (zh) |
CN (1) | CN101395573B (zh) |
GB (1) | GB2448276B (zh) |
WO (1) | WO2007100487A2 (zh) |
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CN107851028A (zh) * | 2015-08-14 | 2018-03-27 | 高通股份有限公司 | 将指令操作数的窄生成值直接存储在乱序处理器中的寄存器映射中 |
CN108279928A (zh) * | 2018-01-30 | 2018-07-13 | 上海兆芯集成电路有限公司 | 微指令调度方法及使用此方法的装置 |
CN108415730A (zh) * | 2018-01-30 | 2018-08-17 | 上海兆芯集成电路有限公司 | 微指令调度方法及使用此方法的装置 |
CN109074260A (zh) * | 2016-04-28 | 2018-12-21 | 微软技术许可有限责任公司 | 乱序的基于块的处理器和指令调度器 |
CN111258657A (zh) * | 2020-01-23 | 2020-06-09 | 上海燧原智能科技有限公司 | 流水线控制方法及相关设备 |
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CN111538534A (zh) * | 2020-04-07 | 2020-08-14 | 江南大学 | 一种基于指令凋零的多指令乱序发射方法及处理器 |
CN114610394A (zh) * | 2022-03-14 | 2022-06-10 | 海飞科(南京)信息技术有限公司 | 指令调度的方法、处理电路和电子设备 |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8990543B2 (en) | 2008-03-11 | 2015-03-24 | Qualcomm Incorporated | System and method for generating and using predicates within a single instruction packet |
US7502918B1 (en) | 2008-03-28 | 2009-03-10 | International Business Machines Corporation | Method and system for data dependent performance increment and power reduction |
FR2941117B1 (fr) * | 2009-01-15 | 2011-02-11 | Peugeot Citroen Automobiles Sa | Procede et dispositif de controle du reveil, d'organes appartenant a au moins un reseau multiplexe, par comptage de reveils intempestifs |
WO2011134861A1 (en) * | 2010-04-26 | 2011-11-03 | Dong Energy A/S | Dispatch controller for a distributed electrical power system |
CN102215162B (zh) * | 2011-03-24 | 2014-07-30 | 无锡众志和达数据计算股份有限公司 | 一种基于现场可编程门阵列的光纤i/o乱序帧处理方法 |
US9529596B2 (en) | 2011-07-01 | 2016-12-27 | Intel Corporation | Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bits |
KR101667167B1 (ko) | 2012-06-15 | 2016-10-17 | 소프트 머신즈, 인크. | Load store 재정렬 및 최적화로부터 생기는 투기적 포워딩 예측 착오/오류로부터의 복원을 구현하는 방법 및 시스템 |
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EP2862069A4 (en) | 2012-06-15 | 2016-12-28 | Soft Machines Inc | DEFINING INSTRUCTIONS TO REORDER AND OPTIMIZE LOADING AND STORAGE |
WO2013188460A2 (en) | 2012-06-15 | 2013-12-19 | Soft Machines, Inc. | A virtual load store queue having a dynamic dispatch window with a distributed structure |
KR101996351B1 (ko) | 2012-06-15 | 2019-07-05 | 인텔 코포레이션 | 통합된 구조를 갖는 동적 디스패치 윈도우를 가지는 가상 load store 큐 |
US20140129805A1 (en) * | 2012-11-08 | 2014-05-08 | Nvidia Corporation | Execution pipeline power reduction |
US9424041B2 (en) * | 2013-03-15 | 2016-08-23 | Samsung Electronics Co., Ltd. | Efficient way to cancel speculative ‘source ready’ in scheduler for direct and nested dependent instructions |
WO2016097811A1 (en) * | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude load replays dependent on fuse array access in out-of-order processor |
US10108420B2 (en) | 2014-12-14 | 2018-10-23 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor |
US9645827B2 (en) | 2014-12-14 | 2017-05-09 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude load replays dependent on page walks in an out-of-order processor |
US10127046B2 (en) | 2014-12-14 | 2018-11-13 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude uncacheable-dependent load replays in out-of-order processor |
JP6286065B2 (ja) | 2014-12-14 | 2018-02-28 | ヴィア アライアンス セミコンダクター カンパニー リミテッド | アウトオブオーダープロセッサの書き込み結合メモリ領域アクセスに依存するロードリプレイを除外する装置及び方法 |
US10089112B2 (en) | 2014-12-14 | 2018-10-02 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor |
WO2016097802A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude load replays dependent on long load cycles in an out-order processor |
US10146539B2 (en) | 2014-12-14 | 2018-12-04 | Via Alliance Semiconductor Co., Ltd. | Load replay precluding mechanism |
US10108421B2 (en) | 2014-12-14 | 2018-10-23 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude shared ram-dependent load replays in an out-of-order processor |
US9740271B2 (en) | 2014-12-14 | 2017-08-22 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor |
WO2016097803A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude uncacheable-dependent load replays in out-of-order processor |
KR101822726B1 (ko) | 2014-12-14 | 2018-01-26 | 비아 얼라이언스 세미컨덕터 씨오., 엘티디. | 로드 리플레이를 억제하는 메커니즘 |
US10114794B2 (en) | 2014-12-14 | 2018-10-30 | Via Alliance Semiconductor Co., Ltd | Programmable load replay precluding mechanism |
WO2016097790A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method to preclude non-core cache-dependent load replays in out-of-order processor |
US10228944B2 (en) | 2014-12-14 | 2019-03-12 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method for programmable load replay preclusion |
US10088881B2 (en) | 2014-12-14 | 2018-10-02 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude I/O-dependent load replays in an out-of-order processor |
KR101819315B1 (ko) | 2014-12-14 | 2018-01-16 | 비아 얼라이언스 세미컨덕터 씨오., 엘티디. | 비순차 프로세서에서 작성 결합 메모리 공간 접근에 따라 로드 리플레이를 억제하기 위한 장치 및 방법 |
US10175984B2 (en) | 2014-12-14 | 2019-01-08 | Via Alliance Semiconductor Co., Ltd | Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor |
US10083038B2 (en) | 2014-12-14 | 2018-09-25 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on page walks in an out-of-order processor |
US10095514B2 (en) | 2014-12-14 | 2018-10-09 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude I/O-dependent load replays in an out-of-order processor |
US10120689B2 (en) | 2014-12-14 | 2018-11-06 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor |
US10146540B2 (en) | 2014-12-14 | 2018-12-04 | Via Alliance Semiconductor Co., Ltd | Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor |
US9804845B2 (en) | 2014-12-14 | 2017-10-31 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor |
US10108429B2 (en) | 2014-12-14 | 2018-10-23 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude shared RAM-dependent load replays in an out-of-order processor |
US9703359B2 (en) | 2014-12-14 | 2017-07-11 | Via Alliance Semiconductor Co., Ltd. | Power saving mechanism to reduce load replays in out-of-order processor |
KR101819314B1 (ko) | 2014-12-14 | 2018-01-16 | 비아 얼라이언스 세미컨덕터 씨오., 엘티디. | 비순차 프로세서에서 오프다이 제어 부재 접근에 따라 로드 리플레이를 억제하는 장치 |
US10114646B2 (en) | 2014-12-14 | 2018-10-30 | Via Alliance Semiconductor Co., Ltd | Programmable load replay precluding mechanism |
US11544214B2 (en) | 2015-02-02 | 2023-01-03 | Optimum Semiconductor Technologies, Inc. | Monolithic vector processor configured to operate on variable length vectors using a vector length register |
CN105653790B (zh) * | 2015-12-29 | 2019-03-29 | 东南大学—无锡集成电路技术研究所 | 一种基于人工神经网络的乱序处理器Cache访存性能评估方法 |
US10445100B2 (en) * | 2016-06-09 | 2019-10-15 | International Business Machines Corporation | Broadcasting messages between execution slices for issued instructions indicating when execution results are ready |
GB2563582B (en) | 2017-06-16 | 2020-01-01 | Imagination Tech Ltd | Methods and systems for inter-pipeline data hazard avoidance |
US11429555B2 (en) * | 2019-02-26 | 2022-08-30 | Apple Inc. | Coprocessors with bypass optimization, variable grid architecture, and fused vector operations |
US10956168B2 (en) * | 2019-03-08 | 2021-03-23 | International Business Machines Corporation | Post completion execution in an out-of-order processor design |
US11086626B2 (en) * | 2019-10-24 | 2021-08-10 | Arm Limited | Circuitry and methods |
CN113867793A (zh) * | 2020-06-30 | 2021-12-31 | 上海寒武纪信息科技有限公司 | 计算装置、集成电路芯片、板卡、电子设备和计算方法 |
US11687347B2 (en) * | 2021-05-25 | 2023-06-27 | Andes Technology Corporation | Microprocessor and method for speculatively issuing load/store instruction with non-deterministic access time using scoreboard |
Family Cites Families (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5109520A (en) | 1985-02-19 | 1992-04-28 | Tektronix, Inc. | Image frame buffer access speedup by providing multiple buffer controllers each containing command FIFO buffers |
US5021945A (en) * | 1985-10-31 | 1991-06-04 | Mcc Development, Ltd. | Parallel processor system for processing natural concurrencies and method therefor |
US5781753A (en) | 1989-02-24 | 1998-07-14 | Advanced Micro Devices, Inc. | Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions |
US5091851A (en) | 1989-07-19 | 1992-02-25 | Hewlett-Packard Company | Fast multiple-word accesses from a multi-way set-associative cache memory |
US5440749A (en) | 1989-08-03 | 1995-08-08 | Nanotronics Corporation | High performance, low cost microprocessor architecture |
EP0461923B1 (en) | 1990-06-15 | 1997-10-01 | Compaq Computer Corporation | True least recently used replacement apparatus |
EP0871108B1 (en) | 1991-03-11 | 2000-09-13 | MIPS Technologies, Inc. | Backward-compatible computer architecture with extended word size and address space |
US5961629A (en) | 1991-07-08 | 1999-10-05 | Seiko Epson Corporation | High performance, superscalar-based computer system with out-of-order instruction execution |
US5493667A (en) | 1993-02-09 | 1996-02-20 | Intel Corporation | Apparatus and method for an instruction cache locking scheme |
US6079014A (en) | 1993-12-02 | 2000-06-20 | Intel Corporation | Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state |
US5493523A (en) | 1993-12-15 | 1996-02-20 | Silicon Graphics, Inc. | Mechanism and method for integer divide involving pre-alignment of the divisor relative to the dividend |
US5510934A (en) | 1993-12-15 | 1996-04-23 | Silicon Graphics, Inc. | Memory system including local and global caches for storing floating point and integer data |
US5537538A (en) | 1993-12-15 | 1996-07-16 | Silicon Graphics, Inc. | Debug mode for a superscalar RISC processor |
US5604909A (en) | 1993-12-15 | 1997-02-18 | Silicon Graphics Computer Systems, Inc. | Apparatus for processing instructions in a computing system |
US5572704A (en) | 1993-12-15 | 1996-11-05 | Silicon Graphics, Inc. | System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes |
US5526504A (en) | 1993-12-15 | 1996-06-11 | Silicon Graphics, Inc. | Variable page size translation lookaside buffer |
US5740402A (en) | 1993-12-15 | 1998-04-14 | Silicon Graphics, Inc. | Conflict resolution in interleaved memory systems with multiple parallel accesses |
US6393550B1 (en) | 1993-12-30 | 2002-05-21 | Intel Corporation | Method and apparatus for pipeline streamlining where resources are immediate or certainly retired |
US5606683A (en) | 1994-01-28 | 1997-02-25 | Quantum Effect Design, Inc. | Structure and method for virtual-to-physical address translation in a translation lookaside buffer |
US5586278A (en) | 1994-03-01 | 1996-12-17 | Intel Corporation | Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor |
US5555432A (en) * | 1994-08-19 | 1996-09-10 | Intel Corporation | Circuit and method for scheduling instructions by predicting future availability of resources required for execution |
WO1996012229A1 (en) | 1994-10-14 | 1996-04-25 | Silicon Graphics, Inc. | Indexing and multiplexing of interleaved cache memory arrays |
WO1996012228A1 (en) | 1994-10-14 | 1996-04-25 | Silicon Graphics, Inc. | Redundant mapping tables |
WO1996012231A1 (en) | 1994-10-14 | 1996-04-25 | Silicon Graphics, Inc. | A translation buffer for detecting and preventing conflicting virtual addresses from being stored therein |
US6216200B1 (en) | 1994-10-14 | 2001-04-10 | Mips Technologies, Inc. | Address queue |
US5625789A (en) | 1994-10-24 | 1997-04-29 | International Business Machines Corporation | Apparatus for source operand dependendency analyses register renaming and rapid pipeline recovery in a microprocessor that issues and executes multiple instructions out-of-order in a single cycle |
US5675758A (en) | 1994-11-15 | 1997-10-07 | Advanced Micro Devices, Inc. | Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations |
US5546545A (en) | 1994-12-09 | 1996-08-13 | International Business Machines Corporation | Rotating priority selection logic circuit |
US5732242A (en) | 1995-03-24 | 1998-03-24 | Silicon Graphics, Inc. | Consistently specifying way destinations through prefetching hints |
US5799165A (en) | 1996-01-26 | 1998-08-25 | Advanced Micro Devices, Inc. | Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay |
US5764999A (en) | 1995-10-10 | 1998-06-09 | Cyrix Corporation | Enhanced system management mode with nesting |
US5670898A (en) | 1995-11-22 | 1997-09-23 | Silicon Graphics, Inc. | Low-power, compact digital logic topology that facilitates large fan-in and high-speed circuit performance |
US5734881A (en) | 1995-12-15 | 1998-03-31 | Cyrix Corporation | Detecting short branches in a prefetch buffer using target location information in a branch target cache |
US6108769A (en) | 1996-05-17 | 2000-08-22 | Advanced Micro Devices, Inc. | Dependency table for reducing dependency checking hardware |
GB2317469B (en) | 1996-09-23 | 2001-02-21 | Advanced Risc Mach Ltd | Data processing system register control |
US5966734A (en) | 1996-10-18 | 1999-10-12 | Samsung Electronics Co., Ltd. | Resizable and relocatable memory scratch pad as a cache slice |
US5802386A (en) * | 1996-11-19 | 1998-09-01 | International Business Machines Corporation | Latency-based scheduling of instructions in a superscalar processor |
US5909572A (en) | 1996-12-02 | 1999-06-01 | Compaq Computer Corp. | System and method for conditionally moving an operand from a source register to a destination register |
US5864341A (en) | 1996-12-09 | 1999-01-26 | International Business Machines Corporation | Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding |
US6044478A (en) | 1997-05-30 | 2000-03-28 | National Semiconductor Corporation | Cache with finely granular locked-down regions |
US6286130B1 (en) * | 1997-08-05 | 2001-09-04 | Intel Corporation | Software implemented method for automatically validating the correctness of parallel computer programs |
US6076159A (en) | 1997-09-12 | 2000-06-13 | Siemens Aktiengesellschaft | Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline |
US6085315A (en) | 1997-09-12 | 2000-07-04 | Siemens Aktiengesellschaft | Data processing device with loop pipeline |
US6223278B1 (en) | 1998-11-05 | 2001-04-24 | Intel Corporation | Method and apparatus for floating point (FP) status word handling in an out-of-order (000) Processor Pipeline |
US6308252B1 (en) | 1999-02-04 | 2001-10-23 | Kabushiki Kaisha Toshiba | Processor method and apparatus for performing single operand operation and multiple parallel operand operation |
EP1209559A1 (en) * | 1999-04-22 | 2002-05-29 | Hajime Seki | Computer system |
US6473837B1 (en) | 1999-05-18 | 2002-10-29 | Advanced Micro Devices, Inc. | Snoop resynchronization mechanism to preserve read ordering |
US6546477B1 (en) | 1999-09-20 | 2003-04-08 | Texas Instruments Incorporated | Memory management in embedded systems with dynamic object instantiation |
US6446197B1 (en) | 1999-10-01 | 2002-09-03 | Hitachi, Ltd. | Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions |
US6643767B1 (en) * | 2000-01-27 | 2003-11-04 | Kabushiki Kaisha Toshiba | Instruction scheduling system of a processor |
US6430655B1 (en) | 2000-01-31 | 2002-08-06 | Mips Technologies, Inc. | Scratchpad RAM memory accessible in parallel to a primary cache |
US20010052053A1 (en) | 2000-02-08 | 2001-12-13 | Mario Nemirovsky | Stream processing unit for a multi-streaming processor |
US7032226B1 (en) | 2000-06-30 | 2006-04-18 | Mips Technologies, Inc. | Methods and apparatus for managing a buffer of events in the background |
US6557127B1 (en) | 2000-02-28 | 2003-04-29 | Cadence Design Systems, Inc. | Method and apparatus for testing multi-port memories |
US6915395B1 (en) | 2000-05-03 | 2005-07-05 | Sun Microsystems, Inc. | Active address content addressable memory |
US6757817B1 (en) | 2000-05-19 | 2004-06-29 | Intel Corporation | Apparatus having a cache and a loop buffer |
US6505285B1 (en) | 2000-06-26 | 2003-01-07 | Ncr Corporation | Scratch segment subsystem for a parallel processing database system |
US6760835B1 (en) | 2000-11-22 | 2004-07-06 | Lsi Logic Corporation | Instruction branch mispredict streaming |
KR20040101231A (ko) * | 2002-03-05 | 2004-12-02 | 인터내셔널 비지네스 머신즈 코포레이션 | 외부적으로 트리거링되는 이벤트와 연관된 데이터/명령을예비 인출하는 방법 |
US7398375B2 (en) * | 2002-04-04 | 2008-07-08 | The Regents Of The University Of Michigan | Technique for reduced-tag dynamic scheduling and reduced-tag prediction |
US6836833B1 (en) | 2002-10-22 | 2004-12-28 | Mips Technologies, Inc. | Apparatus and method for discovering a scratch pad memory configuration |
US7159103B2 (en) | 2003-03-24 | 2007-01-02 | Infineon Technologies Ag | Zero-overhead loop operation in microprocessor having instruction buffer |
US7418575B2 (en) * | 2003-07-29 | 2008-08-26 | Stretch, Inc. | Long instruction word processing with instruction extensions |
US7263599B2 (en) * | 2004-02-06 | 2007-08-28 | Infineon Technologies | Thread ID in a multithreaded processor |
US7219185B2 (en) * | 2004-04-22 | 2007-05-15 | International Business Machines Corporation | Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache |
US20060095732A1 (en) * | 2004-08-30 | 2006-05-04 | Tran Thang M | Processes, circuits, devices, and systems for scoreboard and other processor improvements |
-
2006
- 2006-02-28 US US11/362,764 patent/US7721071B2/en active Active
-
2007
- 2007-02-12 CN CN200780007020.XA patent/CN101395573B/zh not_active Expired - Fee Related
- 2007-02-12 GB GB0814234A patent/GB2448276B/en not_active Expired - Fee Related
- 2007-02-12 WO PCT/US2007/003752 patent/WO2007100487A2/en active Application Filing
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GB2448276B (en) | 2011-06-15 |
WO2007100487A2 (en) | 2007-09-07 |
US20070204135A1 (en) | 2007-08-30 |
CN101395573B (zh) | 2012-06-06 |
US7721071B2 (en) | 2010-05-18 |
GB2448276A (en) | 2008-10-08 |
WO2007100487A3 (en) | 2007-11-22 |
GB0814234D0 (en) | 2008-09-10 |
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