CN101399257A - 对多芯片封装进行扩展、升级、或修理的方法及结构 - Google Patents
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Abstract
本发明涉及一种对多芯片封装进行扩展、升级、或修理的方法及结构。本发明的实施例大体上提供了用于在无需整个替换多芯片封装(MCP)的情况下改变MCP的功能性。MCP可以被设计有顶部封装基片,该顶部封装基片被设计成与附加封装相接合,当通过MCP进行感测时该附加封装改变MCP的功能性。
Description
技术领域
本发明涉及多芯片封装的技术领域。
背景技术
多芯片封装(MCP)是由塑料或陶瓷制成的、包含通过引线接合法在内部相连的两个或多个管芯的单独的半导体封装。MCP允许多个器件集成到在印刷电路板(PCB)上具有相同覆盖区(footprint)的一个单一的更紧凑的封装中,作为单个芯片器件。MCP通常通过管脚(诸如焊球或其他类型的导电元件)与PCB相接触。
发明内容
一个实施例提供了一多芯片封装及一附加封装,其中,附加封装附着至多芯片封装。该多芯片封装大体上包括多个管芯(die)、顶部及底部基片封装、以及可以探测附着至顶部封装基片的器件的存在的电路。一旦附着附加封装,则附加封装就可以自动告知MCP功能性的扩展、升级或替换正在实行中,因此允许MCP适应附加封装。
一个实施例提供了一系统,该系统大体上包括一多芯片封装(MCP)及一附加封装。该MCP具有多个管芯、用于与印刷电路板(PCB)相接合的底部封装基片、以及作为MCP与附加封装之间的接口的顶部封装基片。该附加封装附着至多芯片封装的顶部封装基片,以改变多芯片封装的功能性。
一个实施例提供了一多芯片封装(MCP)。该MCP大体上包括多个管芯、用于与印刷电路板(PCB)相接合的底部封装基片、以及作为MCP与附加封装之间的接口的顶部封装基片、以及用于探测附着至多芯片封装的顶部封装基片的附加封装的存在以改变多芯片封装的功能性的感测电路。
附图说明
因此,可以参照实施例详细地理解本发明的上述特征、对本发明的更具体描述、以上简要概括,本发明的一些实施例在附图中示出。然而,应该注意,附图仅示出了本发明的典型实施例,且因此不应被看作是限定本发明的范围,因为本发明可以允许其他等效实施例。
图1示出了根据本发明的一个实施例的被设计成接收附加封装的多芯片封装(MCP)的一个实施例。
图2示出了图1的附加有附加封装的MCP。
图3是根据本发明的一个实施例的用于通过附加封装来改变MCP的运行的实例操作的流程图。
图4A及图4B示出了通过附加封装来对MCP进行升级。
图5A及图5B示出了通过附加封装来对MCP进行扩展。
具体实施方式
本发明的实施例大体上提供了允许通过附着附加封装来扩展(例如新的逻辑电路或存储器)、升级(例如增大存储器的密度)、或修理(例如替换失效的芯片)多芯片封装(MCP)的技术。
图1是示出了多芯片封装102(MCP)的实施例的简图,该多芯片封装包含多个管芯104、顶部及底部封装基片106、108。探测电路响应于附着至顶部封装基片106的器件的存在并可以改变MCP的功能性,如以下将更详细描述的。
MCP 102中的每个管芯104均可以是各种不同功能类器件中的一种,包括存储器件和/或处理器。每个存储器件均可以是DRAM、Flash(闪存)、或任何其他易失性或非易失性存储器。此外,存储器件不必一定是同一类的。而且,在一个实施例中,一个或多个管芯104可以被保留以用于随着将附加封装附着至MCP 102的顶部封装基片106而可以利用的另外的或扩展的功能性。对于另一实施例,附加封装也可以被用于对MCP 102进行升级或修理。附加封装可以通过各种不同的方法附着至MCP 102,包括焊接、插接(socketing)等。
图2示出了图1的附加有附加封装108的MCP,以在某些方面改变MCP的功能性。将在下面的图3-图5中论述改变后的功能性(扩展、升级、及修理)的各种不同实例。
无论功能改变的类型,改变可以通过感测存在(sense-on-presence)的方法激活,如图2中所示。一旦将附加封装108附着至MCP 102,附加封装108就可以通过电能(VDD)管脚302探测电能。VDD管脚302由通过MCP 102的底部封装基片108连接至PCB 306的管脚304来驱动。电经过301 MCP 102并通过MCP 102的顶部封装基片106连接至附加封装108。
一旦探测到电能,附加封装108就可以自动通过顶部封装基片106向MCP 102发出控制信号308,以表明功能性的扩展、升级或替换正在实行中。位于MCP 102上的探测电路110可以响应于由附加封装108驱动的控制信号308,以允许MCP 102适应附加封装108。可替换地,在另一实施例中,探测电路110可以响应于由连接至MCP 102的底部封装基片108的管脚驱动的控制信号,类似于以上参照VDD管脚302所描述的方法。
根据具体实施例,附加封装可以仅提供指示以改变MCP的功能性(例如,在存在时产生信号)。作为替换方案,或此外,附加封装也可以包含各种不同类型的器件以改变(或增强)MCP的功能性。例如,附加器件可以通过包含与MCP的存储器相同或不同的存储器件来增大MCP的存储容量。例如,如果MCP具有DRAM管芯,则附件器件可以通过一个或多个另外的DRAM管芯来扩展存储容量(在同一覆盖区(footprint)内)。作为另一实例,附加封装可以附加不同类型的存储器,例如,提供非易失性存储器以补充MCP的易失性存储器。
图3示出了当附加封装附着至MCP时如何可以以各种不同的方式来改变MCP功能性。操作可以通过感测存在(sense-on-presence)来激活,如以上参照图2所论述的。
一种操作允许附加封装被用来扩展MCP的功能性202。一个实例可以附加并支持先前与MCP不相关联的一种新类型的存储器204。例如,在一个实施例中,MCP可以包含多个DRAM以及具有与另一类存储器的接口的备用管芯(或者称为保留管芯)。该备用管芯可以在直到包含与备用管芯上的存储器接口相兼容的存储器的附加封装附着至MCP之前保持不使用。
一旦附着附加封装,就可以通过激活MCP中的包含存储器接口的备用管芯206来利用位于附加封装上的存储器。在附着附加封装并激活接口之后,与MCP相通信的控制器则可以被告知附加的功能性208。对于一个实施例,控制器可以通过改变印刷电路板上的跳线设置(jumper settings)来告知210。对于另一实施例,控制器可以通过由MCP发出的状态信号来告知212。
另一操作允许附加封装被用来升级MCP中的功能性214。一个实例可以为位于MCP中的已有存储器添加更大的密度216。例如,如果MCP包含多个DRAM,则另外的DRAM可以通过附加封装附加。附加封装上的另外的DRAM可以通过另外的地址及通过藉由顶部封装基片连接在MCP与附加封装之间的芯片选择管脚来访问。然而,附加封装的可能的负面效应可能导致巨大的总线负载。因此,MCP及附加封装的驱动强度可能需要增大218。
又一实施例允许附加封装被用来替换/修理MCP上的功能性220。例如,附加封装可以包含与MCP上的某些或所有逻辑电路相同的冗余逻辑电路222或者可以用来激活位于MCP上的冗余逻辑电路。因此,在MCP、或MCP上的一个或多个管芯不再起作用的情况下,附加封装上的冗余逻辑电路可以附着至MCP并可以用作替代物(或者附加逻辑电路可以激活MCP中的冗余逻辑电路)。
在一个实施例中,该功能性可以取决于故障的程度仅通过切断整个MCP的电源224、或者切断MCP上的一个或多个管芯的电源来实现。可替换地,在另一实施例中,MCP可以被置于休眠模式226,其中MCP内的选择电路失效,因此使功耗达到最小,但仍允许MCP恢复,如果需要的话。
其他操作228可以包括通过附着附加封装仅使故障逻辑电路失效230,例如,在不用冗余逻辑电路对其进行替换的情况下。其他操作可以包括MCP的各种其他方面,诸如将存储器段重新映射(re-mapping)成不同的地址空间或者改变操作参数的一种或多种其他类型。
图4A及图4B示出了通过附加封装来升级MCP的功能性。具体地,图4A示出了采用多个DRAM 104、以及顶部及底部封装基片106、108的MCP 102。在附加封装没有附着至MCP 102的情况下,可通过控制器访问的DRAM的数量被限制为位于MCP 102上的DRAM 104的数量。然而,如图4B中所示,包含更多DRAM的附加封装108可以通过顶部封装基片106连接至MCP 102,因此允许控制器访问更多的DRAM。如前所述,附加封装上的另外的DRAM可以通过另外的地址及通过藉由顶部封装基片连接在MCP与附加封装之间的芯片选择管脚来访问。
图5A及图5B示出了在附着附加封装时扩展MCP 102的功能性。具体地,图5A示出了采用多个DRAM 104、顶部及底部封装基片106、108、以及包含闪存接口的备用管芯112的MCP 102。在附加封装没有附着至MCP 102的情况下,备用管芯112保持未激活。
然而,如图5B中所示,一旦附着包含闪存存储器的附加封装108,MCP 102中的备用管芯112被激活并准备好与附加封装108相通信。在另一实施例中,MCP可以包含多个DRAM及闪存存储器,其中闪存存储器位于备用管芯上并被激活且一旦附着附加封装108就可编址。
尽管以上描述的是本发明的实施例,但在不背离本发明的基本范围的前提下,可以想出本发明的其他及进一步的实施例,并且本发明的范围由随后的权利要求确定。
Claims (20)
1.一种系统,包括:
多芯片封装(MCP),具有多个管芯、用于与印刷电路板(PCB)相接合的底部封装基片、以及作为所述MCP与附加封装之间的接口的顶部封装基片;以及
附加封装,附着至所述多芯片封装的顶部封装基片,以改变所述多芯片封装的功能性。
2.根据权利要求1所述的系统,其中,所述多芯片封装包含为新的功能性而被保留的、并在一旦附着所述附加封装后就被激活的管芯。
3.根据权利要求1所述的系统,其中,所述多芯片封装的多个管芯包括多个动态随机存取(DRAM)存储器器件。
4.根据权利要求3所述的系统,其中,所述附加封装包含至少一个DRAM存储器器件,从而使所述附加封装与所述MCP的结合具有比MCP独自更大的存储容量。
5.根据权利要求1所述的系统,其中,所述多芯片封装的多个管芯包括至少一个非易失性存储器器件。
6.根据权利要求1所述的系统,其中,所述多芯片封装的多个管芯包括至少一个易失性存储器器件及至少一个非易失性存储器器件。
7.根据权利要求1所述的系统,其中,所述多芯片封装的多个管芯包括至少一个处理器及至少一个存储器器件。
8.一种多芯片封装(MCP),包括:
多个管芯;
底部封装基片,用于与印刷电路板(PCB)相接合;
顶部封装基片,作为所述MCP与附加封装之间的接口;以及
感测电路,用于探测附着至所述多芯片封装的顶部封装基片的附加封装的存在以改变所述多芯片封装的功能性。
9.根据权利要求8所述的MCP,其中,所述多个管芯包含为新的功能性而保留的、并在一旦附着所述附加封装后就被激活的至少一个管芯。
10.根据权利要求9所述的MCP,其中,为新的功能性而保留的管芯包含存储器接口。
11.根据权利要求10所述的MCP,其中:
所述MCP的多个管芯包括多个动态随机存取存储器(DRAM)器件;并且
所述存储器接口包括用于所述附加封装中的非易失性存储器器件的存储器接口。
12.根据权利要求8所述的MCP,其中,所述多芯片封装的多个管芯包括至少一个易失性存储器器件及至少一个非易失性存储器器件。
13.根据权利要求8所述的MCP,其中,所述多芯片封装的多个管芯包括至少一个处理器及至少一个存储器器件。
14.一种方法,包括:
感测将附加封装附着至多芯片封装(MCP)的顶部封装基片;以及
响应于感测到附着所述附加封装而改变所述MCP的功能性。
15.根据权利要求14所述的方法,其中,改变所述MCP的功能性包括使所述MCP的一个或多个管芯失效。
16.根据权利要求15所述的方法,其中,改变所述MCP的功能性还包括使所述附加封装上的器件的功能性激活以替换所述MCP的失效的一个或多个管芯的功能性。
17.根据权利要求15所述的方法,其中,使所述一个或多个管芯失效包括将所述一个或多个管芯置于休眠模式状态。
18.根据权利要求14所述的方法,还包括:
与控制器通信以告知新的功能性是可用的。
19.根据权利要求18所述的方法,其中,与所述控制器通信通过改变PCB上的跳线设置来实现。
20.根据权利要求18所述的方法,其中,与所述控制器通信通过维持从所述附加封装到所述控制器的状态信号来实现。
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US11/860,985 US7944047B2 (en) | 2007-09-25 | 2007-09-25 | Method and structure of expanding, upgrading, or fixing multi-chip package |
US11/860,985 | 2007-09-25 |
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CN111741601A (zh) * | 2020-07-09 | 2020-10-02 | 复旦大学 | 一种通用的可配置的有源基板电路结构 |
CN114129154A (zh) * | 2020-09-04 | 2022-03-04 | 美光科技公司 | 具有存储器的可穿戴监测器 |
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US8869007B2 (en) | 2012-06-14 | 2014-10-21 | International Business Machines Corporation | Three dimensional (3D) memory device sparing |
US8874979B2 (en) | 2012-06-14 | 2014-10-28 | International Business Machines Corporation | Three dimensional(3D) memory device sparing |
WO2014190005A1 (en) * | 2013-05-22 | 2014-11-27 | Transient Electronics, Inc. | Controlled transformation of non-transient electronics |
Family Cites Families (13)
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US6539497B2 (en) * | 1987-06-02 | 2003-03-25 | Texas Instruments Incorporated | IC with selectively applied functional and test clocks |
US5535331A (en) * | 1987-09-04 | 1996-07-09 | Texas Instruments Incorporated | Processor condition sensing circuits, systems and methods |
US6547364B2 (en) * | 1997-07-12 | 2003-04-15 | Silverbrook Research Pty Ltd | Printing cartridge with an integrated circuit device |
JP3871853B2 (ja) * | 2000-05-26 | 2007-01-24 | 株式会社ルネサステクノロジ | 半導体装置及びその動作方法 |
US6734539B2 (en) * | 2000-12-27 | 2004-05-11 | Lucent Technologies Inc. | Stacked module package |
JP2003006041A (ja) * | 2001-06-20 | 2003-01-10 | Hitachi Ltd | 半導体装置 |
US11275405B2 (en) * | 2005-03-04 | 2022-03-15 | Apple Inc. | Multi-functional hand-held device |
US6861288B2 (en) * | 2003-01-23 | 2005-03-01 | St Assembly Test Services, Ltd. | Stacked semiconductor packages and method for the fabrication thereof |
JP4272968B2 (ja) * | 2003-10-16 | 2009-06-03 | エルピーダメモリ株式会社 | 半導体装置および半導体チップ制御方法 |
US7372141B2 (en) * | 2005-03-31 | 2008-05-13 | Stats Chippac Ltd. | Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides |
US7423458B2 (en) * | 2006-03-08 | 2008-09-09 | Analog Devices, Inc. | Multiple sampling sample and hold architectures |
US8050657B2 (en) * | 2006-03-28 | 2011-11-01 | Texas Instruments Incorporated | Tamper resistant circuitry and portable electronic devices |
US7486525B2 (en) * | 2006-08-04 | 2009-02-03 | International Business Machines Corporation | Temporary chip attach carrier |
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CN111741601A (zh) * | 2020-07-09 | 2020-10-02 | 复旦大学 | 一种通用的可配置的有源基板电路结构 |
CN114129154A (zh) * | 2020-09-04 | 2022-03-04 | 美光科技公司 | 具有存储器的可穿戴监测器 |
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