CN101409266B - 封装结构 - Google Patents
封装结构 Download PDFInfo
- Publication number
- CN101409266B CN101409266B CN2008100969096A CN200810096909A CN101409266B CN 101409266 B CN101409266 B CN 101409266B CN 2008100969096 A CN2008100969096 A CN 2008100969096A CN 200810096909 A CN200810096909 A CN 200810096909A CN 101409266 B CN101409266 B CN 101409266B
- Authority
- CN
- China
- Prior art keywords
- nude film
- encapsulating material
- heat abstractor
- face
- encapsulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01076—Osmium [Os]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
本发明涉及一种封装结构,至少包括:散热装置;位在散热装置上的裸片,其中裸片具有第一表面,以及与第一表面相对的第二表面;邻接裸片的第一表面及散热装置的粘合层;以及封装材料,位在散热装置上,且环绕所述的裸片。其中封装材料的所有边缘分别与散热装置的每一边缘具有共同的界线。封装材料的底面邻接于散热装置的顶面。封装结构还至少包括多个传导连接装置,位在裸片的第二表面上。
Description
技术领域
本发明有关于一种集成电路,且特别是有关于一种集成电路的封装方法与结构。
背景技术
随着半导体技术的发展,半导体裸片(Die)渐渐地变得更小与更薄。造成的结果是,半导体裸片的封装变得更困难,而导致合格率降低。
封装技术可区分成二个类型。第一种封装类型被归类为芯片(Chip)层级封装,在该类型中,裸片先由晶片(Wafer)切割下来再进行封装。好处是,只有合格裸片(Know-Good-Dies)才会进行封装。该封装技术其它的好处有,可形成扇出(Fan-Out)芯片封装,也即裸片上的输入/输出点(I/O Pads)可重新配置在较裸片上的面积更广的区域,因此分布在裸片上的输入/输出点数目可以增加。
另一种封装类型一般被称为晶片层级封装(Wafer Level Package;WLP),其中晶片上的裸片一般是在切割前就被封装完成。晶片层级封装技术有许多的优点,例如较佳的产能及较低的成本。另外,底部填充材料(Under-Fill)或成型材料(Molding Compound)的需求量也较少。然而,晶片层级封装具有许多的缺点。一般晶片层级封装是以如图1所示的裸片(Bare-Die)形式来形成。锡球12形成在裸片10的顶面。在切割个别的晶片之后,裸片10并无法受到任何成型材料的保护。裸片10的边角14容易因此而碎裂。另一问题为,因为更多的电路与功能被封装至单一裸片中,裸片需要较佳的散热能力。现有的晶片层级封装工艺无法满足所述的需求。因此,需要一种新的封装技术。
发明内容
本发明所要解决的技术问题在于提供一种封装结构,能够改善半导体裸片的散热能力,以及减少裸片碎裂的可能性。
为了实现上述目的,本发明提出一种形成封装结构的方法,该方法至少包括:提供多个裸片;将多个裸片粘附至散热板;以及切割散热板成多个封装,其中每一封装均包括有所述多个裸片的其中之一,以及一小片散热板。
为了实现上述目的,本发明还提出一种形成封装结构的方法,该方法至少包括:提供晶片;涂覆晶片尺寸的粘合层及切割胶带在所述晶片上,其中晶片尺寸的粘合层邻接于晶片及切割胶带;将晶片及晶片尺寸的粘合层切割成多个第一裸片单元,每一裸片单元包括裸片及粘附在裸片上的粘合层;从多个第一裸片单元上将切割胶带分离;粘附多个第二裸片单元至一散热板上,其中每一第二裸片单元至少包括所述每一第一裸片单元中的裸片;填充封装材料至裸片间的空间;将锡球固定且电性连接至每一第二裸片上的裸片焊垫;以及切割散热板成多个封装,其中每一封装均包括有一裸片单元,以及一小片散热板。
为了实现上述目的,本发明提出一种封装结构,至少包括:散热装置;位在散热装置上的裸片,其中裸片具有第一表面,以及与第一表面相对的第二表面;邻接裸片的第一表面及散热装置的粘合层;以及封装材料,位在散热装置上,且环绕所述的裸片。其中封装材料的所有边缘分别与散热装置的每一边缘具有共同的界线。封装材料的底面邻接于散热装置的顶面。封装结构还至少包括多个传导连接装置,位在裸片的第二表面上,其中传导连接装置是选自于实质由多个锡球及导体柱所组成的一群组。
为了实现上述目的,本发明还提出一种封装结构,至少包括:散热板;位在散热板上的多个裸片;多个粘合层,每一粘合层分别邻接于每一裸片及散热板;以及多个传导连接装置,位在所述多个裸片上。
为了实现上述目的,本发明又提出一种封装结构,至少包括:散热装置;位在散热装置上的裸片;热传导粘合层,位在裸片及散热装置之间且邻接于裸片及散热装置;第一封装材料,位在散热装置上,且环绕裸片的较低部分;多个传导连接装置,位在裸片的顶面上;以及第二封装材料,位在第一封装材料上,且环绕裸片的较高部分。其中第一封装材料的顶面较低于裸片的顶面。第二封装材料的顶面较高于裸片的顶面,且第二封装材料的顶面较低于所述传导连接装置的顶面。
本发明的有益效果有,通过封装材料的保护,避免裸片的碎裂,以减少不合格率。另外,利用散热板来提供一低成本的散热能力强化的解决方案。再者,散热板可具有相同于现有的半导体晶片的尺寸,因此适用于现有的测试设备,可降低额外的设备成本支出。
附图说明
为了能够对本发明及优点有较佳的理解,请参照下述的详细说明并配合相应的附图。相关附图内容说明如下:
图1是从晶片层级工艺所产生的裸片示意图;
图2至图8B是根据本发明的一实施例的制造的各中间阶段的剖面示意图,其中裸片是在被切割下来前先封装至散热板上;
图9是包括有微机电系统装置的示范性封装结构的示意图。
【主要组件符号说明】
10:裸片 12:锡球
14:边角 20:晶片
21:裸片单元 22:裸片
24:粘合层 25:粘合层
26:切割胶带 28:粘合层
30:散热板 34:封装材料
36:焊垫 38:锡球
40:铜柱 42:封装材料
46:散热装置 50:微机电系统装置
52:保护盖 54:裸片
具体实施方式
目前较佳的实施例的产生及使用将在以下详细地讨论。然而,可以理解的是,本发明中提供了许多能够在各种特定状况下具体化的可应用的发明概念。其中所讨论的特定实施例仅用以介绍产生及使用本发明的特定方式,而并非用以限定本发明的范围。
本发明提供一种新颖的封装结构以及形成该结构的方法。以下介绍了本发明的较佳实施例的产生的各中间阶段。在所有介绍本发明的实施例及附图中,相同的参考号码用来表示相同的组件。
如同该技术领域中一般所熟知的,在完成制造后,半导体晶片一般会通过晶片研磨(Wafer-Grinding)来缩减晶片的厚度。而晶片上的裸片会进行测试。然后将晶片作切割,且只有合格裸片能够继续进行封装。图2用来介绍半导体的晶片20的切割程序,其中晶片20包括有多个相同的裸片22。裸片22可具有实质介于5密耳(Mils)至15密耳的厚度。熟悉本领域的技术人员将能够理解,在本说明中所有引述的尺寸仅仅作为说明的实施例,且可随着集成电路尺寸的缩小向下调整。裸片22较佳是具有矩形的外形,例如正方形。而较佳的结构是,每一裸片22包括有半导体衬底,其中有源器件(例如场效应晶体管、双极晶体管、光学元件、以及其它类似元件)、无源器件(例如电阻、电感、以及电容)、以及包括金属线与过孔(未示出)的内连线结构(Interconnect Structures)可形成在半导体衬底上。
切割胶带(Dicing Tape)26,即一般现有的胶带(Blue Tape),是通过粘合层(Glue Layer)24粘附在半导体的晶片20的背面,其中粘合层24的尺寸相等或甚至大于晶片20的尺寸。而较佳的是,粘合层24具有高热传导系数,例如实质大于1.57W/(m*K),该热传导系数已接近于室温下硅的热传导系数。更佳的是,粘合层24的热传导系数实质大于5W/(m*K)。而粘合层24的厚度较佳的是介于约5微米至35微米之间。热填充材料(Thermal Fillers)可添加至粘合层24以增加其散热系数。半导体的晶片20是沿着刻划线作切割,因此每一裸片22可彼此分离。随后从粘合层24上将切割胶带26卸除。由于切口延伸至粘合层24,半导体的晶片20与粘合层24被切割成裸片单元21,其中每一裸片单元21均包括粘附在一裸片22上的一小片粘合层(可称为粘合层28)。图3即示出一裸片单元21的结构示意图。
请参照图4A,裸片单元21固定在散热板(Heat-Dissipating Plate)30之上。在一较佳实施例中,散热板30为金属平板或包含金属的平板(Metal-Containing Plate),其中散热板30可以铜或铝为主要的组成。而散热装置(Heat Spreader)的厚度实质介于10密耳至30密耳之间。另外,散热板30为陶瓷平板。在又一实施例中,散热板30可由半导体材料、介电材料、或者由所述两材料与金属材料中任选其二或以上材料的组合所组成。而较佳的是,散热板30具有高热传导系数,例如实质大于1.57W/(m*K),其中该热传导系数已接近于硅的热传导系数,且更佳的是实质大于10W/(m*K)。甚至更佳的是,散热板30的热传导系数实质大于100W/(m*K),以使得裸片22所产生的热量能够通过散热板30有效地加以排除。散热板30可具有圆形的外形,且其直径实质等于一般半导体晶片的直径,例如8英寸、12英寸、及16英寸等。或者,散热板30可为正方形的外形。
散热板30上预先标示了裸片22的位置,所以裸片22能够准确地粘合在散热板30上所欲的位置。粘合层28使用在裸片22与散热板30之间。而互相邻近的裸片22的单元之间均保留有些许的空间。图4B示出了如图4A所示的结构的剖面示意图。
图4C示出了本发明的另一实施例的示意图。在该实施例中,在将裸片22粘合至散热板30前,裸片22与粘合层28互相分离。因此,粘合层28被涂覆在散热板30上,然后将裸片22粘合至粘合层28(也可称为粘合层25)上。如前面段落所讨论的,粘合层25较佳的是具有高热传导系数。
图5A及图5B示出了封装材料34被填入多个裸片22与粘合层28彼此间的空间的示意图。在图5A所示的第一实施例中,封装材料34被填入至与裸片22的顶面实质等高。需留意的是,需确定位在裸片22的顶面上的焊垫(Bonding Pads)36并没有被覆盖。在图5B所示的第二实施例中,填充的封装材料34低于裸片22的顶面。在一示范性实施例中,封装材料34的顶面与粘合层28的顶面实质等高,或封装材料34的顶面高度介于裸片22的顶面与底面之间。在图5B所示的实施例中,封装材料34不可能覆盖裸片22。封装材料34较佳为有机材料,如环氧树脂(Epoxy),该有机材料是以液态形式填充在裸片22之间的空间。然后执行固化程序(Curing Process)以固化封装材料34。所述的固化可为热固化,例如以实质175℃温度加热约1至2小时。
随后,传导连接装置(Conductive Connectors)形成在焊垫36上。图6A示出了锡球38固定在焊垫36上的示意图,其中焊垫36位在裸片22的顶面上。在一示范性实施例中,助熔剂(Flux)先涂覆至焊垫36上,接着在每一焊垫36上置放一锡球38。助熔剂可利用多个针脚(Pins)来涂覆,其中每一针脚与一焊垫36相对应。而锡球38可利用植球头(Ball Mounting Head)来传递。
在其它实施例中,如图6B所示的结构,是以如铜柱(Copper Pillar)40的导体柱(Conductor Pillars)取代锡球,并在裸片22从晶片20切割前(请参照图3)将导体柱形成在焊垫36上。铜柱40的形成包括形成可抛弃层(DisposableLayer)在晶片20的顶面,且可选择性地形成开口在可抛弃层中以暴露出焊垫36,其中可抛弃层可为介电层或干膜(Dry Film)。然后可以如电镀的工艺形成铜柱40在开口中。接着去除可抛弃层。在本说明中,锡球38及/或铜柱40可称之为传导连接装置。
请参照图7,可涂覆额外的封装材料42。而封装材料42较佳包括有环氧树脂或其它封装复合材料。在一较佳的实施例中,封装材料42以液态形式来涂覆,且利用类似于用来固化封装材料34的方法加以固化。而封装材料34及封装材料42可包括相同或不同的材质。
接着,在封装材料42的顶面作标示(未示出),沿着刻划线将图7所示的结构作切割,将裸片22及粘合层28分离成个别的封装。散热板30也被切割分离成散热装置46。图8A示出了一最后封装结构,其中该封装结构包括有裸片22及散热装置46。优点是,裸片22通过粘合层28热耦合至散热装置46上,而粘合层28具有良好的热传导系数。由裸片22所产生的热因此能够消散至散热装置46。在该阶段中,裸片22被封装材料所封装,因此裸片22的边角能够受到保护而免于碎裂。
图8B示出了如图4C所示的结构的最终结果示意图。因为粘合层25在切割前为连续层,故最后的粘合层28延伸至封装的边缘,且粘合层28的多个边缘分别与散热装置46的每一边缘具有共同的界线。
本发明的实施例也可应用在微机电系统(Micro-Electro-MechanicalSystem;MEMS)装置上。如同现有的技术,微机电系统是通过微型化的制造(Micro-Fabrication)技术将位在一般硅衬底上的机械元件、传感器、执行器(Actuator)及电子元件作整合。图9示出了一包括有裸片54及微机电系统装置50的示范性结构,其中该结构是由保护盖52所保护。散热装置46是透过粘合层28粘覆在保护盖52上。借着将裸片54、微机电系统装置50、及保护盖52整合成一单裸片,如图9所示的封装结构,因此可利用实质相同于如图4A至图8B所示的方法及材料加以形成。
所述的本发明的实施例具有多个优点。第一,在裸片的封装过程中,裸片可通过封装材料加以保护,且可因此避免裸片的碎裂。第二,散热板的使用不仅改善薄裸片(Thin Dies)的处理,也可提供一低成本的热强化解决方案。此外,散热板可具有相同于现有的半导体晶片的尺寸,且因此还适用于现有的晶片测试设备。晶片测试的成本可因此而降低。
当然,本发明还可有其它多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员当可根据本发明做出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
Claims (14)
1.一种封装结构,其特征在于,至少包括:
一散热装置;
一裸片,位在该散热装置上,其中该裸片具有一第一表面,以及相对于该第一表面的一第二表面;
一粘合层,邻接该裸片的该第一表面及该散热装置;
一封装材料,位在该散热装置上,且环绕该裸片,其中该封装材料的所有边缘分别与该散热装置的每一边缘具有共同的界线,且其中该封装材料的一底面邻接于该散热装置的一顶面,该封装材料至少包括邻接于该散热装置的一第一层,及位在该第一层上的一第二层;以及
多个传导连接装置,位在该裸片的该第二表面。
2.根据权利要求1所述的封装结构,其特征在于,该封装材料至少包括一顶面,该封装材料的该顶面高于该裸片的一顶面,且其中所述传导连接装置的下部掩藏在该封装材料中。
3.根据权利要求1所述的封装结构,其特征在于,该封装材料的该第一层及该第二层包括有不同的材料。
4.根据权利要求1所述的封装结构,其特征在于,该散热装置至少包括一金属。
5.根据权利要求1所述的封装结构,其特征在于,该散热装置的厚度介于10密耳至30密耳之间。
6.根据权利要求1所述的封装结构,其特征在于,该粘合层的厚度介于5密耳至35密耳之间。
7.根据权利要求1所述的封装结构,其特征在于,该封装材料环绕该粘合层。
8.根据权利要求1所述的封装结构,其特征在于,所述传导连接装置是选自于由多个锡球及导体柱所组成的一群组。
9.一种封装结构,其特征在于,至少包括:
一散热装置;
一裸片,位在该散热装置上,其中该裸片具有一第一表面,以及相对于该第一表面的一第二表面;
一粘合层,邻接该裸片的该第一表面及该散热装置,其中该粘合层的边缘分别与该散热装置的每一边缘具有共同的界线;
一第一封装材料,位在该粘合层上,且环绕该裸片的一下部,其中该第一封装材料的一顶面较低于该裸片的该第二表面,该第一封装材料的一底面邻接于该粘合层的一顶面;
多个传导连接装置,位在该裸片的该第二表面上;以及
一第二封装材料,位在该第一封装材料上,且环绕该裸片的一上部,其中该第二封装材料的一顶面较高于该裸片的该第二表面,且该第二封装材料的该顶面较低于所述传导连接装置的顶面。
10.一种封装结构,其特征在于,至少包括:
一散热板;
多个裸片,位在该散热板上
多个粘合层,每一所述粘合层分别邻接于每一所述裸片及该散热板,其中所述多个裸片以一空间彼此分离;
一封装材料,位在所述裸片及所述粘合层之间的空间,其中该封装材料至少包括邻接于该散热板的一第一层,及位在该第一层上的一第二层;以及
多个传导连接装置,位在所述裸片上,其中每一所述传导连接装置的一部分掩藏在该封装材料中。
11.根据权利要求10所述的封装结构,其特征在于,每一所述传导连接装置的一额外部分暴露在该封装材料上。
12.根据权利要求10所述的封装结构,其特征在于,该散热板是一金属平板。
13.根据权利要求10所述的封装结构,其特征在于,该散热板是一陶瓷平板。
14.一种封装结构,其特征在于,至少包括:
一散热装置;
一裸片,位在该散热装置上;
一粘合层,位在该裸片及该散热装置之间且邻接该裸片及该散热装置;
一第一封装材料,位在该散热装置上,且环绕该裸片的一下部,其中该第一封装材料的一顶面较低于该裸片的一顶面;
多个传导连接装置,位在该裸片的该顶面上;以及
一第二封装材料,位在该第一封装材料上,且环绕该裸片的一上部,其中该第二封装材料的一顶面较高于该裸片的该顶面,且该第二封装材料的该顶面较低于所述传导连接装置的顶面。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/871,802 US7772691B2 (en) | 2007-10-12 | 2007-10-12 | Thermally enhanced wafer level package |
US11/871,802 | 2007-10-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101409266A CN101409266A (zh) | 2009-04-15 |
CN101409266B true CN101409266B (zh) | 2011-11-16 |
Family
ID=40533384
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008100969096A Active CN101409266B (zh) | 2007-10-12 | 2008-05-07 | 封装结构 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7772691B2 (zh) |
CN (1) | CN101409266B (zh) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8258624B2 (en) | 2007-08-10 | 2012-09-04 | Intel Mobile Communications GmbH | Method for fabricating a semiconductor and semiconductor package |
US7985662B2 (en) * | 2009-04-14 | 2011-07-26 | Powertech Technology Inc. | Method for manufacturing dies formed with a dielectric layer |
EP2330618A1 (en) * | 2009-12-04 | 2011-06-08 | STMicroelectronics (Grenoble 2) SAS | Rebuilt wafer assembly |
US8497587B2 (en) * | 2009-12-30 | 2013-07-30 | Stmicroelectronics Pte Ltd. | Thermally enhanced expanded wafer level package ball grid array structure and method of making the same |
US8378480B2 (en) * | 2010-03-04 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy wafers in 3DIC package assemblies |
US20110221053A1 (en) * | 2010-03-11 | 2011-09-15 | Qualcomm Incorporated | Pre-processing to reduce wafer level warpage |
US8829676B2 (en) * | 2011-06-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for wafer level package |
US9246052B2 (en) | 2011-07-15 | 2016-01-26 | Institute Of Semiconductors, Chinese Academy Of Sciences | Packaging structure of light emitting diode and method of manufacturing the same |
US8513098B2 (en) * | 2011-10-06 | 2013-08-20 | Stats Chippac, Ltd. | Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more eWLB packages per wafer with encapsulant deposited under temperature and pressure |
US8524577B2 (en) | 2011-10-06 | 2013-09-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more eWLB packages per wafer with encapsulant deposited under temperature and pressure |
TWI489600B (zh) * | 2011-12-28 | 2015-06-21 | Xintec Inc | 半導體堆疊結構及其製法 |
US9006000B2 (en) * | 2012-05-03 | 2015-04-14 | Sandisk Technologies Inc. | Tj temperature calibration, measurement and control of semiconductor devices |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US9123685B2 (en) | 2013-07-15 | 2015-09-01 | Freescale Semiconductor Inc. | Microelectronic packages having frontside thermal contacts and methods for the fabrication thereof |
US9099454B2 (en) * | 2013-08-12 | 2015-08-04 | Infineon Technologies Ag | Molded semiconductor package with backside die metallization |
US9275878B2 (en) | 2013-10-01 | 2016-03-01 | Infineon Technologies Ag | Metal redistribution layer for molded substrates |
US10056294B2 (en) * | 2013-12-02 | 2018-08-21 | Maxim Integrated Products, Inc. | Techniques for adhesive control between a substrate and a die |
CN114242698A (zh) * | 2014-07-17 | 2022-03-25 | 蓝枪半导体有限责任公司 | 半导体封装结构及其制造方法 |
CN104916599B (zh) | 2015-05-28 | 2017-03-29 | 矽力杰半导体技术(杭州)有限公司 | 芯片封装方法和芯片封装结构 |
US10037975B2 (en) | 2016-08-31 | 2018-07-31 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and a method of manufacturing the same |
US10319707B2 (en) * | 2017-09-27 | 2019-06-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor component, package structure and manufacturing method thereof |
US10515901B2 (en) * | 2017-09-29 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | InFO-POP structures with TIVs having cavities |
CN117303305A (zh) * | 2023-11-29 | 2023-12-29 | 麦斯塔微电子(深圳)有限公司 | 一种mems器件封装结构及其制备方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101028728A (zh) * | 2005-09-26 | 2007-09-05 | 育霈科技股份有限公司 | 晶片级尺寸封装的切割方法 |
CN101101900A (zh) * | 2006-06-27 | 2008-01-09 | 奇梦达股份公司 | 管芯配置及制造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6605525B2 (en) * | 2001-05-01 | 2003-08-12 | Industrial Technologies Research Institute | Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed |
US6908784B1 (en) * | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
US6940177B2 (en) * | 2002-05-16 | 2005-09-06 | Dow Corning Corporation | Semiconductor package and method of preparing same |
US7312101B2 (en) * | 2003-04-22 | 2007-12-25 | Micron Technology, Inc. | Packaged microelectronic devices and methods for packaging microelectronic devices |
TWI253155B (en) * | 2003-05-28 | 2006-04-11 | Siliconware Precision Industries Co Ltd | Thermally enhanced semiconductor package and fabrication method thereof |
WO2005036633A1 (ja) * | 2003-10-07 | 2005-04-21 | Nagase & Co., Ltd. | 電子部材の製造方法、及び、接着材付icチップ |
TWI259564B (en) * | 2003-10-15 | 2006-08-01 | Infineon Technologies Ag | Wafer level packages for chips with sawn edge protection |
TWI245350B (en) * | 2004-03-25 | 2005-12-11 | Siliconware Precision Industries Co Ltd | Wafer level semiconductor package with build-up layer |
-
2007
- 2007-10-12 US US11/871,802 patent/US7772691B2/en active Active
-
2008
- 2008-05-07 CN CN2008100969096A patent/CN101409266B/zh active Active
-
2010
- 2010-07-01 US US12/829,017 patent/US8039315B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101028728A (zh) * | 2005-09-26 | 2007-09-05 | 育霈科技股份有限公司 | 晶片级尺寸封装的切割方法 |
CN101101900A (zh) * | 2006-06-27 | 2008-01-09 | 奇梦达股份公司 | 管芯配置及制造方法 |
Non-Patent Citations (1)
Title |
---|
说明书第8页第25行至第11页第23行及附图3A-3Q. |
Also Published As
Publication number | Publication date |
---|---|
US7772691B2 (en) | 2010-08-10 |
US8039315B2 (en) | 2011-10-18 |
CN101409266A (zh) | 2009-04-15 |
US20100273296A1 (en) | 2010-10-28 |
US20090096085A1 (en) | 2009-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101409266B (zh) | 封装结构 | |
TWI606563B (zh) | 薄型晶片堆疊封裝構造及其製造方法 | |
CN103811430B (zh) | 层叠封装结构及其形成方法 | |
TWI305410B (en) | Multi-chip package structure | |
CN104037153B (zh) | 3d封装件及其形成方法 | |
TWI517342B (zh) | 覆晶晶圓級封裝及其方法 | |
US5879964A (en) | Method for fabricating chip size packages using lamination process | |
CN103077933B (zh) | 三维的芯片到晶圆级集成 | |
KR101476883B1 (ko) | 3차원 패키징을 위한 응력 보상층 | |
US10276545B1 (en) | Semiconductor package and manufacturing method thereof | |
US20130069218A1 (en) | High density package interconnect with copper heat spreader and method of making the same | |
US7776648B2 (en) | High thermal performance packaging for circuit dies | |
US8815645B2 (en) | Multi-chip stacking method to reduce voids between stacked chips | |
TWI628757B (zh) | 終極薄扇出型晶片封裝構造及其製造方法 | |
CN103201833A (zh) | 密封管芯、包含该密封管芯的微电子封装以及制造所述微电子封装的方法 | |
US8093104B1 (en) | Multi-chip stacking method to reduce voids between stacked chips | |
US9147600B2 (en) | Packages for multiple semiconductor chips | |
CN102810520A (zh) | 热改善的集成电路封装件 | |
TWI543320B (zh) | 半導體封裝件及其製法 | |
US20130234330A1 (en) | Semiconductor Packages and Methods of Formation Thereof | |
US10504841B2 (en) | Semiconductor package and method of forming the same | |
CN212392233U (zh) | 晶圆级芯片封装结构 | |
CN101295655A (zh) | 平板/晶圆结构封装设备与其方法 | |
US20170178993A1 (en) | Electronic component and methods of manufacturing the same | |
JP2003258158A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |