CN101414555B - Method for manufacturing flash memory floating gate - Google Patents
Method for manufacturing flash memory floating gate Download PDFInfo
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- CN101414555B CN101414555B CN2007100941467A CN200710094146A CN101414555B CN 101414555 B CN101414555 B CN 101414555B CN 2007100941467 A CN2007100941467 A CN 2007100941467A CN 200710094146 A CN200710094146 A CN 200710094146A CN 101414555 B CN101414555 B CN 101414555B
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- floating gate
- polysilicon
- flash memory
- silicon dioxide
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Abstract
The invention discloses a method for manufacturing a flash floating gate, a bowl-shaped groove of the floating gate is formed by isotropic dry etching with the help of a photoresist mask; then silicon dioxide is deposited in the bowl-shaped groove, the silicon dioxide which is positioned at the outside of the bowl-shaped groove is removed by using the chemical polishing method, thereby forming the floating gate; and then polycrystalline silicon which is positioned out of a flash unit is removed by the self-alignment mode with the help of the dry etching to form the acute periphery of the floating gate, thereby ensuring the floating gate structure not to be affected by other operations during the manufacturing process of the flash, further improving the production efficiency and leading the process to be easy in the optimization of the tip of the floating gate and have smaller fluctuations. The method can reduce the erase failure and reduce the erase voltage in the implementation of the erase action of the flash, thereby leading the flash unit to be easier to control.
Description
Technical field
The present invention relates to flash memory and make the field, relate in particular to a kind of method for manufacturing flash memory floating gate.
Background technology
The flash memory of floating gate structure adopts the most advanced and sophisticated polysilicon of band as floating boom usually, and the most advanced and sophisticated Be Controlled grid of floating boom cover.And will implement to wipe to flash memory the time, by the source being missed low-voltage, control gate connects high voltage, the electronics in the floating boom will be subjected to the floating boom periphery most advanced and sophisticated near high effect of electric field tunnelling flow to control gate by the oxide layer between floating boom and the control gate.In existing floating grid structure flash memory manufacture process, usually all use the local field method for oxidation to form the tip of floating boom, this method is more to the subsequent step that pointed shape impacts, therefore can cause production efficiency lower, be not easy the tip is optimized, and when flash memory was implemented erasing move, efficient was affected easily and causes wiping not exclusively.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method for manufacturing flash memory floating gate, can avoid in the flash memory manufacture process subsequent operation to the influence at established floating boom tip, and then can enhance productivity, and be easy to realize that the tip to floating boom is optimized, it is less to fluctuate.
For solving the problems of the technologies described above, the invention provides a kind of method for manufacturing flash memory floating gate, comprising:
(1) at substrate 201 surface heat oxidation one deck gate oxides 202, deposition one deck polysilicon 203 on described gate oxide 202 is coated photoresist 204 then subsequently;
(2) described polysilicon 203 is carried out photoetching,, on described polysilicon 203, form the bowl-type groove of floating boom with isotropic dry etch then by photoresist 204 masks;
(3) described polysilicon 203 is mixed;
(4) deposit layer of silicon dioxide 205 on the polysilicon after the doping 203;
(5) utilize chemico-mechanical polishing to remove the silicon dioxide 205 that is positioned at described bowl-type groove outside, form floating boom; And then utilize the autoregistration dry etching, remove the polysilicon 203 that is not covered by described silicon dioxide 205.
The present invention has such beneficial effect owing to adopted technique scheme, promptly by by the optical cement mask, forms the bowl-type groove of floating boom with isotropic dry etch; Deposition of silica in the described then bowl-type groove, and utilize the method for chemical polishing to remove the silicon dioxide that is positioned at described bowl-type groove outside, thus form floating boom; And then by dry etching the polysilicon beyond the flash cell is removed with self-aligned manner, form sharp-pointed floating boom periphery, thereby guaranteed that this floating gate structure can not be subjected to the influence of other operations in the flash memory manufacture process, and then improved the production efficiency height, make that technology is easy to the tip of floating boom is optimized and fluctuateed less.And the method for the invention guaranteed can reduce and wipe inefficacy when flash memory is implemented erasing move, reduces erasing voltage, makes flash cell more be easy to control.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the schematic flow sheet of flash memory floating gate structure constructed in accordance;
Fig. 2 a-2f is the structural representation in the floating gate structure manufacture process according to the present invention.
Embodiment
Below by Fig. 1 and Fig. 2, method for manufacturing flash memory floating gate of the present invention is described specifically, this method mainly may further comprise the steps:
(1) substrate 201 monocrystalline silicon surface thermal oxidations one layer thickness exists
Film 202 in the scope, as the gate oxide 202 of floating boom, deposition one layer thickness exists on described gate oxide 202 subsequently
Polysilicon 203 in the scope is coated photoresist 204, then so that described polysilicon 203 is carried out photoetching, specifically shown in Fig. 2 a.
(2) utilize known photoetching technique that described polysilicon 203 is carried out photoetching,, on described polysilicon 203, form the bowl-type groove (being the flash cell district) of floating boom with isotropic dry etch, specifically shown in Fig. 2 b then by photoresist 204 masks.
(3) shown in Fig. 2 c, described polysilicon 203 is carried out phosphorus (P) ion doping, to reduce its resistivity.
(4) deposit one layer thickness exists on the polysilicon after the doping 203
In the scope, and be preferably
Silicon dioxide 205, specifically shown in Fig. 2 d.
(5) utilize chemico-mechanical polishing to remove the silicon dioxide 205 that is positioned at described bowl-type groove outside, thereby form floating boom; And then utilize the autoregistration dry etching, remove the polysilicon 203 that is not covered, thereby formed sharp-pointed floating boom periphery, specifically shown in Fig. 2 e by silicon dioxide 205.
(6) subsequently, regrowth one layer thickness exists on whole silicon wafer
In the scope, and be preferably
Control gate oxide layer 206, deposit one layer thickness exists on described gate oxide then
In the scope, and be preferably
The polysilicon of control gate 207, utilize known photoetching technique afterwards, to described polysilicon carry out photoetching and do carve after, just obtained required flash memory structure, specifically shown in Fig. 2 f.As can be seen, the operations in this step (6) can not produce any influence to the tip of established floating boom.
Claims (6)
1. a method for manufacturing flash memory floating gate is characterized in that, comprising:
(1) at substrate (201) surface heat oxidation one deck gate oxide (202), go up deposition one deck polysilicon (203) at described gate oxide (202) subsequently, coat photoresist (204) then;
(2) described polysilicon (203) is carried out photoetching,, go up the bowl-type groove that forms floating boom at described polysilicon (203) with isotropic dry etch then by photoresist (204) mask;
(3) described polysilicon (203) is mixed;
(4) polysilicon after doping (203) is gone up deposit layer of silicon dioxide (205);
(5) utilize chemico-mechanical polishing to remove the silicon dioxide (205) that is positioned at described bowl-type groove outside, form floating boom; And then utilize the autoregistration dry etching, remove the polysilicon (203) that is not covered by described silicon dioxide (205).
2. method for manufacturing flash memory floating gate according to claim 1 is characterized in that, the thickness of described gate oxide (202) 85～
In the scope, the thickness of described polysilicon (203) 1200～
In the scope.
3. method for manufacturing flash memory floating gate according to claim 1 and 2 is characterized in that, the thickness of the silicon dioxide (205) of institute's deposit in described step (4) 800～
In the scope.
4. method for manufacturing flash memory floating gate according to claim 3 is characterized in that, the thickness of the silicon dioxide (205) of institute's deposit in described step (4) is
5. according to claim 1,2 or 4 described method for manufacturing flash memory floating gate, it is characterized in that to described polysilicon (203) doping in described step (3) is phosphonium ion.
6. method for manufacturing flash memory floating gate according to claim 3 is characterized in that, to described polysilicon (203) doping in described step (3) is phosphonium ion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100941467A CN101414555B (en) | 2007-10-16 | 2007-10-16 | Method for manufacturing flash memory floating gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100941467A CN101414555B (en) | 2007-10-16 | 2007-10-16 | Method for manufacturing flash memory floating gate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101414555A CN101414555A (en) | 2009-04-22 |
| CN101414555B true CN101414555B (en) | 2011-12-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2007100941467A Active CN101414555B (en) | 2007-10-16 | 2007-10-16 | Method for manufacturing flash memory floating gate |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101923296B (en) * | 2009-06-17 | 2011-12-14 | 上海华虹Nec电子有限公司 | Making method of photoetching fiducial mark in process of making NVM (Non-Volatile Memory) device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5045488A (en) * | 1990-01-22 | 1991-09-03 | Silicon Storage Technology, Inc. | Method of manufacturing a single transistor non-volatile, electrically alterable semiconductor memory device |
| CN1841783A (en) * | 2005-03-07 | 2006-10-04 | 三星电子株式会社 | Split gate memory unit and its array manufacturing method |
| CN1945798A (en) * | 2005-08-17 | 2007-04-11 | 三星电子株式会社 | Method of manufacturing a non-volatile memory device |
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2007
- 2007-10-16 CN CN2007100941467A patent/CN101414555B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5045488A (en) * | 1990-01-22 | 1991-09-03 | Silicon Storage Technology, Inc. | Method of manufacturing a single transistor non-volatile, electrically alterable semiconductor memory device |
| CN1841783A (en) * | 2005-03-07 | 2006-10-04 | 三星电子株式会社 | Split gate memory unit and its array manufacturing method |
| CN1945798A (en) * | 2005-08-17 | 2007-04-11 | 三星电子株式会社 | Method of manufacturing a non-volatile memory device |
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| CN101414555A (en) | 2009-04-22 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |