CN101458639B - Central processing unit type recognition circuit and central processing unit type identification method - Google Patents
Central processing unit type recognition circuit and central processing unit type identification method Download PDFInfo
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- CN101458639B CN101458639B CN2007101621019A CN200710162101A CN101458639B CN 101458639 B CN101458639 B CN 101458639B CN 2007101621019 A CN2007101621019 A CN 2007101621019A CN 200710162101 A CN200710162101 A CN 200710162101A CN 101458639 B CN101458639 B CN 101458639B
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Abstract
The invention provides a central processing unit type recognition circuit comprising a pulse-generating circuit, a latch and a control module. The pulse-generating circuit receives a VTT_PG signal by being delayed and generates a pulse signal for latching an MS_ID signal transmitted by the central processing unit. The latch is respectively connected with the pulse-generating circuit and the central processing unit for receiving the pulse signal and taking out and latching the MS_ID signal transmitted by the central processing unit when receiving the pulse signal. The control module is connected to the latch for acquiring the MS_ID signal transmitted by the central processing unit in the latch and judging the type of the central processing unit. The invention can a VID signal and the MS_ID signal which is transmitted by the central processing unit and shared with the same one pin with the MS_ID signal for the control module to judge the type of the central processing unit, thereby adjusting the appropriate system operation mode.
Description
Technical field
The present invention relates to a kind of computer realm, particularly a kind of circuit and the method that can discern the CPU type of VID signal and the same pin of MS_ID signal common.
Background technology
Along with the fast development of computer technology, when function was more and more perfect, its processing speed was also more and more faster.In order to make computing machine normally operate and to improve processing speed, certainly will need to select correct mode of operation.And the configuration of computing machine is not one old constant, and different configuration often needs different mode of operations.As one or two dissimilar central processing unit (CPU) etc. can be installed on some mainboards, if in this case with the mode of operation operational system of mistake, may reduce the travelling speed of central processing unit greatly, even cause system mistake.Therefore the type of each parts is one crucial program in the detection system.
MS ID (Market Segment ID) is the signal for the system identification CPU type, and general CPU can provide special-purpose pin to read for other control module in the system.But, there are some central processing units then to cancel special-purpose MS_ID signal pin now, provide the pin of VID signal (central processing unit voltage identification signal) that the MS_ID signal is provided simultaneously but utilize.(as the signal among Fig. 1) therefore receives VTT_PG signal (normal working voltage signal) at central processing unit, be under the state of computer one start, central processing unit is output MS_ID signal earlier, and then exports normal VID signal (the POC section among Fig. 2 is the time period that sends the MS_ID signal).Because MS_ID signal and the same pin of VID signal common, and the MS_ID signal be only launch computer in a flash just output signal, therefore other control elements can't obtain the MS_ID signal At All Other Times in the system, cause other control module in the system can't obtain the type of central processing unit thus, be unfavorable for the running of the every function of system.
The patent No. is the sequence shade curtain read-only storage adaptor that the patent of invention of TW00460791 has disclosed a kind of hardware type, it can be coupled between central processing unit and the sequence shade curtain read-only storage, in order to allow central processing unit see through hardware fully, and need not use software, just can read data stored in the sequence shade curtain read-only storage.This adapter comprises address latch, the first ternary control gate, address comparator, main control unit, access control signal generator, data latches and the second ternary control gate.The operator scheme that the characteristics of this adapter are to adopt address comparator to judge that at present received address institute should carry out is non-ly to read the page operations pattern or for reading the page operations pattern, and employing main control unit and access control signal generator produce the required control signal of switch mode.Be hardware circuit because all in this adapter are formed member, do not need software program to control fully.
The foregoing invention patent is the shared address/data bus that data latches is coupled to sequence shade curtain read-only storage, in order to latch the data that sequence shade curtain read-only storage is exported.It is the action of latching how to carry out reading of data that but the foregoing invention patent does not disclose data latches.In addition, the foregoing invention patent has solved central processing unit and has directly read data in the sequence shade curtain read-only storage by hardware, and do not solve MS_ID signal and the same pin of VID signal common in the prior art, and cause other control chip in the system can't obtain the problem of CPU type.
Summary of the invention
The purpose of this invention is to provide a kind of central processing unit type recognition circuit, the signal (MS_ID signal) because of confession system identification CPU type makes control module can't obtain the MS_ID signal with the shared same pin of central processing unit voltage identification signal (VID signal) in the existing computer system to solve, so that can't judge the problem of CPU type.
Another object of the present invention provides a kind of CPU type recognition methods, to solve in the existing computer system, consequently can't judge the problem of CPU type because of MS_ID signal and the same pin of VID signal common make control module can't obtain the MS_ID signal.
The present invention proposes a kind of central processing unit type recognition circuit, and in order to the type of the central processing unit of identification VID signal and the same pin of MS_ID signal common, this central processing unit type recognition circuit comprises pulse-generating circuit, latch and control module.Pulse-generating circuit is in order to receiving trigger pip, and produces in order to latch the pulse signal of the MS_ID signal that central processing unit sends, and wherein this trigger pip is normal working voltage signal or delayed normal working voltage signal.Latch comprises input end, output terminal and clock end.Clock end connects the output of pulse-generating circuit.Input end connects the VID signal of central processing unit and the shared pin of MS_ID signal, in order to latch the MS_ID signal that VID signal and the same pin of MS_ID signal common send under the control of pulse signal.Control module is connected to the output terminal of latch, in order to obtain the MS_ID signal of the central processing unit transmission through latching, to judge the type of central processing unit.
According to the described central processing unit type recognition circuit of preferred embodiment of the present invention, pulse-generating circuit comprises first triode, RC circuit, OR circuit and second triode.First triode has first collector/emitter, second collector/emitter and first base stage.First base stage is connected to trigger pip, first collector/grounded emitter.This first triode is in order to the reception trigger pip, and generation and the reverse reverse signal of trigger pip.The RC circuit is in order to receiving trigger pip, and trigger pip is postponed to produce inhibit signal behind a Preset Time.OR circuit is connected to the second collector/emitter and the RC circuit of first triode respectively, and in order to receive reverse signal and inhibit signal, union obtains clock signal.Second triode has the 3rd collector/emitter, the 4th collector/emitter and second base stage.Second base stage is connected to OR circuit, the 3rd collector/grounded emitter, and the 4th collector/emitter is connected to the clock end of latch.This second triode is in order to the receive clock signal, and clock signal is reverse, and produces the pulse signal in order to the MS_ID signal that latchs the central processing unit transmission.
According to the described central processing unit type recognition circuit of preferred embodiment of the present invention, control module is the system substrate controller module.
According to the described central processing unit type recognition circuit of preferred embodiment of the present invention, above-mentioned latch comprises the zero clearing unit, in order to when central processing unit is switched on, the data in the latch is carried out clear operation.
According to the described central processing unit type recognition circuit of preferred embodiment of the present invention, latch is 8 bit data/address latch.
The present invention reintroduces a kind of CPU type recognition methods, discern the type of the central processing unit of VID signal and the same pin of MS_ID signal common in order to control module, this CPU type recognition methods may further comprise the steps: at first, one trigger pip is provided, and central processing unit normally powers on, and wherein this trigger pip is normal working voltage signal or delayed normal working voltage signal.Secondly, produce in order to latch the pulse signal of the MS_ID signal that central processing unit sends according to trigger pip.Then, under the control of this pulse signal, latch the MS_ID signal that central processing unit sends.At last, control module is judged the type of central processing unit according to the MS_ID signal of the central processing unit transmission of latching.
According to the described CPU type recognition methods of preferred embodiment of the present invention, may further comprise the steps when producing pulse signal: at first, produce and the reverse reverse signal of trigger pip.Secondly, postpone to produce inhibit signal after a period of time by trigger pip.Then, reverse signal and inhibit signal are carried out exclusive disjunction and obtain clock signal.At last, clock signal is reverse, and the pulse signal of generation forward.
The present invention is because of having adopted central processing unit type recognition circuit, therefore can be when central processing unit adopts same pin to send VID signal and MS_ID signal, when powering on, system obtains and latchs the MS_ID signal, and offer the control chip that needs to determine CPU type in the system, with selective system mode of operation the most efficiently.
Description of drawings
Fig. 1 is the synoptic diagram of a MS_ID signal and a pin of VID signal common in the existing central processing unit;
Fig. 2 is a VID pin signal timing diagram;
Fig. 3 is a kind of central processing unit type recognition circuit structural drawing of the embodiment of the invention;
Fig. 4 is the another kind of central processing unit type recognition circuit circuit diagram of the embodiment of the invention;
Fig. 5 is that the pulse signal of the embodiment of the invention produces graph of a relation;
Fig. 6 is a kind of CPU type recognition methods process flow diagram of the embodiment of the invention;
Process flow diagram when Fig. 7 is the generation pulse signal of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing, specify the present invention.
See also Fig. 3, it is for the theory structure exemplary plot of a kind of central processing unit type recognition circuit of the present invention.
The central processing unit type recognition circuit 300 of present embodiment is connected to central processing unit 307.This central processing unit type recognition circuit 300 comprises pulse-generating circuit 301, latch 303 and control module 305.This central processing unit type recognition circuit 300 is in order to latch VID signal (central processing unit voltage identification signal) and MS_ID signal (Market Segment ID, signal for the system identification CPU type) the MS_ID signal of central processing unit 307 transmissions of shared same pin is for the type of control module 305 according to this MS_ID signal judgement central processing unit 307.
Wherein, pulse-generating circuit 301 receives trigger pip, and produces a pulse signal in order to the MS_ID signal that latchs central processing unit 307 transmissions.This trigger pip is generally represents central processing unit 307 energising normal VTT_PG signal (normal working voltage signal) or delayed VTT_PG signals.The MS_ID signal that latch 303 sends in order to the central processing unit 307 that takes out and latch VID signal and the same pin of MS_ID signal common, this latch 303 comprises clock end 309, input end 311 and output terminal 313.Clock end 309 is connected to the output of pulse-generating circuit 301, produces the pulse signal that circuit 301 produces in order to received pulse.Input end 311 is connected to central processing unit 307, in order to when clock end 309 receives pulse signal, receives the MS_ID signal that VID signal and the same pin of MS_ID signal common are sent.Latch 303 can be to be 8 bit data/address latch of 74LS273 as model.Control module 305 is connected to the output terminal 313 of latch 303, in order to obtaining the MS_ID signal of being deposited in the latch 303, and judges the type of central processing unit according to the MS_ID signal.Control module 305 can be system substrate controller (BMC), and the system substrate controller need be known the type of central processing unit when determining the mode of operation of system.When central processing unit 307 did not send the MS_ID signal, the same pin that central processing unit 307 is shared by VID signal and MS_ID signal sent the VID signal and uses VID signaling module 315 to use to other.
See also Fig. 4, it is for the exemplifying embodiment figure of a kind of central processing unit type recognition circuit of the present invention.
The central processing unit type recognition circuit 400 of present embodiment comprises pulse-generating circuit 301, latch 303 and system substrate controller 413.Latch 303 comprises the zero clearing unit, and it moves by pin 411 (being the pin CLR_N among Fig. 4).When central processing unit was switched on, the zero clearing unit received a reset signal (being the signal SSI_PGD_PS among Fig. 4), and the data in the latch 303 are carried out zero clearing.
Pulse-generating circuit 301 comprises first triode 401, RC circuit 403, OR circuit 405 and second triode 407, is used to produce a pulse signal.When central processing unit was switched on, pin 409 received delayed VTT_PG signal (being the PWRGD_CPU0_VTT_DELAY signal among Fig. 4).The base stage of first triode 401 is connected to pin 409, grounded emitter, and collector is connected to an input end of OR circuit 405.After first triode 407 receives delayed VTT_PG signal, produce the reverse signal (seeing also the signal Vout1 among Fig. 5) with delayed VTT_PG signals reverse, and this reverse signal is sent to OR circuit 405.RC circuit 403 is connected between another input end of pin 409 and OR circuit 405, after it receives delayed VTT_PG signal, by producing an inhibit signal (seeing also the signal Vout2 among Fig. 5) behind Preset Time of delayed VTT_PG signal delay, and this inhibit signal is sent to OR circuit 405.Wherein can not send the time (being the POC time period among Fig. 2) of MS_ID signal less than central processing unit time delay.RC circuit 403 is made up of resistance and electric capacity, and resistance string is connected between pin 409 and the OR circuit 405 in the present embodiment, and an end of electric capacity is connected to OR circuit 405, other end ground connection.The time size that RC circuit 403 postpones can decide by the value of selecting electric capacity and resistance for use.Two input ends of OR circuit 405 connect first triode 401 and RC circuit 403 respectively, and output terminal connects second triode 407.It receives the reverse signal of first triode, 407 transmissions and the inhibit signal that RC circuit 403 sends, and carries out exclusive disjunction according to reverse signal and inhibit signal, obtains a clock signal (seeing also the signal Vout among Fig. 5).The base stage of second triode 407 is connected to OR circuit 405, and collector is connected to latch 303, grounded emitter.Second triode 407 receives the clock signal of OR circuit 405 outputs, with clock signal oppositely after, produce in order to latching a MS_ID signal that central processing unit sends and a pulse signal of forward, and this pulse signal inputed in the latch 303.
Latch 303 reads and deposits the MS_ID signal by the pin 415 that is connected to central processing unit after receiving the pulse signal that pulse-generating circuit 301 sends.
See also Fig. 6, it is a kind of CPU type recognition methods process flow diagram of the embodiment of the invention.
The CPU type recognition methods of present embodiment, the MS_ID signal in order to the central processing unit that latchs VID signal and the same pin of MS_ID signal common sends may further comprise the steps:
S601: a trigger pip is provided, and the central processing unit normal power-up.This trigger pip is generally VTT_PG signal or delayed VTT_PG signal.
S603: produce pulse signal.Trigger pip is handled, and produced a pulse signal according to trigger pip.
S605: latch the MS_ID signal that this central processing unit sends.Can adopt latch herein,, and under the control of pulse signal, latch the MS_ID signal that central processing unit sends, be deposited with in the latch the pulse signal input latch.Latch can be 8 bit data/address latch, is latch of 74LS273 etc. as model.
S607: the type of judging central processing unit according to the MS_ID signal.This step is finished by the control module in the system, and as BMC etc., thereby its type control system that need know central processing unit turns round with preferably mode of operation.
Because MS_ID signal and pin of VID signal common, and only provide under the state of system's one start, therefore, present embodiment is under the state of system's one start, earlier the MS_ID signal is taken out and is deposited with in the latch, so that deliver to the control module that needs to determine CPU type.When determining the mode of operation of system, need know the type of central processing unit as BMC (system substrate controller).
See also Fig. 7, the process flow diagram when it is the generation pulse signal of the embodiment of the invention.
S701: produce and a reverse reverse signal of trigger pip;
S703: produce an inhibit signal after delay a period of time by trigger pip.
S705: reverse signal and inhibit signal are carried out exclusive disjunction obtain a clock signal.
S707: clock signal is reverse, and the pulse signal of generation forward.
Present embodiment latchs a kind of method of the pulse signal of MS_ID signal for generation, but does not therefore limit the present invention, can also use other method or circuit to produce in order to latch the pulse signal of MS_ID signal.
The present invention is because of having adopted central processing unit type recognition circuit, therefore can be when central processing unit adopts same pin to send VID signal and MS_ID signal, when powering on, system obtains and latchs the MS_ID signal, and offer the control module that needs to determine CPU type in the system, with selective system mode of operation the most efficiently.Therefore the invention solves other control module in the existing system and can not obtain the problem of MS_ID signal, more help the running of the every function of system.
More than disclosed only be several specific embodiment of the present invention, but the present invention is not limited thereto, any those skilled in the art can think variation, all should drop in protection scope of the present invention.
Claims (9)
1. a central processing unit type recognition circuit in order to the type of identification central processing unit voltage identification signal with a central processing unit of the same pin of signal common that supplies the system identification CPU type, is characterized in that, comprising:
One pulse-generating circuit, in order to receive a trigger pip, the pulse signal for the signal of system identification CPU type of generation in order to latch that this central processing unit sends, wherein this trigger pip is normal working voltage signal or delayed normal working voltage signal;
One latch, comprise input end, output terminal and clock end, its clock end connects the output of this pulse-generating circuit, its input end connects the central processing unit voltage identification signal of this central processing unit and the shared pin of the signal that supplies the system identification CPU type, in order to latch the signal for the system identification CPU type that this same pin of central processing unit voltage identification signal and the signal common that supplies the system identification CPU type sends under the control of this pulse signal; And
One control module is connected to the output terminal of this latch, in order to obtain the signal of this confession system identification CPU type through latching, to judge the type of this central processing unit.
2. central processing unit type recognition circuit as claimed in claim 1 is characterized in that, this pulse-generating circuit comprises:
One first triode, it has first collector/emitter, second collector/emitter and first base stage, first base stage is connected to this central processing unit, first collector/grounded emitter, this first triode is in order to receiving this trigger pip, and produces and the reverse reverse signal of this trigger pip;
One RC circuit is connected to this central processing unit, in order to receiving this trigger pip, and this trigger pip is postponed to produce an inhibit signal behind the Preset Time;
One OR circuit is connected to this second collector/emitter and this RC circuit of this first triode respectively, and in order to receive this reverse signal and this inhibit signal, union obtains a clock signal; And
One second triode, it has the 3rd collector/emitter, the 4th collector/emitter and second base stage, second base stage is connected to this OR circuit, the 3rd collector/grounded emitter, the 4th collector/emitter is connected to this clock end of this latch, this second triode is in order to receive this clock signal, and this clock signal is reverse, and produces this pulse signal in order to the signal that supplies the system identification CPU type that latchs this central processing unit transmission.
3. central processing unit type recognition circuit as claimed in claim 1 is characterized in that, this control module is the system substrate controller module.
4. central processing unit type recognition circuit as claimed in claim 1 is characterized in that, this latch comprises a zero clearing unit, uses so that the data in the latch are carried out clear operation.
5. central processing unit type recognition circuit as claimed in claim 1 is characterized in that, this latch is one 8 bit data/address latch.
6. CPU type recognition methods, in order to the type of control module identification central processing unit voltage identification signal with a central processing unit of the same pin of signal common that supplies the system identification CPU type, it is characterized in that, may further comprise the steps:
Provide a trigger pip, and this central processing unit powers on normally, wherein this trigger pip is normal working voltage signal or delayed normal working voltage signal;
Produce a pulse signal according to this trigger pip for the signal of system identification CPU type in order to latch that this central processing unit sends;
Under the control of this pulse signal, latch the signal that this central processing unit sends for the system identification CPU type; And
This control module reads the signal of this confession system identification CPU type that latchs, to judge the type of this central processing unit.
7. CPU type recognition methods as claimed in claim 6 is characterized in that, may further comprise the steps when producing this pulse signal:
Produce and the reverse reverse signal of this trigger pip;
Produce an inhibit signal by this trigger pip after delay a period of time;
This reverse signal and this inhibit signal are carried out exclusive disjunction obtain a clock signal; And
This clock signal is reverse, and this pulse signal of generation forward.
8. CPU type recognition methods as claimed in claim 6 is characterized in that, also is included in central processing unit when normally powering on, and in advance latched data is carried out clear operation.
9. CPU type recognition methods as claimed in claim 7 is characterized in that, wherein is not less than the duration that central processing unit sends the signal that supplies the system identification CPU type time delay of trigger pip.
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| CN2007101621019A CN101458639B (en) | 2007-12-11 | 2007-12-11 | Central processing unit type recognition circuit and central processing unit type identification method |
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| CN2007101621019A CN101458639B (en) | 2007-12-11 | 2007-12-11 | Central processing unit type recognition circuit and central processing unit type identification method |
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| CN101458639A CN101458639A (en) | 2009-06-17 |
| CN101458639B true CN101458639B (en) | 2010-12-01 |
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| CN103577372A (en) * | 2013-11-13 | 2014-02-12 | 曙光信息产业(北京)有限公司 | Method for achieving multiplexing of I/O pins in FPGA on basis of D latch |
| CN103810067A (en) * | 2014-02-27 | 2014-05-21 | 山东超越数控电子有限公司 | Recognizing and detecting method for domestic processor type of blade server |
| CN112083243B (en) * | 2020-08-25 | 2023-03-28 | 深圳市赛禾医疗技术有限公司 | Catheter type identification method and device, terminal equipment and readable storage medium |
| CN117368701B (en) * | 2023-12-07 | 2024-03-15 | 芯洲科技(北京)股份有限公司 | Pad detection circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5163145A (en) * | 1989-04-25 | 1992-11-10 | Dell Usa L.P. | Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory reference |
| CN2185959Y (en) * | 1993-08-04 | 1994-12-21 | 罗锰镍 | Quasi-synchronous pulse generator |
| US5551012A (en) * | 1991-04-22 | 1996-08-27 | Acer Incorporated | Single socket upgradeable computer motherboard with automatic detection and socket reconfiguration for inserted CPU chip |
| US5640536A (en) * | 1990-08-31 | 1997-06-17 | Ncr Corporation | Work station architecture with selectable CPU |
| US5790834A (en) * | 1992-08-31 | 1998-08-04 | Intel Corporation | Apparatus and method using an ID instruction to identify a computer microprocessor |
| US6581190B1 (en) * | 1999-11-30 | 2003-06-17 | International Business Machines Corporation | Methodology for classifying an IC or CPU version type via JTAG scan chain |
-
2007
- 2007-12-11 CN CN2007101621019A patent/CN101458639B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5163145A (en) * | 1989-04-25 | 1992-11-10 | Dell Usa L.P. | Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory reference |
| US5640536A (en) * | 1990-08-31 | 1997-06-17 | Ncr Corporation | Work station architecture with selectable CPU |
| US5551012A (en) * | 1991-04-22 | 1996-08-27 | Acer Incorporated | Single socket upgradeable computer motherboard with automatic detection and socket reconfiguration for inserted CPU chip |
| US5790834A (en) * | 1992-08-31 | 1998-08-04 | Intel Corporation | Apparatus and method using an ID instruction to identify a computer microprocessor |
| CN2185959Y (en) * | 1993-08-04 | 1994-12-21 | 罗锰镍 | Quasi-synchronous pulse generator |
| US6581190B1 (en) * | 1999-11-30 | 2003-06-17 | International Business Machines Corporation | Methodology for classifying an IC or CPU version type via JTAG scan chain |
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Inventor after: Li Xiangli Inventor after: Zhang Yan Inventor after: Li Linqing Inventor after: Hu Shaohui Inventor after: Liu Dandan Inventor before: Zhang Jieguang Inventor before: Liu Shihao |
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Effective date of registration: 20171010 Address after: The town of Mudanjiang Ning'an city in Heilongjiang province after the 1 Village No. 114 Co-patentee after: Zhang Yan Patentee after: Li Xiangli Co-patentee after: Li Linqing Co-patentee after: Hu Shaohui Co-patentee after: Liu Dandan Address before: Taipei City, Taiwan Chinese Shilin District Hougang Street No. 66 Patentee before: Inventec Corporation |
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