CN101471235B - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- CN101471235B CN101471235B CN2008101475375A CN200810147537A CN101471235B CN 101471235 B CN101471235 B CN 101471235B CN 2008101475375 A CN2008101475375 A CN 2008101475375A CN 200810147537 A CN200810147537 A CN 200810147537A CN 101471235 B CN101471235 B CN 101471235B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
A method for fabricating a semiconductor device includes forming a first mask pattern over an etch target layer, forming a second mask pattern over the etch target layer, forming spacers at sidewalls of the first mask pattern and the second mask pattern, and etching the etch target layer with an etching mask where the second mask pattern is removed. The method improves a profile of a pad pattern and critical dimension uniformity.
Description
Technical field
The present invention relates to use spacer patterns technology (SPT) to make the method for semiconductor device.
Background technology
Along with the integrated level increase of semiconductor device, the size and the pitch of the pattern of forming circuit reduce.In order in semiconductor device, to form fine pattern, various manufacturing equipments and method have been proposed.
Photo-mask process (being also referred to as optical lithography) is to be used for little manufacturing field so that optionally remove the operation of the part (or body of substrate) of film.This operation makes to use up geometrical pattern is transferred to photosensitizing chemical thing on the substrate (photoresist or abbreviate " photoresistance " as) from photomask.
According to Rayleigh equation, the size of the fine pattern in the semiconductor device is directly proportional with employed light wavelength in photo-mask process, and is inversely proportional to the size of employed lens in this operation.Therefore, in order to obtain fine pattern, reduced in this exposure process employed light wavelength or increased the size of lens.Yet these methods need be developed new manufacturing equipment, thereby cause difficulty in equipment control; And increase manufacturing cost thus.
In order to overcome the problems referred to above, proposed to use legacy equipment (rather than new manufacturing equipment) to form other method of the fine pattern with high integration.A kind of method is the double patterning technology, the exposure process that this technology implementation is following: promptly, use different masks that the photoresistance film is carried out double patterning with printed circuit pattern, and another kind of method is to use sept to obtain the spacer patterns technology (SPT) of fine pattern as etching mask.Below, will describe SPT in detail.
Fig. 1 a to Fig. 1 e is the cutaway view of SPT (specifically, being the method that is used to form the control grid of flash memory device) that conventional semiconductor devices is shown.Usually, flash memory device comprises unit strings (cell string) and the switching transistor that is connected with a plurality of (16 or 32) control grid, and this switching transistor is used to connect drain selection line (SSL) and the drain electrode selection wire (DSL) that is positioned at the unit strings two ends.
With reference to Fig. 1 a, on semiconductor substrate 100, form etching target layer 110, and on this etching target layer 110, form expendable film 120a.This etching target layer 110 has the depositional fabric that comprises polysilicon 110a and nitride film 110b.Expendable film 120a comprises positive tetraethyl orthosilicate (TEOS) oxidation film.The height of deposit thickness decision employed sept in this SPT of this expendable film 120a.
On this expendable film 120a, form hard mask layer 160, bottom antireflective coating (BARC) film 170 and the first photoresistance film.Yet, when implementing exposure process, because photoresistance film and the refringence between the formed hard mask in the bottom of this photoresistance film, and be difficult to be formed on the first meticulous photoresistance pattern defined in the mask.Therefore, use BARC film 170 to prevent because the photoresistance film and firmly the refringence between the mask cause this photoresistance film 180 light loss that is reflected bad.
Usually, in the semiconductor lithography operation, used anti-reflective film as the extinction photoresist thin layer that is used for stably forming fine circuitry.In this anti-reflective film, contact interface and light characteristic need have high-resolution photoresist and mate well with employed in conventional processes.Anti-reflective film is regulated the substrate reflectivity in the corresponding wavelength scope, to obtain not have the photoresistance pattern of standing wave (standing wave) and recess (notching).In addition, anti-reflective film improves the tack of critical dimension (CD) uniformity and photoresistance pattern and substrate.Therefore, anti-reflective film has important function in the DUV operation.Anti-reflective film is included on the photoresistance film formed reflection coating provided (TARC) film and the formed BARC film in the bottom of photoresistance film.The BARC film has been widely used in obtaining the fine circuitry pattern.
With reference to Fig. 1 a, use the first photoresistance pattern 180 as mask etching BARC film 170 and hard mask layer 160.Use the hard mask layer 160 of patterning to come etch sacrificial film 120a, to form sacrificial pattern 120.After forming this sacrificial pattern 120, remove the first photoresistance pattern 180, anti-reflective film 170 and hard mask layer 160.
With reference to Fig. 1 b, on the resulting structures that comprises sacrificial pattern 120, form layer of spacer material.Operation is eat-back in enforcement, to form sept 130 on the sidewall of this sacrificial pattern 120.This sept 130 comprises polysilicon and limits the control grid.
With reference to Fig. 1 c, implement the Wet-type etching operation, removing sacrificial pattern 120, thereby only keep sept 130.
With reference to Fig. 1 d, (and not in having the zone line that is formed at a plurality of control grids in the semiconductor substrate 100) is formed for the second photoresistance pattern 140 that the transistorized grid of switch is limited in outer peripheral areas.
The switching transistor that is connected with SSL and DSL in this outer peripheral areas is arranged on the two ends of unit strings usually.In exposure process, this switching transistor (rather than in the zone line formed control grid) may have defective and focus on (defective focus).When defocusing of this outer peripheral areas became more serious, the manufacturing allowance of the depth of focus (DOF) was not enough.In addition, the switching transistor that is used to connect selection wire SSL and DSL is relevant with the conducting of raceway groove, thereby needs the CD of accurate control position and the size of pattern.In addition, the size of switching transistor and selection wire (width) is greater than the size of control grid included in the unit strings, to such an extent as to be difficult to use sept 130 to form fine pattern.Therefore, in outer peripheral areas, need the second photoresistance pattern 140 that adds.
With reference to Fig. 1 e, use the sept 130 and the second photoresistance pattern 140 to come etching etching target layer 110, to form following etching target pattern 155a and 155b: the grid that this pattern 155a and 155b are used to limit a plurality of control grids and are arranged on the switching transistor at these unit strings two ends as mask.
Form the 3rd photoresistance pattern (not shown), so that the outward flange of the semiconductor substrate that is formed with etching target pattern 155a and 155b is exposed.The 3rd photoresistance pattern (not shown) is the cutting mask that is used for being segmented in the sept part in the line end zone that the deposition of layer of spacer material produces.Use the 3rd photoresistance pattern (not shown) to remove the part that is arranged on this line end place of etching target pattern 155a and 155b so that cut apart each bar line, and remove the 3rd photoresistance pattern (not shown) as mask.
In this SPT, when forming the pad type photoresistance pattern 140 that the transistorized grid of switch is limited, before forming this photoresistance pattern 140, form the BARC film, thereby prevent to damage this photoresistance pattern 140.Yet, owing to be pre-formed sept 130, thereby can not form the BARC film.Shown in Fig. 1 d, owing to can not form the BARC film when being formed with sept 130, photoresistance pattern 140 may have defective profile and other defective.
If when being formed with sept 130, deposit this anti-reflective film, can be in the outer peripheral areas that does not have sept 130 anti-reflective film be deposited as and has given thickness, but this anti-reflective film is not formed in the meticulous zone between the sept 130, has bigger thickness but be deposited as.In the case, deposit profile and the CD uniformity of this anti-reflective film to improve photoresistance pattern 140.Yet if forming pad type photoresistance pattern 140 after etching etching target layer 110, this method need together remove anti-reflective film with the photoresistance pattern 140 as mask.In addition, need to increase the thickness of this photoresistance pattern 140, thereby can not guarantee the operation allowance.
When use comprises as basic CF
4Etching gas when removing this anti-reflective film, can corrode sept 130 and reduce its height.Therefore, etching selectivity can be not enough when etching etching target layer 110.
As mentioned above, in the conventional method of making semiconductor device, when forming pad type photoresistance pattern 140, be difficult to apply anti-reflective film, this can be owing to reflection of light causes recess, make the photoresistance pattern generating defective that in outer peripheral areas, forms, produce the slag dirt in the narrow block between pattern, and owing to the tack reduction of pattern and substrate causes pattern to lift.
Summary of the invention
A kind of method of making semiconductor device that provides is provided various embodiment of the present invention, described method forms the pad pattern by applying anti-reflective film before being included in and adopting cell mask operation formation etching target pattern, to improve the profile and the CD uniformity of filling up pattern and to prevent that photoresistance pattern generating slag dirt and pattern from lifting, so that improve device property.
According to one embodiment of present invention, a kind of method of making semiconductor device comprises: form first mask pattern on etching target layer; On described etching target layer, form second mask pattern; Side-walls at described first mask pattern and described second mask pattern forms sept; And use the etching mask that has removed described second mask pattern to come the described etching target layer of etching.At this, the material of described second mask pattern and size are different from the material and the size of described first mask pattern.
Preferably, use described first mask pattern and formed sept is as the etching mask that is used to form the gate pattern of switching transistor on the sidewall of described first mask pattern, described switching transistor is connected to drain selection line and drain electrode selection wire at the two ends of unit strings.In addition, use formed sept conduct on the sidewall of described second mask pattern is used for forming in described unit strings the etching mask of a plurality of control gate patterns.
According to one embodiment of present invention, a kind of method of making semiconductor device comprises: be formed for forming the coarse mask pattern of gate pattern of switching transistor and the meticulous mask pattern that is used for forming in unit strings the control gate pattern continuously; And form sept in the side-walls of described coarse mask pattern and described meticulous mask pattern, to implement the STI operation.
According to one embodiment of present invention, a kind of method of making semiconductor device comprises: form etching target layer on semiconductor substrate; On the etching target layer of the edge that is arranged at described semiconductor substrate, form the pad pattern; On the resulting structures that comprises described pad pattern, form the expendable film of planarization; Under the situation of the described pad pattern of not etching, the described expendable film of etching is to form sacrificial pattern; Form sept in described sacrificial pattern and described pad pattern place; Remove described sacrificial pattern to keep described sept; And come the described etching target layer of etching as mask with described sept and pad pattern with described sept.
Description of drawings
Fig. 1 a to Fig. 1 e is the cutaway view that the conventional method of making semiconductor device is shown.
Fig. 2 a to Fig. 2 g is the cutaway view that illustrates according to the method for the manufacturing semiconductor device of the embodiment of the invention.
Embodiment
Fig. 2 a to Fig. 2 g is the cutaway view that illustrates according to the method for the manufacturing semiconductor device of the embodiment of the invention.In this embodiment, semiconductor device comprises unit strings and the switching transistor that is connected with a plurality of control grids, and this switching transistor is used to connect drain selection line (SSL) and the drain electrode selection wire (DSL) that is positioned at these unit strings two ends.
With reference to Fig. 2 a, on semiconductor substrate 200, form etching target layer 210.On this etching target layer 210, form a polysilicon layer 220a and a BARC film 250a.On a BARC film 250a, form the first photoresistance pattern 260a that limits the pad pattern.Etching target layer 210 has the depositional fabric that comprises polysilicon 210a and nitride film 210b.
With reference to Fig. 2 b, use the first photoresistance pattern 260a to come etching polysilicon layer 220a as mask, forming pad pattern 220, the grid that 220 pairs in this pattern is used to connect the switching transistor of SSL or DSL limits.To form operation by sept subsequently, on the sidewall of this pattern 220, form sept.Therefore, this pattern 220 forms the grid (that is, difference is the thickness of this sept) less than switching transistor.
After forming a BARC film 250a, implement exposure process, produce defective or recess to prevent the first photoresistance pattern 260a.That is to say, after forming the BARC film on the etching target layer, form the photoresistance pattern, reducing the reflectivity of this etching target layer, thereby prevent to fill up pattern generating defective and photoresistance pattern generating slag dirt and be lifted.
With reference to Fig. 2 c, implement cmp (CMP) operation, so that formed expendable film 230 on pattern 220 and etching target layer 210 is carried out planarization.
When expendable film 230 is deposited as when having given thickness, produce jumps by pattern 220.This jump may cause in operation subsequently and defocus, thereby makes a plurality of meticulous control gate pattern variation in the unit strings.Therefore, implement the CMP operation to eliminate this jump.
Form the hard mask 240 and the second anti-reflective film 250b on the expendable film 230 after planarization.This hard mask 240 comprises polysilicon, and this is because the etching selectivity of hard mask is not enough to use the photoresistance pattern etching to be positioned at the expendable film 230 of bottom.
On the second anti-reflective film 250b, be formed for limiting the second photoresistance pattern 260b of word line.
This second photoresistance pattern 260b forms line/apart from type.The ratio of line-spacing is 1: 3.
With reference to Fig. 2 d, use the second photoresistance pattern 260b to come etching second anti-reflective film 250b and hard mask 240 as mask.
Use the second photoresistance pattern 260b, the second anti-reflective film 250b and hard mask 240 to come etching bottom expendable film 230 as mask.
Because comprise the expendable film 230 of TEOS film have with as the different etching selectivity of the pattern 220 of polysilicon, so pattern 220 does not have etched but remains.
Shown in Fig. 2 c and Fig. 2 d, when forming the second photoresistance pattern 260b by exposure process, the second anti-reflective film 250b prevents to produce defective pattern by the refractive index difference of hard mask 240.
Remove the second photoresistance pattern 260b, the second anti-reflective film 250b and hard mask 240.
With reference to Fig. 2 e, deposition forms the polysilicon layer of material as sept on the resulting structures that comprises sacrificial pattern 230a and pattern 220.
Operation is eat-back in enforcement, till sacrificial pattern 230a exposes, to form sept 270 on the sidewall of this sacrificial pattern 230a and pattern 220.
This sept 270 forms on the sidewall of pattern 220, to increase the CD of this pattern 220, so that can form the gate pattern greater than this pattern 220.
With reference to Fig. 2 f, remove sacrificial pattern 230a, so that can be preserved in unit strings, forming the sept 270 of a plurality of control gate patterns.
Remove sacrificial pattern 230a by the wet etching that uses HF.Because repellence in this HF solution, can not be removed as the nitride film 210b of material below.The pattern 220 that etching selectivity is identical with the etching selectivity of sept 270 can not be removed yet.
With reference to Fig. 2 g, come etching etching target layer 210 as mask with the pattern 220 that is formed with sept 270 on sept 270 and the sidewall.Continuous nitride etching film 210b and polysilicon 210a.
Owing to the same material of pattern 220 meeting etchings belows, therefore the pattern 220 as mask comprises polysilicon, and this polysilicon is compared meeting with other material that is used as mask and improved etch uniformity.
Remove sept 270 and pattern 220, forming etching target pattern 215a and 215b, etching target pattern 215a and 215b limit the grid of a plurality of control gate patterns and the switching transistor that is used to be connected SSL or DSL.
Form the 3rd photoresistance pattern (not shown), so that the outward flange of the semiconductor substrate 200 with etching target pattern 215a and 215b is exposed.The 3rd photoresistance pattern (not shown) is the cutting mask, is used for cutting apart the sept part of the line end location that deposition process produced that is arranged on layer of spacer material.
Use the 3rd photoresistance pattern (not shown) removes etching target pattern 215 as mask a part that is arranged on the line end place cutting apart each bar line, and remove the 3rd photoresistance pattern (not shown).
In conventional method, at first form sept, this sept is the etching mask that is used to form meticulous gate pattern, be formed for forming the photoresistance pattern of coarse gate pattern then, in contrast to this, in an embodiment of the present invention, at first form polysilicon film, this polysilicon film is the etching mask that is used to form coarse gate pattern, is formed for forming the sept of meticulous gate pattern then.By the double exposure operation, can in semiconductor device, form the gate pattern that has different size separately, thereby reduce the complexity of operation.In addition, after forming the BARC film, implement each exposure process, thereby improve the accuracy that forms the photoresistance pattern that has different size separately.
As mentioned above, in method according to the manufacturing semiconductor device of the embodiment of the invention, before forming the etching target pattern by the cell mask operation, apply anti-reflective film to form the pad pattern, thereby improve the profile and the CD uniformity of pad pattern and prevent that photoresistance pattern generating slag dirt and pattern from lifting, to improve device property.
The above embodiment of the present invention is illustrative rather than restrictive.The various modes that substitute and be equal to all are feasible.The present invention is not limited to the type of deposition as herein described, etching, polishing and patterning step.The present invention also is not limited to the semiconductor device of any particular type.For instance, the present invention can be used for dynamic random access memory (DRAM) device or nonvolatile semiconductor memory member.Other that content of the present invention is done increases, deletes or revise to be conspicuous and to fall in the scope of appended claims.
The application requires the priority of korean patent application No.10-2007-0140859 that submitted on December 28th, 2007 and the korean patent application No.10-2008-49895 that submitted on May 28th, 2008, and the full content of above-mentioned korean patent application is incorporated this paper by reference into.
Claims (20)
1. method of making semiconductor device comprises:
On etching target layer, form first mask pattern;
On described etching target layer, form second mask pattern;
Form first sept and form second sept in the side-walls of described first mask pattern in the side-walls of described second mask pattern;
Remove described second mask pattern; And
Come the described etching target layer of etching with the etching mask that comprises first mask pattern, described first sept and described second sept.
2. method according to claim 1, wherein,
First sept that uses described first mask pattern and form in the side-walls of described first mask pattern is as the etching mask that is used to form the gate pattern of switching transistor, and described switching transistor is connected to drain selection line and drain electrode selection wire at the two ends of unit strings.
3. method according to claim 2, wherein,
Use is used for forming in described unit strings the etching mask of a plurality of control gate patterns in formed second sept conduct of the side-walls of described second mask pattern.
4. method according to claim 1, wherein,
Described first mask pattern comprises polysilicon film, and described second mask pattern comprises the TEOS film.
5. method according to claim 1, wherein,
Described first sept and described second sept comprise polysilicon film.
6. method according to claim 1, wherein,
The step that forms described first mask pattern comprises:
On described etching target layer, form polysilicon film;
On described polysilicon film, form anti-reflective film;
Make formed photoresistance film patterning on described anti-reflective film; And
Use described anti-reflective film of described photoresistance film etching and described polysilicon film.
7. method according to claim 1, wherein,
The step that forms described second mask pattern comprises:
On described etching target layer and described first mask pattern, form the TEOS film;
On described TEOS film, form anti-reflective film;
Make the photoresistance film patterning that on described anti-reflective film, forms; And
Use described anti-reflective film of described photoresistance film etching and described TEOS film.
8. method of making semiconductor device comprises:
Be formed for forming the coarse mask pattern of gate pattern of switching transistor and the meticulous mask pattern that is used for forming the control gate pattern continuously in unit strings; And
Side-walls at described coarse mask pattern and described meticulous mask pattern forms sept, to implement the SPT operation.
9. method according to claim 8, wherein,
The step that forms described coarse mask pattern and described meticulous mask pattern comprises:
On hard mask layer, form first anti-reflective film;
The coarse photoresistance pattern that use forms on described first anti-reflective film makes described hard mask layer patternization;
Form the expendable film that covers described hard mask layer, so that described expendable film planarization;
On described expendable film, form second anti-reflective film; And
The meticulous photoresistance pattern that use forms on described second anti-reflective film makes described expendable film patterning.
10. method according to claim 8, wherein,
Described coarse mask pattern has the etching selectivity identical with the etching selectivity of described sept, and described meticulous mask pattern has the etching selectivity different with the etching selectivity of described sept.
11. method according to claim 8, wherein,
The step of implementing described SPT operation comprises:
Side-walls at described coarse mask pattern and described meticulous mask pattern forms sept;
Remove described meticulous mask pattern; And
Use described sept and described coarse mask pattern to come the described etching target layer of etching.
12. a method of making semiconductor device comprises:
On semiconductor substrate, form etching target layer;
On the described etching target layer of the edge that is arranged at described semiconductor substrate, form the pad pattern;
On the resulting structures that comprises described pad pattern, form the expendable film of planarization;
Under the situation of the described pad pattern of not etching, the described expendable film of etching is to form sacrificial pattern;
Side-walls at described sacrificial pattern and described pad pattern forms sept;
Remove described sacrificial pattern to keep described sept; And
The pad pattern that uses described sept and have a described sept comes the described etching target layer of etching as mask.
13. method according to claim 12, wherein,
Described etching target layer has the depositional fabric that comprises polysilicon layer and nitride film.
14. method according to claim 12, wherein,
Described pad pattern is defined for the grid of drain selection line and is used to drain the grid of selection wire.
15. method according to claim 12, wherein,
When being formed for forming the photoresistance pattern of described pad pattern, use anti-reflective film.
16. method according to claim 12, wherein,
The critical dimension of described pad pattern forms the critical dimension less than target pattern.
17. method according to claim 12, wherein,
Described expendable film comprises the TEOS film.
18. method according to claim 12, wherein,
When being formed for forming the photoresistance pattern of described sacrificial pattern, use anti-reflective film.
19. method according to claim 13, wherein,
Come the described sacrificial pattern of etching by the Wet-type etching operation of using HF solution.
20. according to the method for claim 13, wherein,
Described sacrificial pattern forms line/apart from type, and the ratio of line-spacing is 1: 3.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070140859 | 2007-12-28 | ||
| KR10-2007-0140859 | 2007-12-28 | ||
| KR20070140859 | 2007-12-28 | ||
| KR1020080049895 | 2008-05-28 | ||
| KR10-2008-0049895 | 2008-05-28 | ||
| KR1020080049895A KR100966976B1 (en) | 2007-12-28 | 2008-05-28 | Method for fabricating semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101471235A CN101471235A (en) | 2009-07-01 |
| CN101471235B true CN101471235B (en) | 2011-02-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008101475375A Expired - Fee Related CN101471235B (en) | 2007-12-28 | 2008-08-20 | Method for fabricating semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP5122422B2 (en) |
| KR (1) | KR100966976B1 (en) |
| CN (1) | CN101471235B (en) |
| TW (1) | TWI404119B (en) |
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| US8685627B2 (en) | 2007-12-20 | 2014-04-01 | Hynix Semiconductor Inc. | Method for manufacturing a semiconductor device |
| KR101024712B1 (en) * | 2007-12-20 | 2011-03-24 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR101094486B1 (en) | 2010-07-09 | 2011-12-19 | 주식회사 하이닉스반도체 | Method of manufacturing patterns for a semiconductor device |
| FR2968122B1 (en) * | 2010-11-30 | 2012-12-07 | Commissariat Energie Atomique | IMPROVED PATTERN REALIZATION METHOD FROM LATERAL SPACER TRANSFER |
| JP6003571B2 (en) * | 2012-11-21 | 2016-10-05 | 大日本印刷株式会社 | Method for producing template for nanoimprint |
| KR102343859B1 (en) * | 2015-01-29 | 2021-12-28 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
| US10515818B2 (en) * | 2016-11-29 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor methods and devices |
| TWI776398B (en) * | 2020-04-23 | 2022-09-01 | 台灣積體電路製造股份有限公司 | Manufacturing method of mask |
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| US6955961B1 (en) * | 2004-05-27 | 2005-10-18 | Macronix International Co., Ltd. | Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution |
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| KR20060010921A (en) * | 2004-07-29 | 2006-02-03 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100571629B1 (en) * | 2004-08-31 | 2006-04-17 | 주식회사 하이닉스반도체 | Method for manufacturing in semiconductor device |
| US7115525B2 (en) * | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
| US7253118B2 (en) * | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
| JP4271243B2 (en) * | 2006-04-11 | 2009-06-03 | 株式会社東芝 | Method for forming integrated circuit pattern |
| JP4996155B2 (en) * | 2006-07-18 | 2012-08-08 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| US7790360B2 (en) * | 2007-03-05 | 2010-09-07 | Micron Technology, Inc. | Methods of forming multiple lines |
| KR101024712B1 (en) * | 2007-12-20 | 2011-03-24 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR100946080B1 (en) * | 2007-12-28 | 2010-03-10 | 주식회사 하이닉스반도체 | Method for forming a pattern of semiconductor device |
-
2008
- 2008-05-28 KR KR1020080049895A patent/KR100966976B1/en not_active IP Right Cessation
- 2008-08-06 TW TW097129757A patent/TWI404119B/en not_active IP Right Cessation
- 2008-08-20 CN CN2008101475375A patent/CN101471235B/en not_active Expired - Fee Related
- 2008-11-12 JP JP2008289705A patent/JP5122422B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6955961B1 (en) * | 2004-05-27 | 2005-10-18 | Macronix International Co., Ltd. | Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200929328A (en) | 2009-07-01 |
| KR100966976B1 (en) | 2010-06-30 |
| JP2009164581A (en) | 2009-07-23 |
| CN101471235A (en) | 2009-07-01 |
| TWI404119B (en) | 2013-08-01 |
| KR20090072920A (en) | 2009-07-02 |
| JP5122422B2 (en) | 2013-01-16 |
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