CN101483159B - Chip construction and process thereof, chip stacking construction and process thereof - Google Patents
Chip construction and process thereof, chip stacking construction and process thereof Download PDFInfo
- Publication number
- CN101483159B CN101483159B CN2008100017007A CN200810001700A CN101483159B CN 101483159 B CN101483159 B CN 101483159B CN 2008100017007 A CN2008100017007 A CN 2008100017007A CN 200810001700 A CN200810001700 A CN 200810001700A CN 101483159 B CN101483159 B CN 101483159B
- Authority
- CN
- China
- Prior art keywords
- chip
- basic unit
- layer
- conductive layer
- elastic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention discloses a chip structure and a stacking structure stacked by the chip structure, wherein the chip structure has a base layer and at least one elastic contact point. Moreover in order to re-arrange a plurality of bonding pads originally around the base layer as a specific layout, the chip structure also has a re-routing layer. The substrate has a first surface and a second surface. The elastic contact point is embedded in the base layer and protruded outside the first surface and the second surface of the base layer. The elastic contact point has an elastic projection and a conductive layer for cladding the elastic projection, and the conductive layer connects the re-routing layer. The two chip structures can be mutually connected through the elastic contact point or re-routing layer.
Description
Technical field
The invention relates to a kind of chip structure and technology thereof and chip stack structure and technology thereof, and particularly relevant for a kind of chip structure and technology and chip stack structure and technology thereof with elastic contact.
Background technology
In information-intensive society now, the user pursues high-speed, high-quality, polyfunctional electronic product.With regard to product appearance, the design of electronic product is to stride forward towards light, thin, short, little trend.In order to achieve the above object, recently develop and a kind of multi-core encapsulation module, just the chip with a plurality of difference in functionalitys or identical function is packaged on the same carrier (carrier) in the lump, and carrier for example is substrate or lead frame, and sees through carrier and external circuit electric connection.Therefore, multi-core encapsulation module has transmission speed faster, shorter transmission path and better electrical characteristic, and further dwindle the size and the area of chip-packaging structure, thereby make multicore sheet encapsulation technology be widely used in various electronic products in, and become following main product.
In addition, stacked package (stacked package) structure promptly is to utilize multicore sheet encapsulation technology that a plurality of chips or passive device are disposed on the same carrier in the mode of piling up.In known techniques, the mode of piling up mainly is that same position is made micro through hole on each chip, and cooperate the plating of high-aspect-ratio that electric conducting material is inserted in the micro through hole, the more chip-stacked micro through hole of each chip that makes is joined afterwards, to reach electrically conducting between the chip.
In addition, other has a kind of mode of piling up is at the other substrate with a plurality of electrodes that attaches of the stacked chips of multilayer, electrically conduct mutually between these electrodes, and each chip electrically conducts with an electrode respectively, reaches electrically conducting between the chip by this.In addition, the mode of piling up can also be that circuit is connected to the chip sides and the brilliant back of the body, and makes projection to electrically connect adjacent chip at brilliant back.Also having a kind of mode of piling up is that circuit is connected to chip sides, and finishes the electric connection of circuit connection and chip chamber in the side of stacked chips.
Summary of the invention
The present invention is about a kind of chip structure and technology thereof, and it has better simply technology, and can pile up and form the chip stack structure with high-reliability.
The present invention is in addition about by the formed chip stack structure of above-mentioned chip structure and technology and application.
For specifically describing content of the present invention, at this a kind of chip structure is proposed, it has basic unit and at least one elastic contact.Basic unit has first surface and second surface.Elastic contact embeds basic unit and protrudes in outside the first surface and second surface of basic unit.Elastic contact has elastic projection and the conductive layer that coats elastic projection.
For specifically describing content of the present invention, at this a kind of chip stack structure is proposed, it has a plurality of chip units that pile up mutually, and each chip unit has basic unit and at least one elastic contact.Basic unit has first surface and second surface.Elastic contact embeds basic unit and protrudes in outside the first surface and second surface of basic unit.Elastic contact has elastic projection and the conductive layer that coats elastic projection.Wherein, adjacent two chip units are bonded with each other by the elastic contact that it had.
For specifically describing content of the present invention, at this a kind of chip stack structure is proposed, it has a plurality of chip units that pile up mutually, and each chip unit has basic unit, layer and at least one elastic contact reroute.Basic unit has first surface and second surface.Elastic contact embeds basic unit and protrudes in outside the first surface and second surface of basic unit.Elastic contact has elastic projection and the conductive layer that coats elastic projection.The layer that reroutes is disposed on the first surface of basic unit and connects the conductive layer of elastic contact.Wherein, adjacent two chip units are bonded with each other by the elastic contact that it had or the layer that reroutes respectively.
For specifically describing content of the present invention, a kind of chip technology is proposed at this.At first, provide basic unit, and basic unit have first surface and second surface.Then, form at least one elastic contact, and elastic contact embeds basic unit and protrudes in outside the first surface and second surface of basic unit.Elastic contact comprises elastic projection and first conductive layer that coats elastic projection.
For specifically describing content of the present invention, a kind of technology of chip stack structure is proposed at this.At first, form a plurality of chip units, wherein the technology of each chip unit is as described below.At first, provide basic unit, basic unit has first surface and second surface.Then, form elastic contact at least, and elastic contact embeds basic unit and protrudes in outside the first surface and second surface of basic unit, and elastic contact comprises elastic projection and first conductive layer that coats elastic projection.At this moment, tentatively finish chip unit, and after this, the stacked chips unit also makes two adjacent chip units be bonded with each other by the elastic contact that it had, to form chip stack structure.
For specifically describing content of the present invention, a kind of technology of chip stack structure is proposed at this.At first, form a plurality of chip units, wherein the technology of each chip unit is as described below.At first, provide basic unit, basic unit has first surface and second surface.Then, on the first surface of basic unit, form the layer that reroutes.Then, form at least one elastic contact, and elastic contact embeds basic unit and protrudes in outside the first surface and second surface of basic unit, and elastic contact comprises elastic projection and first conductive layer that coats elastic projection.Wherein, first conductive layer connects the layer that reroutes.Tentatively finish chip unit this moment, and after this, the stacked chips unit also makes two adjacent chip units be bonded with each other by the elastic contact that it had or the layer that reroutes, to form chip stack structure.
In sum, because the elastic contact of chip structure of the present invention has elasticity, thereby the stress that on elastic contact, produced of available buffer chip stack structure, increase the reliability that adjacent two chips in the chip stack structure are bonded with each other.On the other hand, chip structure of the present invention need not form known micro through hole when making, and does not therefore need the electroplating technology of high-aspect-ratio, helps to simplify manufacture method and can reduce manufacturing cost.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the profile of the chip structure of one embodiment of the invention.
Fig. 2 A～Fig. 2 N illustrates the making flow process of chip structure of the present invention.
Fig. 3 is the profile of a kind of chip stack structure of the present invention.
Fig. 4 is the profile of another kind of chip stack structure of the present invention
Fig. 5 is the profile of another chip stack structure of the present invention.
The main element symbol description
100,200: chip structure
110: basic unit
112,114,122a: surface
120: elastic contact
122,522a: elastic projection
124,124a, 124a ', 124b, 522b: conductive layer
130: layer reroutes
140,524: dielectric layer
152: opening
300,400,500: chip stack structure
310,410,510,520: chip unit
526: the sensing medicine
C: Microvia
PR: photoresist layer
Embodiment
Fig. 1 is the profile of the chip structure of one embodiment of the invention.
Please refer to Fig. 1, chip structure 100 has a basic unit 110 and at least one elastic contact 120.Basic unit 110 has surface 112 and surface 114, and elastic contact 120 embeds basic units 110 and the surface 112 that protrudes in basic unit 110 and surface 114 outside.Basic unit 110 for example is integrated circuit (Integrated-Circuit, IC) chip.Elastic contact 120 has an elastic projection 122 and a conductive layer 124 that coats elastic projection 122.The material of elastic projection 122 for example is a macromolecular material, and the material of elastic projection 122 can be polyimides (polyimide, PI), dimethyl silicone polymer (Polydimethylsioxane, PDMS) or ABF film (Ajinomoto build-up film).The material of conductive layer 124 for example is copper, tin, palladium or titanium.
In present embodiment, for make originally be positioned at basic unit 110 around a plurality of weld pads (not illustrating) can specified arrangement, for example the mode of face array rearranges in basic unit 110, so chip structure 100 also can have the layer 130 that reroutes.The layer 130 that reroutes is disposed on the surface 112 of basic unit 110, and connects the conductive layer 124 of elastic contact 120.And a plurality of chip structures 100 can be stacked into a chip stack structure (not illustrating), and adjacent two chip structures 100 in this chip stack structure can be bonded with each other by the elastic contact 120 or the layer 130 that reroutes that chip structure 100 is had.In addition, in present embodiment, be the protection and the layer 130 that reroutes that insulate, so chip structure 100 also can have a dielectric layer 140.Dielectric layer 140 is disposed on the surface 112 of basic unit 110 and covers the layer 130 that reroutes.Dielectric layer 140 has an opening 142, to expose this elastic contact 120.The material of dielectric layer 140 for example is a macromolecular material, and the material of dielectric layer 140 can be polyimides, dimethyl silicone polymer or ABF film.In addition, based on technologic facility, dielectric layer 140 can use identical materials to make with elastic projection 122, forms and have identical materials.
In the application of reality, chip structure of the present invention also can be used as a biological chip, and wherein the material of conductive layer, dielectric layer and elastic projection is respectively biocompatible materials.The material of conductive layer for example is metal, oxide or the colloid that contains metal, and can different effects be arranged with the field of using.For example, when chip structure was biochip as therapeutic type, the material of conductive layer can be thermo electric materials such as paramagnetism nanometer ferrite, and when chip structure was biochip as detection type, the material of conductive layer can be the nm of gold colloid.In addition, chip structure of the present invention also can have a sensing medicine, and it is positioned at the conductive layer surface that dielectric layer exposes, with environment in test substance produce reaction.A kind of manufacture method that below will enumerate chip structure 100 is described further.
Fig. 2 A～Fig. 2 N illustrates the making flow process of chip structure of the present invention.
At first, please refer to Fig. 2 A, a basic unit 110 is provided.In addition, in present embodiment, for make originally be positioned at basic unit 110 around a plurality of weld pads (not illustrating) can specified arrangement, for example the mode of face array rearranges in basic unit 110, and therefore the layer 130 that reroutes also can be provided.Basic unit 110 has surface 112 and surface 114, and the layer 130 that reroutes is configurable on the surface 112 of basic unit 110.
Then, please refer to Fig. 2 B, on the surface 112 of basic unit 110, form a photoresist layer PR, to cover basic unit 110.Afterwards, in basic unit 110, form a Microvia C who runs through photoresist layer PR.In addition, Microvia C runs through photoresist layer PR simultaneously and reroutes layer 130.The method that forms photoresist layer PR for example is to attach photoresist dry film (dry film) or coating liquid photoresist.In addition, the method for formation Microvia C for example is laser drill or machine drilling.
Then, please refer to Fig. 2 C, on the surface of photoresist layer PR and the mode of the inner surface of Microvia C by for example sputter (sputtering) form a conductive layer 124a '.In addition, conductive layer 124a ' also can electrically connect with the layer 130 that reroutes.Afterwards, please refer to Fig. 2 D, thicken conductive layer 124a ', and shown in Fig. 2 E, form conductive layer 124a, remove photoresist layer PR by the photoresist method of stripping by the mode of for example electroplating.At this moment, the conductive layer 124a ' that is positioned on the photoresist layer PR also can be removed in the lump along with photoresist layer PR, and stays conductive layer 124a, and this is photoresist method of stripping (lift-off).Certainly, the present invention is not limited to this, just also can form conductive layer 124a by other suitable methods.
Afterwards, please refer to Fig. 2 F, form a dielectric layer 140 ' to cover Microvia C on the surface 112 of basic unit 110, the mode that wherein forms dielectric layer 140 ' for example is to provide a dielectric material in basic unit 110 by modes such as pressing or rotary coating.Then, please refer to Fig. 2 G, dielectric layer 140 ' is carried out patterning to form elastic projection 122.In addition; please refer to Fig. 2 K,, therefore dielectric layer 140 ' is carried out patterning except can forming elastic projection 122 for the protection and the layer 130 that reroutes that insulate; can also form a dielectric layer 140 that covers the layer 130 that reroutes, and dielectric layer 140 separates with elastic projection 122.If the material of above-mentioned dielectric layer 140 ' has photonasty, then can by for example expose, step such as development comes pattern dielectric layer 140 '.Certainly, also can select in other embodiments to come pattern dielectric layer 140 ' with laser drill or other suitable processing methods.
It should be noted that following step is applicable to Fig. 2 H～Fig. 2 J and Fig. 2 L～Fig. 2 N simultaneously.Please refer to Fig. 2 H and Fig. 2 L, on elastic projection 122 is exposed to surperficial 122a outside reroute layer 130 and the basic unit 110, form a conductive layer 124b, and conductive layer 124b is connected with conductive layer 124a and forms the conductive layer 124 of coating elastic projection 122.So, form the elastic contact 120 that is constituted by elastic projection 122 and the conductive layer 124 that coats elastic projection 122.Above-mentioned conductive layer 124b can adopt the existing processes technology to make.For example, can in basic unit 110, form a mask (as patterning photoresist layer) earlier, form conductive layer 124b with for example sputter or other film techniques in the specific region of basic unit 110 by mask again.
Then, please refer to Fig. 2 I and Fig. 2 M, basic unit 110 is carried out thinning make the surface 114 of basic unit 110 expose elastic contact 120, and the mode of thinning basic unit 110 for example is to grind basic unit 110.More common grinding technique is a cmp, it mainly is a kind of the auxiliary of grinding pad (Polishing Pad) collocation chemical assistant (Reagent) that utilize, with the dual processing action of chemical reaction and mechanical polishing, the mode that basic unit 110 is ground.
Afterwards, please refer to Fig. 2 J and Fig. 2 N, further remove part basic unit 110, elastic contact 120 is protruded in outside the surface 114 of basic unit 110, the method that wherein removes basic unit 110 for example be reactive ion-etching (Reactive Ion Etch, RIE) or other suitable technologies.
Below roughly finish the making of chip structure 100 and chip structure 200, chip structure 100,200 of the present invention is to make in the mode of the known micro through hole of Microvia C replacement when making elastic contact 120, therefore the electroplating technology that does not need high-aspect-ratio is so manufacture method is simple and easy and can reduce manufacturing cost.
Chip structure proposed by the invention can further pile up mutually, to form a stacked structure.Below will enumerate with a plurality of chip stack structures of the present invention and application thereof and describe.
Fig. 3 is the profile of a kind of chip stack structure of the present invention, and Fig. 4 is the profile of another kind of chip stack structure of the present invention.
Please refer to Fig. 3, chip stack structure 300 has a plurality of chip units 310 (being chip structure 100) that pile up mutually, and adjacent two chip units 310 are bonded with each other by the elastic contact 120 that it had.The method that elastic contact 120 is bonded with each other can be that first elastic contact 120 with adjacent two chip units 310 is combined contact mutually, then elastic contact 120 is carried out for example heating processes such as LASER HEATING, microwave or ultrasonic waves, make elastic contact 120 fusion and being bonded with each other slightly, to couple adjacent two chip units 310.Number that it should be noted that the chip unit 310 of chip stack structure 300 can adjust according to actual conditions.In the present embodiment for convenience of description, be that the chip stack structure 300 that is stacked into three chip units 310 is an example.In addition, please refer to Fig. 4, chip stack structure 400 is similar to chip stack structure 300, being in chip stack structure 400 of both difference has a plurality of chip units 410 (being chip structure 200) that pile up mutually, and adjacent two chip units 410 can be bonded with each other by the elastic contact 120 that it had or the layer 130 that reroutes.
From the above, adjacent two chip units 310 in the chip stack structure 300 can be bonded with each other by the elastic contact 120 that it had, and adjacent two chip units 410 in the chip stack structure 400 can be bonded with each other by the elastic contact 120 that it had or the layer 130 that reroutes.Wherein, because elastic contact 120 has elasticity, therefore can buffer chip stacked structure 300,400 the stress that is produced on the elastic contact 120 (for example be because of chip between or different thermal stress that produce of thermal coefficient of expansion between chip and the contact), and then increase the reliability that adjacent two chips in the chip stack structure 300,400 are bonded with each other.
In addition, chip stack structure proposed by the invention also can have other multiple uses, for example is as purposes such as biological therapy or biological sensings, below will do further introduction.It should be noted that following is to do explanation with the stacked structure similar to chip stack structure 300, certainly, in other embodiment, also can be as purposes such as biological therapy or biological sensings with the stacked structure similar to chip stack structure 400.
Fig. 5 is the profile of another chip stack structure of the present invention.
Please refer to Fig. 5, chip stack structure 500 is made of with chip unit 520 chip unit 510 that couples mutually, wherein chip unit 520 for example is mentioned biology sensing chip of previous embodiment or biological therapy chip, and chip unit 510 for example is the wireless transmission chip, with the transmission drive signal to chip unit 520 or receive sensing signal from chip unit 520.In addition, purposes in response to biological therapy or sensing, chip unit 510 can select for use biocompatible materials to make under preferable situation with the each several part member in the chip unit 520, and for example the elastic projection 522a of chip unit 520, conductive layer 522b and dielectric layer 524 etc. can be made by biocompatible materials respectively.Wherein, the material of conductive layer 522b for example is metal, oxide or the colloid that contains metal.
If chip stack structure 500 is the purposes as biological sensing, then chip unit 510 can be the wireless transmission chip, and chip unit 520 can be biology sensing chip, and the material of conductive layer 522b can be the nm of gold colloid.At this moment, conductive layer 522b on the elastic projection 522a of chip unit 520 can have a sensing medicine 526 with the sensing external substance, and can transmit sensing signal by chip unit 520 and give chip unit 510, again with the sensing signal of a receiver (not illustrating) receiving chip unit 510, to carry out the sensing signal analysis.Chip unit 510 can also transmit drive signal to chip unit 520, with control chip unit 520.
If chip stack structure 500 is purposes as biological therapy, then chip unit 510 can be the wireless transmission chip and chip unit 520 can be the biological therapy chip, and the material of conductive layer 522b can be thermo electric materials such as paramagnetism nanometer ferrite.At this moment, conductive layer 522b on the elastic projection 522a of chip unit 520 can have a sensing medicine 526, and when sensing medicine 526 detects specific material, for example during You Hai cell (not illustrating), can transmit signals by chip unit 520 and give chip unit 510, again with the signal of a receiver (not illustrating) receiving chip unit 510.At this moment, receiver can start one can produce the equipment (not illustrating) in magnetic field, can be affected by magnetic fields and generate heat and be arranged in the conductive layer 522b of the chip stack structure 500 in the magnetic field that equipment produced that can produce magnetic field, and then kill harmful cell.Chip unit 510 can also transmit drive signal to chip unit 520, with control chip unit 520.
In sum, because the elastic contact of chip structure of the present invention has elasticity, therefore, when adjacent two chip units in the chip stack structure of the present invention are bonded with each other by the elastic contact that it had or are bonded with each other with the layer that reroutes by elastic contact that it had, the stress that can be produced on elastic contact with the buffer chip stacked structure by elastic contact, and then increase the reliability that adjacent two chip units in the chip stack structure are bonded with each other.And compared to the production method of known formation micro through hole, chip structure of the present invention only need form Microvia when making elastic contact, and does not need to use the electroplating technology of high-aspect-ratio, so manufacture method is simple and easy and can reduce manufacturing cost.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, any person with usual knowledge in their respective areas, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (29)
1. chip structure comprises:
Basic unit has first surface and second surface;
At least one elastic contact embeds this basic unit and protrudes in outside this first surface and this second surface of this basic unit, and this at least one elastic contact comprises elastic projection and the conductive layer that coats this elastic projection.
2. chip structure as claimed in claim 1 also comprises the layer that reroutes, and is disposed on this first surface of this basic unit, and connects this conductive layer of this at least one elastic contact.
3. chip structure as claimed in claim 2 also comprises dielectric layer, is disposed on this first surface of this basic unit and covers this layer that reroutes, and this dielectric layer has opening, to expose this at least one elastic contact.
4. chip structure as claimed in claim 3 also comprises the sensing medicine, and it is positioned at this conductive layer surface that this dielectric layer exposes.
5. chip structure as claimed in claim 3, wherein the material of this dielectric layer comprises macromolecular material.
6. chip stack structure comprises:
The a plurality of chip units that pile up mutually, each chip unit comprises:
Basic unit has first surface and second surface; And
At least one elastic contact, embed this basic unit and protrude in outside this first surface and this second surface of this basic unit, this at least one elastic contact comprises elastic projection and the conductive layer that coats this elastic projection, and wherein adjacent two chip units are bonded with each other by this at least one elastic contact that it had.
7. chip stack structure as claimed in claim 6, wherein each chip unit also comprises the layer that reroutes, and is disposed on this first surface of this basic unit, and connects this conductive layer of this at least one elastic contact.
8. chip stack structure as claimed in claim 7, wherein each chip unit also comprises dielectric layer, is disposed on this first surface of this basic unit and covers this layer that reroutes, this dielectric layer has opening, to expose this at least one elastic contact.
9. chip stack structure as claimed in claim 8, wherein this chip unit is a biochip, and this biochip also comprises the sensing medicine, and it is positioned at this conductive layer surface that this dielectric layer exposes.
10. chip stack structure as claimed in claim 8, wherein the material of those dielectric layers comprises macromolecular material.
11. a chip stack structure comprises:
The a plurality of chip units that pile up mutually, each chip unit comprises:
Basic unit has first surface and second surface;
At least one elastic contact embeds this basic unit and protrudes in outside this first surface and this second surface of this basic unit, and this at least one elastic contact comprises elastic projection and the conductive layer that coats this elastic projection; And
The layer that reroutes is disposed on this first surface of this basic unit, and connects this conductive layer of this at least one elastic contact, and wherein adjacent two chip units are bonded with each other by this at least one elastic contact or those layers that reroutes that it had respectively.
12. chip stack structure as claimed in claim 11, wherein each chip unit also comprises dielectric layer, is disposed on this first surface of this basic unit and covers this layer that reroutes, and this dielectric layer has opening, to expose this at least one elastic contact.
13. chip stack structure as claimed in claim 12, wherein this chip unit is a biochip, and this biochip also comprises the sensing medicine, and it is positioned at this conductive layer surface that this dielectric layer exposes.
14. a chip technology comprises:
Basic unit is provided, and this basic unit has first surface and second surface;
Form at least one elastic contact, this at least one elastic contact embeds this basic unit and protrudes in outside this first surface and this second surface of this basic unit, and this at least one elastic contact comprises elastic projection and first conductive layer that coats this elastic projection.
15. chip technology as claimed in claim 14, the method that wherein forms this at least one elastic contact comprises:
A side that has this first surface in this basic unit forms Microvia;
Inner surface at this Microvia forms second conductive layer;
Form elastic projection, this elastic projection is arranged in this Microvia and protrudes in this first surface of this basic unit;
Be exposed at this elastic projection and form the 3rd conductive layer on the surface outside this first surface of this basic unit, wherein the 3rd conductive layer is connected with this second conductive layer and constitutes this first conductive layer that coats this elastic projection, to form this at least one elastic contact that is made of this elastic projection and this first conductive layer that coats this elastic projection; And
This basic unit is carried out thinning, so that this at least one elastic contact protrudes in outside this second surface of this basic unit.
16. chip technology as claimed in claim 15 before forming this Microvia, comprises also forming the layer that reroutes that wherein this Microvia runs through this layer that reroutes, and this layer that reroutes electrically connects with this second conductive layer.
17. chip technology as claimed in claim 16, the method that wherein forms this elastic projection comprises:
In this basic unit, form first dielectric layer, to cover this Microvia; And
This first dielectric layer is carried out patterning, to form this elastic projection.
18. chip technology as claimed in claim 17 is wherein carried out patterning to this first dielectric layer, has also formed second dielectric layer, and this second dielectric layer covers this layer that reroutes.
19. chip technology as claimed in claim 15, the method that wherein forms this elastic projection comprises:
In this basic unit, form first dielectric layer, to cover this Microvia; And
This first dielectric layer is carried out patterning, to form this elastic projection.
20. the technology of a chip stack structure comprises:
Form a plurality of chip units, the technology of each chip unit comprises:
Basic unit is provided, and this basic unit has first surface and second surface;
Form at least one elastic contact, this elastic contact embeds this basic unit and protrudes in outside this first surface and this second surface of this basic unit, and this at least one elastic contact comprises elastic projection and first conductive layer that coats this elastic projection; And
Pile up those chip units, two adjacent chip units are bonded with each other, by this at least one elastic contact that it had to form this chip stack structure.
21. the technology of chip stack structure as claimed in claim 20, the method that wherein forms this at least one elastic contact comprises:
A side that has this first surface in this basic unit forms Microvia;
Inner surface at this Microvia forms second conductive layer;
Form elastic projection, this elastic projection is arranged in this Microvia and protrudes in this first surface of this basic unit;
Be exposed at this elastic projection and form the 3rd conductive layer on the surface outside this first surface of this basic unit, wherein the 3rd conductive layer is connected with this second conductive layer and constitutes this first conductive layer that coats this elastic projection, to form this at least one elastic contact that is made of this elastic projection and this first conductive layer that coats this elastic projection; And
This basic unit is carried out thinning, so that this at least one elastic contact protrudes in outside this second surface of this basic unit.
22. the chip technology of stacked structure as claimed in claim 21 before forming this Microvia, comprises also forming the layer that reroutes that wherein this Microvia runs through this layer that reroutes, and this layer that reroutes electrically connects with this second conductive layer.
23. the technology of chip stack structure as claimed in claim 22, the method that wherein forms this elastic projection comprises:
In this basic unit, form first dielectric layer, to cover this Microvia; And
This first dielectric layer is carried out patterning, to form this elastic projection.
24. the technology of chip stack structure as claimed in claim 23 is wherein carried out patterning to this first dielectric layer, also comprise having formed second dielectric layer, and this second dielectric layer covers this layer that reroutes.
25. the technology of chip stack structure as claimed in claim 21, the method that wherein forms this elastic projection comprises:
In this basic unit, form first dielectric layer, to cover this Microvia; And
This first dielectric layer is carried out patterning, to form this elastic projection.
26. the technology of a chip stack structure comprises:
Form a plurality of chip units, the technology of each chip unit comprises:
Basic unit is provided, and this basic unit has first surface and second surface;
On this first surface of this basic unit, form the layer that reroutes;
Form at least one elastic contact, this at least one elastic contact embeds this basic unit and protrudes in outside this first surface and this second surface of this basic unit, this at least one elastic contact comprises elastic projection and first conductive layer that coats this elastic projection, and this first conductive layer connects this layer that reroutes; And
Pile up those chip units, two adjacent chip units are bonded with each other, by this at least one elastic contact or those layers that reroutes that it had to form this chip stack structure.
27. the technology of chip stack structure as claimed in claim 26, the method that wherein forms this at least one elastic contact comprises:
A side that has this first surface in this basic unit forms the Microvia that runs through this layer that reroutes;
Inner surface at this Microvia forms second conductive layer, and wherein this second conductive layer is connected with this layer that reroutes;
Form elastic projection, this elastic projection is arranged in this Microvia and protrudes in this first surface of this basic unit;
Be exposed at this elastic projection and form the 3rd conductive layer on the surface outside this first surface of this basic unit, wherein the 3rd conductive layer is connected with this second conductive layer and constitutes this first conductive layer that coats this elastic projection, to form this at least one elastic contact that is made of this elastic projection and this first conductive layer that coats this elastic projection; And
This basic unit is carried out thinning, so that this at least one elastic contact protrudes in outside this second surface of this basic unit.
28. the technology of chip stack structure as claimed in claim 27, the method that wherein forms this elastic projection comprises:
In this basic unit, form first dielectric layer, to cover this Microvia; And
This first dielectric layer is carried out patterning, to form this elastic projection.
29. the technology of chip stack structure as claimed in claim 28 is wherein carried out patterning to this first dielectric layer, also comprise having formed second dielectric layer, and this second dielectric layer covers this layer that reroutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100017007A CN101483159B (en) | 2008-01-10 | 2008-01-10 | Chip construction and process thereof, chip stacking construction and process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100017007A CN101483159B (en) | 2008-01-10 | 2008-01-10 | Chip construction and process thereof, chip stacking construction and process thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101483159A CN101483159A (en) | 2009-07-15 |
| CN101483159B true CN101483159B (en) | 2010-12-29 |
Family
ID=40880199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100017007A Expired - Fee Related CN101483159B (en) | 2008-01-10 | 2008-01-10 | Chip construction and process thereof, chip stacking construction and process thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101483159B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6235554B1 (en) * | 1995-11-27 | 2001-05-22 | Micron Technology, Inc. | Method for fabricating stackable chip scale semiconductor package |
| CN1625805A (en) * | 2002-02-06 | 2005-06-08 | 揖斐电株式会社 | Board for mounting semiconductor chip and manufacturing method and semiconductor module |
-
2008
- 2008-01-10 CN CN2008100017007A patent/CN101483159B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6235554B1 (en) * | 1995-11-27 | 2001-05-22 | Micron Technology, Inc. | Method for fabricating stackable chip scale semiconductor package |
| CN1625805A (en) * | 2002-02-06 | 2005-06-08 | 揖斐电株式会社 | Board for mounting semiconductor chip and manufacturing method and semiconductor module |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2005-26405A 2005.01.27 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101483159A (en) | 2009-07-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8093718B2 (en) | Chip structure and stacked structure of chips | |
| CN104102902B (en) | A kind of semiconductor fingerprint identification sensor and its manufacture method | |
| JP2004046832A (en) | Ic card, and its production method | |
| US7768795B2 (en) | Electronic circuit device, electronic device using the same, and method for manufacturing the same | |
| US6659356B2 (en) | Hybrid IC card | |
| FI112121B (en) | Smart sticker web, process for making it, process for making a carrier web, and component of a smart sticker on a smart sticker web | |
| JP2016504751A (en) | Embedding thin chips in polymers | |
| WO2009078810A1 (en) | Contact-less and dual interface inlays and methods for producing the same | |
| TW200812448A (en) | Flexible electronic assembly | |
| KR20000068559A (en) | Process for manufacturing semiconductor wafer, process for manufacturing semiconductor chip, and ic card | |
| JP2004310619A (en) | Method for manufacturing ic card | |
| JPH11195096A (en) | Non-contact electronic card and its production | |
| WO2007116677A1 (en) | Ic module, ic inlet and ic mounted body | |
| WO2009147547A1 (en) | Electronic device and method of manufacturing an electronic device | |
| CN101483159B (en) | Chip construction and process thereof, chip stacking construction and process thereof | |
| TWI278979B (en) | Chip package substrate and manufacturing method thereof | |
| CN208538860U (en) | A kind of flush type light sensation mould group | |
| CN111463189B (en) | Flexible device based on system-in-package and manufacturing method thereof | |
| CN111463187B (en) | Flexible device based on system-in-package and manufacturing method thereof | |
| JP2004334639A (en) | Ic card and manufacturing method thereof | |
| KR101037639B1 (en) | Rfid tag and manufacturing method thereof | |
| TW201143015A (en) | Semiconductor package structure | |
| JPH104122A (en) | Semiconductor device | |
| JP2022507119A (en) | Electronic module for chip card | |
| JP4236972B2 (en) | Combination type IC card and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101229 Termination date: 20190110 |