CN101506966B - 具有凹陷式栅极的动态随机存取存储器晶体管及其制作方法 - Google Patents

具有凹陷式栅极的动态随机存取存储器晶体管及其制作方法 Download PDF

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CN101506966B
CN101506966B CN2007800307677A CN200780030767A CN101506966B CN 101506966 B CN101506966 B CN 101506966B CN 2007800307677 A CN2007800307677 A CN 2007800307677A CN 200780030767 A CN200780030767 A CN 200780030767A CN 101506966 B CN101506966 B CN 101506966B
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戈登·A·哈勒
山·D·唐
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Micron Technology Inc
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Abstract

本发明揭示一种存储器阵列，其包含形成于半导体衬底(22)上的多个存储器单元(20)。所述存储器单元中的个别单元包含第一(24)及第二(26)场效应晶体管，其分别包括栅极(28/30)、沟道区及一对源极/漏极区。所述第一及第二场效应晶体管的栅极形成于所述衬底中的开口中且硬连线在一起。传导数据线形成于所述衬底中的开口中且硬连线到所述源极/漏极区中的两者。电荷存储装置硬连线到不同于源极/漏极区中的所述两者的至少一者。

Description

具有凹陷式栅极的动态随机存取存储器晶体管及其制作方法
技术领域
本发明涉及存储器阵列及制作存储器阵列的方法。
背景技术
存储器是一种类型的集成电路，且在计算机系统中用于存储数据。此通常在一个或一个以上个别存储器单元阵列中制作。所述存储器单元可以是易失性、半易失性或非易性存储器单元。非易失性存储器单元可存储数据达延长的时间周期，且在许多情况下包含计算机关闭时。非易失性存储器发生耗散，且因此需要被更新/重新写入，且在许多情况下包含每秒钟进行多次。
一种实例性易失性半导体存储器是动态随机存取存储器(DRAM)，其具有图1中所示的例示性现有技术DRAM单元。图1描绘个别/单个DRAM单元10，其包括场效应存取晶体管12及存储电容器14。场效应晶体管12包含一对源极/漏极区15、16及栅极17。源极/漏极区16被描绘为与存储电容器14连接，而源极/漏极区15与位线18电连接。栅极17通常呈细长字线的形式，以形成数个场效应晶体管的栅极，所述栅极形成一“行”。位线18通常与形成一“列”的场效应晶体管的多个源极/漏极区15连接，所述列通常大体上正交于栅极/字线行。在许多情况下，直接相邻的场效应晶体管对可共享与位线电连接的共用源极/漏极区15。
还建议了利用电容器的双晶体管DRAM单元，例如美国专利第6,818,937号中所揭示的单元。
虽然本发明的动机是解决上文所识别的问题，但其决不受此限制。本发明仅受未对本说明书做解释性或其它限定性参考的文字表达的所附权利要求书及根据等效原则限制。
发明内容
一种存储器阵列包含形成于半导体衬底(22)上的多个存储器单元(20)。所述存储器单元中的个别单元包含第一(24)及第二(26)场效应晶体管，其分别包括栅极(28/30)、沟道区及一对源极/漏极区。所述第一及第二场效应晶体管的栅极形成于所述衬底的开口中且硬连线在一起。传导数据线形成于所述衬底的开口中且硬连线到所述源极/漏极区中的两者。电荷存储装置硬连线到不同于源极/漏极区中的所述两者的至少一者。
一种制作存储器阵列的方法包括：在半导体装置内形成有源区域区与沟槽隔离区的交替线；将一系列跑道状沟槽蚀刻到所述有源区域区及所述沟槽隔离区中，所述跑道状沟槽大体上正交于所述有源区域区与所述沟槽隔离区的交替线；在所述沟槽内形成传导材料以相对于所述沟槽中的个别沟槽形成一对电连接的字线；在所述有源区域区内形成源极/漏极区，所述源极/漏极区横向地在所述沟槽内部/中间且横向地在所述沟槽外部；形成传导数据线，所述传导数据线与横向地接纳在所述沟槽外部的源极/漏极区电连接；及形成电荷存储装置，所述电荷存储装置与横向地接纳在所述沟槽内部/中间的源极/漏极区分别电连接。
附图说明
上文已参照下文附图描述了本发明优选实施例。
图1是现有技术DRAM单元的示意图。
图2是衬底片断的示意性透视剖面图及包括根据本发明各方面的存储器单元的局部示意图。
图3是根据本发明一方面的单个/个别存储器单元的示意图。
图4是包括例如图2中所描绘的存储器单元的衬底片断的展开示意性俯视平面图。
图5是沿图4中的线5-5截取的示意性截面图。
图6是沿图4中的线6-6截取的示意性截面图。
图7是根据本发明各方面的衬底片断的又一展开示意性俯视平面图。
具体实施方式
本发明各方面涵盖存储器阵列及制作存储器阵列的方法。存储器阵列构造可通过任何方法来制作，且不必一定受本文中所揭示制作存储器阵列的方法所限制。同样，制作存储器阵列的方法不必一定受本文中所揭示的存储器阵列构造所限制。
最初参照图2描述存储器阵列构造的例示性方面。在各种实施方案中，根据本发明制作的存储器阵列包括形成在半导体衬底上的多个存储器单元。在本文件的上下文中，术语“半导体衬底”或“半传导衬底”被定义为意指包括半传导材料的任何构造，所述半传导材料包含但不限于例如半传导晶片(单独或在其上包括其它材料的组合件中)及半传导材料层(单独或在包括其它材料的组合件中)的体半传导材料。术语“衬底”是指任何支撑结构，其中包含但不限于上文所描述的半传导衬底。例示性优选半导体衬底包含体半导体衬底，例如实例性体单晶硅。当然，本发明各方面还可用于绝缘体上半导体衬底及可在其内或其上制作可操作存储器阵列的任何其它衬底(不论是现有的还是待研发的)中。
所述存储器阵列将包括多个存储器单元，其中根据本发明各种实施方案的例示性个别存储器单元统一由图2中的参考编号20来指示。并非存储器阵列中的所有存储器单元都一定具有相同构造，但可包含且通常包含多个大致相同构造的个别存储器单元。无论如何且仅以实例的方式，图2描绘包括半传导材料23的半导体衬底22。半传导材料23可包括体半导体材料，例如已经以传导性增强杂质全面地或相对于较小隔离区及/或阱而合适地本底掺杂的体单晶硅。当然也预期其它半导体材料及衬底。仅以实例的方式，半传导材料23的例示性本底掺杂是适当剂量/浓度的p型掺杂，以便可在栅极激活时形成n型场效应晶体管的沟道区。
个别存储器单元20包含第一场效应晶体管24及第二场效应晶体管26。每一晶体管包括栅极、沟道区及一对源极/漏极区。例如，第一场效应晶体管24被描绘为包括栅极28且第二场效应晶体管26被描绘为包括栅极30。在所描绘的且为一个例示性优选实施例中，栅极28及30分别被接纳在形成于半导体衬底22的半传导材料23内开口29及31内。在一个实施方案中，开口29及31呈细长沟槽形式，且接纳在其内的半传导材料将形成多个存储器单元的字线/栅极。仅以实例的方式，开口29、31的例示性开口宽度及所描绘的相邻开口之间的间距优选地小于或等于500埃。来自半传导材料23的最外表面的所描绘沟槽开口29及31的例示性深度为从100埃到500埃。栅极28及30的例示性优选半导体材料是以传导性方式掺杂的半传导材料及/或金属。在此文件的上下文中，“金属”界定元素金属、元素金属的合金或混合物或传导金属化合物中的任一者。仅以实例的方式，栅极28及30的一种优选传导材料为氮化钛。
栅极电介质32被描绘为衬里开口29及31。任何合适的现有或待研发的电介质都是可用的，其中二氧化硅就是一个实例，且具有从30埃到80埃的例示性优选厚度范围。
第一场效应晶体管24包括一对源极/漏极区34及36，且第二场效应晶体管26包括一对源极/漏极区38及40。此可通过离子植入、扩散掺杂等及任何其它工艺(不论是现有的还是待研发的)中的任一者而形成。此类源极/漏极区36、36、38及40的例示性优选厚度小于或等于距离材料23外表面500埃。在所描绘的例示性优选实施例中，源极/漏极区对中的一者横向接纳于栅极28与30中间，且由第一及第二晶体管24及26共享。在所描绘的例示性实施例中，第一场效应晶体管24的源极/漏极区36及第二场效应晶体管26的源极/漏极区40组成同一源极/漏极区，且所述源极/漏极区由此第一及第二场效应晶体管共享。在一个实施方案中，且如图所示，对34/36的其它源极/漏极区34被横向地接纳在栅极28的外侧，且对38/40的其它源极/漏极区38被横向地接纳在栅极30的外侧。在所描绘的例示性优选实施例中，共享源极/漏极区36/40既被横向地接纳在栅极28与30中间，又被竖向地接纳在所述栅极外侧。进一步在所描绘的优选实施例中，其它源极/漏极区34及38中的每一者被竖向地接纳在栅极28及30外侧，且其中所描绘的源极/漏极区形成于体半传导材料23的一个优选实施方案中。然而，当然也预期其它构造，其中包含(仅以实例的方式)升高的源极/漏极。
第一场效应晶体管24包括沟道区42且第二场效应晶体管26包括沟道区44。组合地，且作为一个优选实施例，此在所描绘的截面中形成大体W形状。每一沟道区42、44包括至少一个衬底截面中的可切换电流路径46，所述电流路径在共享源极/漏极区36/40与相应的其它源极/漏极区34或38之间延伸。优选地，如图所示，每一电流路径46包括相互连接的第一与第二大致垂直段48及50。在所描绘的例示性实施例中，第一及第二大致垂直段48及50可分别被视为包括竖向内端部52，及接纳在第一大致垂直段48与第二大致垂直段50之间最接近竖向内端部52的互连段56。在所描绘的例示性实施方案中，互连段56相对于所描绘的一般衬底定向大致水平地定向。
图2示意性地描绘与源极/漏极区对34/36及源极/漏极区对38/40的其它源极/漏极区34、38中的每一者电连接的传导数据线60。在一个例示性优选实施例中，传导数据线60被竖向地接纳在栅极28及30的外侧。图2还示意性地描绘与共享源极/漏极区36/40电连接的电荷存储装置62。在所描绘的例示性优选实施例中，电荷存储装置62包括电容器。
图2示意性地描绘与其相应的源极/漏极区电连接的传导数据线60及电荷存储装置62，且此可以任何方式或在任何实施方案中发生。在一个优选方面中，电荷存储装置62被竖向地接纳在栅极28及30的外侧，且在一个优选方面中，传导数据线60被竖向地接纳在栅极28及30的外侧。进一步在一个优选及例示性方面中，电荷存储装置62被竖向地接纳在传导数据线60的外侧，例如在一个将在接续论述中加以例示的优选实施方案中。进一步在一个优选实施例中，个别存储器单元20包括DRAM单元，其中传导数据线60包括位线。
在一个优选实施方案中，传导性材料分别使第一及第二晶体管24及26的栅极28与30电互连。例如，图2示意性地描绘电连接传导性栅极28与30的传导性材料区或段64。在一个例示性实施方案中，与栅极28及30互连的传导性材料64被接纳在已形成于半导体衬底22内的沟槽内，且更优选地被接纳在半导体衬底22的半传导材料23内。为清晰起见，材料23及(很有可能)外围绝缘材料32没有在图2中所描绘的示意性透视剖面图中显示为最接近传导材料64。
本发明的一个方面包含存储器阵列，所述存储器阵列包括形成于半导体衬底上的多个存储器单元。所述存储器单元中的个别存储器单元包括第一及第二场效应晶体管，其分别包括栅极、沟道区及一对源极/漏极区。第一及第二场效应晶体管的栅极硬连线在一起。传导数据线硬连线到所述源极/漏极区中的两者，且电荷存储装置硬连线到不同于源极/漏极区中的所述两者的至少一者。例如，且仅以实例的方式，图2示意性地描绘这一存储器阵列的个别存储器单元的例示性优选构造，且图3示意性地描绘这一例示性个别存储器单元。
在此方面的一个优选实施方案中，所述源极/漏极区中的一者被横向地接纳在所述栅极之间。在一个优选实施方案中，所述源极/漏极区中的一者由所述第一及第二场效应晶体管共享，且在一个优选方面中，电荷存储装置连接到所述一个共享源极/漏极区。在此方面的一个优选实施方案中，所述栅极由接纳在至少一个沟槽中的传导材料硬连线在一起，所述沟槽形成在半导体衬底的半传导材料内且在所述栅极之间延伸。然而，还预期电互连栅极的其它方面，例如通过单独的互连线或层，或通过任何其它方式(不论是现有的还是待研发的)且针对本发明揭示内容的任何方面电互连。在一个优选实施方案中，每一沟道区包括在至少一个截面中的电流路径，所述电流路径在包括互连的第一与第二大致垂直段的源极/漏极区之间延伸。还预期首先描述的图2实施例的任何其它例示性属性。
仅以实例的方式，图4-6针对图2的构造描绘并入传导数据线及电荷存储装置结构的例示性额外构造。与图2相同的编号被用在适当处，其中额外结构用额外编号来指示。绝缘盖70被接纳在传导栅极28、30上方。一种例示性优选材料是氮化硅。已在半传导材料23外侧竖向形成层间电介质72。一种例示性材料是二氧化硅，其可以是经掺杂的或未经掺杂的。已穿过所述材料形成传导数据线触点开口74直到源极/漏极区34及38。已沉积及图案化传导材料75以形成传导数据线60。仅以实例的方式，此可通过类镶嵌工艺或通过沉积及减成图案化及蚀刻工艺而形成。一个例示性优选方法包含沉积一种或一种以上传导材料75，随后对其进行图案化及减成蚀刻。可在图案化材料75之前或之后在其上方沉积绝缘材料76，且沉积并随后各向异性蚀刻相同或不同绝缘材料76以形成绝缘传导数据线侧壁间隔层(未显示)。蚀刻以形成数据线60可如图5截面中所描绘有效地使材料75凹陷到触点开口74内，且其中一些绝缘间隔层形成材料76随后在其中沉积在图5截面中的材料75上方。
已沉积另一层间介电层78(图5)。例示性优选材料包含经掺杂或未经掺杂的二氧化硅。已穿过层间介电层78及72蚀刻触点开口80直到共享源极/漏极区36/40。传导性填塞材料81接纳在其中。电荷存储装置62被描绘为包括电容器，所述电容器具有与接纳在触点开口80内的传导插头81电连接的存储节点电极82。电容器电介质84接纳在存储节点电极82外侧及上方，且其上方已形成外部传导单元板电极86。当然，预期任何例示性或待研发材料来用于电容器电介质84及传导性电容器电极82及86。
所描绘的图2及图4-6构造是个别存储器单元及根据本发明各方面的存储器阵列的例示性描绘。所属技术领域的技术人员将容易地了解，此可以众多方式(不论是现有的还是待研发的)中的任一者来制造。仅以实例的方式，参照图7描述制作存储器阵列的方法的例示性发明方面。图7是包括(仅以实例的方式)存储器阵列区域100的半导体衬底的俯视图。交替的有源区域区的线101与沟槽隔离区的线102已形成于合适的半导体衬底内，例如首先描述的实施例的衬底22。已将一系列跑道状沟槽104蚀刻到有源区域区101及沟槽隔离区102中，所述跑道状沟槽大体上正交于有源区域区101与沟槽隔离区102的交替线。仅以实例的方式，此可呈图2的开口29及31的形式以制作个别存储器单元。传导材料形成于跑道状沟槽104内以相对于个别的跑道状沟槽形成一对电连接的字线。例示性优选材料是上文针对栅极28及30描述的材料。因此，且同样在一个例示性优选实施例中，将形成栅极电介质(为清晰起见未在图7中显示)以在提供栅极材料28/30之前为例示性所描绘跑道状沟槽104加衬。
源极/漏极区可横向地在跑道状沟槽104内部且横向地在跑道状沟槽104外部的有源区域区内形成。仅以实例的方式，且参照图2实施例，在图7中，例示性的此横向内部源极/漏极区以36/40来指明，且例示性的此类横向外部源极/漏极区以34及38来指明。
形成传导数据线(为清晰起见未在图7中显示)以与横向地接纳在跑道状沟槽外部的源极/漏极区电连接，例如电连接到例示性的图2及4-6实施例的源极/漏极区34及38。形成电荷存储装置(为清晰起见未在图7中显示)以与横向地接纳在跑道状沟槽104的内部的源极/漏极区分别电连接。例如，且仅以实例的方式，电容器或其它装置可相对于图2及4-6实施例的源极/漏极区36/40而形成。仅以实例的方式显示例示性单独的传导触点110，其被接纳在存储器阵列100外部以用于相对于传导材料(即，针对每一沟槽104的传导材料28及30)进行电连接以用于存取/激活每一字/栅极线对。
本发明一方面涵盖一种制作存储器阵列的方法，所述方法包括在半导体衬底内形成有源区域区与沟槽隔离区的交替线。在图7中且仅以实例的方式描绘例示性的此类交替线。将一系列沟槽对蚀刻到有源区域区及沟槽隔离区中，所述沟槽对大体上正交于有源区域区与沟槽隔离区的交替线。仅以实例的方式，图7中的例示性的所描绘沟槽开口29及31是例示性的此类系列的沟槽对，且与是否形成跑道状沟槽无关。
无论如何，在一个实施方案中，将至少一个互连沟槽蚀刻在与每一对沟槽中的个别沟槽互连的半导体衬底内某处。例如，且仅以实例的方式，例示性的所描绘半圆/拱形沟槽区段112中的每一者是使相应的沟槽对29及31互连的例示性的此互连沟槽。仅可制作此类沟槽112中的一者，或可蚀刻交替形状或配置的沟槽。此外，可同时且/或使用共同遮蔽步骤来蚀刻例示性沟槽对，或针对遮蔽步骤及/或蚀刻单独地蚀刻。
在沟槽对及互连沟槽内形成传导材料以相对于所述沟槽对中的个别沟槽形成一对电连接的字线。此可包括在所述沟槽对及互连沟槽内同时地或在不同时间完全地沉积至少一些传导材料。(图2中的互连材料/区64对应于此互连沟槽及传导材料。)
源极/漏极区形成于有源区域区内每一对沟槽的个别沟槽中间，且横向地位于每一对沟槽的个别沟槽的外部。形成传导数据线以与横向地接纳在每一对沟槽中的个别沟槽外部的源极/漏极区电连接。形成电荷存储装置以与接纳在每一对沟槽中的个别沟槽中间的源极/漏极区分别电连接。仅以实例的方式，参照图2及图4-6的实施例对此进行描绘。
上文描述的例示性的图2、图4-6及图7实施例可通过若干现有或待研发技术中的任一者来制造。进一步仅以实例的方式，可将图2、4-6及7中所描绘的沟槽开口29、31制造为亚平版印刷式。例如，且仅以实例的方式，可在第一硬遮蔽层中将沟槽开口轮廓制作成尽可能小的平版印刷特征大小。此后，可在其上方沉积额外的合适薄度的硬遮蔽材料以为在第一硬遮蔽层中形成的沟槽的侧壁及基底加衬。此可经受各向异性类间隔层蚀刻，借此减小向衬底材料23中蚀刻沟槽开口29及31之前沟槽的开口宽度，且借此形成将为亚平版印刷式的所描绘沟槽。此外，还可通过利用沉积到小于此时存在的最小光刻特征尺寸的横向厚度的经各向异性蚀刻的硬掩模间隔层来以类似方式将沟槽之间的硬遮蔽块制作为亚平版印刷式。
此外，且无论如何，可在形成沟槽开口29、31之前沉积外围电路栅极材料，然后在图案化所述外围栅极材料之前穿过阵列区域内的外围电路栅极材料形成沟槽开口29、31以在外围电路区域中形成场效应晶体管栅极。此外，且仅以实例的方式，可在从所述阵列中移除外围栅极材料之前相对于所述阵列内的外围传导栅极材料沉积及图案化回例示性的所描述门电介质32及门材料28、30。此外，且仅以实例的方式，例示性的所描绘的将传导门材料28、30凹陷到存储器阵列内可与外围栅极材料的蚀刻相当地发生。此外，且仅以实例的方式，形成于传导栅极材料28、30上方的绝缘材料70可与针对外围栅极构造形成的绝缘间隔层的制作相当地形成且与其具有相同材料。当然，预期关于制作本文中所识别及请求的结构中的任一者的任何其它现有的或待研发的处理，且与本文中所请求及描述的存储器阵列的制作方法相结合。

Claims (50)

1.一种存储器阵列，其包括：
多个存储器单元，其形成于半导体衬底上，所述存储器单元中的个别单元包括：
第一及第二场效应晶体管，其分别包括栅极、沟道区及一对源极/漏极区；所述栅极被接纳在形成于所述衬底的半传导材料内的开口内，所述源极/漏极区对中的一者被横向地接纳在所述栅极中间并由所述第一及第二晶体管共享，所述第一及第二晶体管的所述源极/漏极区对中的另一者中的每一者被横向地接纳在其相应栅极的外侧；
传导数据线，其被竖向地接纳在所述栅极的外侧且与所述源极/漏极区对中的另一者中的每一者电连接；及
电荷存储装置，其与所述共享源极/漏极区电连接。
2.如权利要求1所述的存储器阵列，其中所述半传导材料包括体半导体材料。
3.如权利要求2所述的存储器阵列，其中所述体半导体材料包括体单晶硅。
4.如权利要求1所述的存储器阵列，其中所述源极/漏极区对中的所述一者被竖向地接纳在所述栅极的外侧。
5.如权利要求1所述的存储器阵列，其中所述源极/漏极区对的另一者中的每一者被竖向地接纳在所述栅极的外侧。
6.如权利要求1所述的存储器阵列，其中所述源极/漏极区对中的所述一者及所述源极/漏极区对中的另一者中的每一者被竖向地接纳在所述栅极的外侧。
7.如权利要求1所述的存储器阵列，其中所述电荷存储装置被竖向地接纳在所述栅极的外侧。
8.如权利要求1所述的存储器阵列，其中所述电荷存储装置被竖向地接纳在所述栅极的外侧且竖向地接纳在所述传导数据线的外侧。
9.如权利要求1所述的存储器阵列，其中每一沟道区包括在至少一个截面中的电流路径，所述电流路径在所述共享源极/漏极区与包括经互连的第一与第二大致垂直段的相应的另一源极/漏极区之间延伸。
10.如权利要求1所述的存储器阵列，其包括使所述第一与第二晶体管的所述栅极电互连的传导材料。
11.如权利要求10所述的存储器阵列，其中所述传导材料被接纳在形成于所述半导体衬底内的沟槽内。
12.如权利要求10所述的存储器阵列，其中所述传导材料被接纳在形成于所述半导体衬底的所述半传导材料内的沟槽内。
13.如权利要求1所述的存储器阵列，其中，
每一沟道区包括在至少一个截面中的电流路径，所述电路流径在所述共享源极/漏极区与包括经互连的第一与第二大致垂直段的所述相应的另一源极/漏极区之间延伸；且
传导材料使所述第一与第二晶体管的所述栅极电互连。
14.如权利要求1所述的存储器阵列，其中所述存储器阵列包括DRAM单元。
15.一种存储器阵列，其包括：
多个存储器单元，其形成于半导体衬底上，所述存储器单元中的个别单元包括：
第一及第二场效应晶体管，其分别包括栅极、沟道区及一对源极/漏极区；所述源极/漏极区对中的一者被横向地接纳在所述栅极中间并由所述第一及第二晶体管共享，所述第一及第二晶体管的所述源极/漏极区对中的另一者中的每一者被横向地接纳在其相应栅极的外侧，每一沟道区包括在至少一个截面中的电流路径，所述电路流径在所述共享源极/漏极区与包括经互连的第一与第二大致垂直段的相应的另一源极/漏极区之间延伸；传导数据线，其与所述源极/漏极区对中的另一者中的每一者电连接；及
电荷存储装置，其与所述共享源极/漏极区电连接。
16.如权利要求15所述的存储器阵列，其中所述第一及第二大致垂直段包括竖向内端部，在所述一个截面中的所述电流路径包括被接纳在最接近所述竖向内端部的所述第一与第二大致垂直段之间的互连段。
17.如权利要求15所述的存储器阵列，其中在所述一个截面中的所述电流路径包括接纳在所述第一与第二大致垂直段之间的互连的大致水平段。
18.如权利要求15所述的存储器阵列，其中所述传导数据线被竖向地接纳在所述栅极的外侧。
19.如权利要求15所述的存储器阵列，其中所述电荷存储装置被竖向地接纳在所述栅极的外侧。
20.如权利要求15所述的存储器阵列，其中所述电荷存储装置被竖向地接纳在所述栅极的外侧且被竖向地接纳在所述传导数据线的外侧。
21.如权利要求15所述的存储器阵列，其包括使所述第一与第二晶体管的所述栅极电互连的传导材料。
22.如权利要求15所述的存储器阵列，其中所述传导数据线包括位线，且所述存储器单元包括DRAM单元。
23.一种存储器阵列，其包括：
多个存储器单元，其形成于半导体衬底上，所述存储器单元中的个别单元包括：
第一及第二场效应晶体管，其分别包括栅极、沟道区及一对源极/漏极区；所述源极/漏极区对中的一者被横向地接纳在所述栅极中间并由所述第一及第二晶体管共享，所述第一及第二晶体管的所述源极/漏极区对中的另一者中的每一者被横向地接纳在其相应栅极的外侧，传导材料使所述第一与第二晶体管的所述栅极电互连；
传导数据线，其与所述源极/漏极区对中的另一者中的每一者电连接；及
电荷存储装置，其与所述共享源极/漏极区电连接。
24.如权利要求23所述的存储器阵列，其中所述传导材料被接纳在形成于所述半导体衬底内的沟槽内。
25.如权利要求23所述的存储器阵列，其中所述传导材料被接纳在形成于所述半导体衬底的半传导材料内的沟槽内。
26.如权利要求23所述的存储器阵列，其中所述传导数据线被竖向地接纳在所述栅极的外侧。
27.如权利要求23所述的存储器阵列，其中所述电荷存储装置被竖向地接纳在所述栅极的外侧。
28.如权利要求23所述的存储器阵列，其中所述电荷存储装置被竖向地接纳在所述栅极的外侧且被竖向地接纳在所述传导数据线的外侧。
29.如权利要求23所述的存储器阵列，其中所述电荷存储装置包括电容器。
30.一种存储器阵列，其包括：
多个存储器单元，其形成于体半导体衬底上，所述存储器单元中的个别单元包括：
第一及第二场效应晶体管，其分别包括栅极、沟道区及一对源极/漏极区；所述栅极被接纳在形成于所述衬底的体半传导材料内的沟槽内，所述源极/漏极区对中的一者被横向地接纳在体半传导材料内所述栅极中间并由所述第一及第二晶体管共享，所述第一及第二晶体管的所述源极/漏极区对中的另一者中的每一者被接纳在体半传导材料内且被横向地接纳在其相应栅极的外侧，传导材料使所述第一与第二晶体管的所述栅极电互连，每一沟道区包括在至少一个截面中的体半传导材料内的电流路径，所述电路流径在所述共享源极/漏极区与包括经互连的第一与第二大致垂直段的相应的另一源极/漏极区之间延伸；
传导数据线，其被竖向地接纳在所述栅极的外侧且与所述源极/漏极区对中的另一者中的每一者电连接；及
电荷存储装置，其与所述共享源极/漏极区电连接且被竖向地接纳在所述传导数据线的外侧。
31.如权利要求30所述的存储器阵列，其中所述传导材料包括金属。
32.如权利要求31所述的存储器阵列，其中所述金属包括TiN。
33.一种存储器阵列，其包括：
多个存储器单元，其形成于半导体衬底上，所述存储器单元中的个别单元包括：
第一及第二场效应晶体管，其分别包括栅极、沟道区及一对源极/漏极区；所述第一及第二场效应晶体管的所述栅极硬连线在一起，所述第一场效应晶体管的所述一对源极/漏极区中的一者及所述第二场效应晶体管的所述一对源极/漏极区中的一者由所述第一及第二场效应晶体管共享；
传导数据线，其硬连线到不同于所述一个源极/漏极区的所述源极/漏极区中的两个且电连接所述两个源极/漏极区；及
电荷存储装置，其硬连线到所述一个源极/漏极区。
34.如权利要求33所述的存储器阵列，其中所述一个源极/漏极区被横向地接纳在所述第一场效应晶体管的所述栅极与所述第二场效应晶体管的所述栅极之间。
35.如权利要求33所述的存储器阵列，其中所述栅极由接纳在形成于所述半导体衬底的半传导材料内的至少一个沟槽中且在所述栅极之间延伸的传导材料硬连线在一起。
36.如权利要求33所述的存储器阵列，其中所述栅极由接纳在形成于所述半导体衬底的半传导材料内的至少两个沟槽中且在所述栅极之间延伸的半导体材料硬连线在一起。
37.如权利要求33所述的存储器阵列，其中所述电荷存储装置被竖向地接纳在所述栅极的外侧。
38.如权利要求33所述的存储器阵列，其中所述传导数据线被竖向地接纳在所述栅极的外侧。
39.如权利要求33所述的存储器阵列，其中每一沟道区包括在至少一个截面中的电流路径，所述电流路径在包括经互连的第一与第二大致垂直段的源极/漏极区之间延伸。
40.一种制作存储器阵列的方法，其包括：
在半导体衬底内形成有源区域区与沟槽隔离区的交替线；
将一系列跑道状沟槽蚀刻到所述有源区域区及所述沟槽隔离区中，所述跑道状沟槽大体上正交于有源区域区与沟槽隔离区的所述交替线；
在所述跑道状沟槽内形成传导材料以相对于所述跑道状沟槽中的个别沟槽形成一对电连接的字线；
在所述有源区域区内横向地在所述跑道状沟槽内部且横向地在所述跑道状沟槽的外部形成源极/漏极区；
形成与横向地接纳在所述跑道状沟槽的外部的所述源极/漏极区电连接的传导数据线；及
形成与横向地接纳在所述轨道状沟槽的内部的所述源极/漏极区分别电连接的电荷存储装置。
41.一种制作存储器阵列的方法，其包括：
在半导体衬底内形成有源区域区与沟槽隔离区的交替线；
将一系列沟槽对蚀刻到所述有源区域区及所述沟槽隔离区中，所述沟槽对大体上正交于有源区域区与沟槽隔离区的所述交替线；
将至少一个互连沟槽蚀刻到使每一对所述沟槽中的个别沟槽互连的所述半导体衬底中；
在所述沟槽对及所述互连沟槽内形成传导材料以相对于所述对中的个别沟槽形成一对电连接的字线；
在所述有源区域区内在每一对的所述沟槽中的个别沟槽中间且横向地在每一对所述沟槽中的个别沟槽的外部形成源极/漏极区；
形成与横向地接纳在每一对的所述沟槽中的个别沟槽的外部的所述源极/漏极区电连接的传导数据线；及形成与接纳在每一对的所述沟槽中的个别沟槽中间的所述源极/漏极区分别电连接的电荷存储装置。
42.如权利要求41所述的方法，其中蚀刻所述系列的沟槽对及蚀刻所述互连沟槽包括共同的遮蔽步骤。
43.如权利要求41所述的方法，其中蚀刻所述系列的沟槽对及蚀刻所述互连沟槽包括共同的蚀刻步骤。
44.如权利要求41所述的方法，其中形成所述传导材料包括在所述沟槽对内且同时在所述互连沟槽内沉积至少一些传导材料。
45.如权利要求41所述的方法，其包括为每一对仅蚀刻一个互连沟槽。
46.如权利要求41所述的方法，其包括为每一对仅蚀刻两个互连沟槽。
47.如权利要求41所述的方法，其包括为每一对蚀刻多个互连沟槽。
48.一种存储器阵列，其包括：
多个存储器单元，所述存储器单元中的个别单元包括：
第一及第二栅极、横向地位于所述栅极中间的第一源极/漏极区、横向地位于所述第一栅极的外侧的第二源极/漏极区及横向地位于所述第二栅极的外侧的第三源极/漏极区；
传导数据线，其电连接所述第二源极/漏极区及所述第三源极/漏极区两者；及
电荷存储装置，其与所述第一源极/漏极区电连接。
49.如权利要求48所述的存储器阵列，其中所述第一源极/漏极区竖向地位于所述第一及第二栅极的外侧。
50.如权利要求48所述的存储器阵列，其中所述传导数据线竖向地位于所述第一及第二栅极的外侧，所述电荷存储装置竖向地位于所述传导数据线的外侧。
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