CN101527547B - Method and related device for controlling power output stage of power amplifier - Google Patents
Method and related device for controlling power output stage of power amplifier Download PDFInfo
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- CN101527547B CN101527547B CN200810083154.6A CN200810083154A CN101527547B CN 101527547 B CN101527547 B CN 101527547B CN 200810083154 A CN200810083154 A CN 200810083154A CN 101527547 B CN101527547 B CN 101527547B
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Abstract
The invention relates to a control circuit for a power amplifier, which comprises an oversampling unit, a control module, a pulse width modulation circuit and a pulse width adjusting unit, wherein the oversampling unit is used for oversampling a digital input signal to generate an oversampling signal; the control module is used for generating a first control signal and a second control signal based on the oversampling signal; the pulse width modulation circuit is used for generating a first pulse width modulation signal based on the first control signal; and the pulse width adjusting unit is used for adjusting the pulse width of the first modulation signal based on the second control signal to generate a second pulse width modulation signal so as to control the power output stage of the power amplifier.
Description
Technical field
The present invention has the technology about audio frequency process, is espespecially used for controlling the method for power output stage and the relevant apparatus of power amplifier.
Background technology
Digital power amplifier, or be called D-type power amplifier (class-D power amplifier), be widely used in many audio processing equipments because having high efficiency advantage.Digital audio frequency power amplifier utilizes a PWM circuit (PWM circuit) to produce a pulse-width modulation signal, to control the running of power output stage (power stage) according to digital input signals.
The usefulness of digital audio frequency power amplifier is relevant with the resolution (that is bit number) of PWM circuit (PWM circuit).Generally speaking, the resolution of PWM circuit is higher, and the usefulness of digital audio frequency power amplifier better.But known PWM circuit just can reach the object promoting resolution under must be operated at higher frequency.With the angle of process, the frequency of operation of lift elements can increase degree of difficulty and the manufacturing cost of manufacture.When considering cost, the usefulness of digital audio frequency power amplifier will be subject to the restriction of process and be difficult to effective lifting.
Summary of the invention
In view of this, an object of the present invention is the method and the relevant apparatus that provide the power output stage controlling audio-frequency power amplifier, to solve the problem.
Present description provides a kind of embodiment of control circuit of power amplifier, it includes: an oversampling unit, is used for carrying out oversampling to a digital input signals, to produce an oversampling signal; One control module, is used for producing one first control signal and one second control signal according to this oversampling signal; One PWM circuit, is used for producing one first pulse-width modulation signal according to this first control signal; And a pulse-width adjustment unit, be used for adjusting according to this second control signal the pulsewidth of this first pulse-width modulation signal, to produce one second pulse-width modulation signal to control a power output stage of this power amplifier.
This specification provides a kind of method controlling the power output stage of power amplifier, and it includes: carry out oversampling to a digital input signals, to produce an oversampling signal; One first control signal and one second control signal is produced according to this oversampling signal; One first pulse-width modulation signal is produced according to this first control signal; And adjust the pulsewidth of this first pulse-width modulation signal according to this second control signal, to produce one second pulse-width modulation signal to control this power output stage.
Accompanying drawing explanation
Fig. 1 is the calcspar after a preferred embodiment of audio-frequency power amplifier of the present invention simplifies.
Fig. 2 is that the present invention is used for the embodiment flow chart of method of the power output stage in control chart 1.
Fig. 3 is the calcspar after the first embodiment of control module in Fig. 1 simplifies.
Fig. 4 is the calcspar after the first embodiment of pulse-width adjustment unit in Fig. 1 simplifies.
Fig. 5 is the calcspar after the second embodiment of control module in Fig. 1 simplifies.
Fig. 6 is the calcspar after the second embodiment of pulse-width adjustment unit in Fig. 1 simplifies.
Fig. 7 is the calcspar after the 3rd embodiment of pulse-width adjustment unit in Fig. 1 simplifies.
Fig. 8 is the calcspar after the 3rd embodiment of control module in Fig. 1 simplifies.
[main element symbol description]
100 audio-frequency power amplifiers
102 control circuits
110 oversampling unit
120 control modules
130 PWM circuit
140 pulse-width adjustment unit
150 clock generating modules
160 power output stages
200 flow charts
210,220,230,240,250 steps
310,510,520,810,820 triangular integration modulators
320,830 determining meanss
410,610,710 phase shifters
420,620,720,736 multiplexers
430,732 or door
630,734 and door
730 combinational logics
Embodiment
Please refer to Fig. 1, the calcspar of its audio-frequency power amplifier 100 illustrated according to one embodiment of the invention.As shown in the figure, audio-frequency power amplifier 100 comprises a control circuit (controller) 102 and a power output stage (power stage) 160, and wherein power output stage 160 is generally a switching power output stage.In the present embodiment, control circuit 102 includes oversampling unit (oversampler) 110, control module 120, PWM circuit (PWM circuit) 130, pulse-width adjustment unit (pulse width adjuster) 140 and a clock generation module 150.Clock generating module 150 is used for producing oversampling unit 110 and one first work clock CLK_1 needed for control module 120, and one second work clock CLK_2 needed for PWM circuit 130, wherein the frequency of this first work clock CLK_1 is F1, and the frequency of this second work clock CLK_2 is F2, and F2 is greater than F1.In implementation, clock generating module 150 can utilize a phase-locked loop to produce this second work clock CLK_2, and utilizes a frequency elimination device to carry out frequency elimination to this second work clock CLK_2, to produce lower this first work clock CLK_1 of frequency.Below, collocation Fig. 2 is further illustrated running and the execution mode of control circuit 102.
Fig. 2 is embodiment flow process Figure 200 of method that the present invention is used for controlling power output stage 160, and its each step comprised is described below:
In step 210, oversampling unit 110 meeting receive frequency is the digital audio and video signals Di of a N1 bit of F0, and according to this first work clock CLK_1, oversampling (oversampling) is carried out to this digital audio and video signals Di, with oversampling signal (oversampledsignal) Ds of the N1 bit that to produce frequency be F1, wherein F1 is greater than F0.
In a step 220, control module 120 can produce according to this oversampling signal Ds the first control signal Ctl_1 that frequency is a N2 bit of F1, and frequency is the second control signal Ctl_2 of a N3 bit of F1, wherein N1 > N2 >=N3 >=1.
Please refer to Fig. 3, its illustrate into control module 120 of the present invention first embodiment simplify after calcspar.As shown in Figure 3, the control module 120 of the present embodiment comprises the triangular integration modulator of a N4 bit (sigma delta modulator) 310 and a determining means 320, wherein N4=N2+N3 and N4 < N1.Triangular integration modulator 310 is used for carrying out a trigonometric integral modulation to this oversampling signal Ds, to produce the modulating signal M0 of a N4 bit.Operationally, triangular integration modulator 310, except reducing the bit number of digital audio and video signals, also has the function of noise reformation (noise shaping) concurrently.
Then, this modulating signal M0 that determining means 320 can export according to triangular integration modulator 310, produces this first control signal Ctl_1 and this second control signal Ctl_2.In implementation, determining means 320 can produce this first control signal Ctl_1 according to the multiple high bit of this modulating signal M0 (most significant bits), and produces this second control signal Ctl_2 according at least one low bit (1east significant bit) of this modulating signal M0.Such as, in one embodiment, N2 the high bit that determining means 320 can export this modulating signal M0 is used as this first control signal Ctl_1, and N3 the low bit exporting this modulating signal M0 is used as this second control signal Ctl_2.In this instance, determining means 320 can realize with a de-multiplexer.
Then, in step 230, PWM circuit 130 can produce according to this first control signal Ctl_1 the first pulse-width modulation signal PWM1 that frequency is 1 bit of F2, wherein F2=2
n2× F1.
In step 240, the instruction of this second control signal Ctl_2 that pulse-width adjustment unit 140 can produce according to control module 120, adjusts the pulsewidth of this first pulse-width modulation signal PWM1, to produce one second pulse-width modulation signal PWM2.Below, will Fig. 4 be utilized to further illustrate enforcement and the function mode of pulse-width adjustment unit 140.
Fig. 4 illustrate into pulse-width adjustment unit 140 of the present invention first embodiment simplify after calcspar.The pulse-width adjustment unit 140 of the present embodiment includes a phase shifter (phase shifter) 410, multiplexer 420 and one or door (OR gate) 430.Phase shifter 410 is used for producing multiple inhibit signal according to this first pulse-width modulation signal PWM1.In this example, phase shifter 410 utilizes the delay chain (delay chain) be made up of n delay-level (delaystage) to postpone this first pulse-width modulation signal PWM1, to produce n inhibit signal P1 ~ Pn, wherein n=2
n3-1.In one embodiment, the retardation of each delay-level of phase shifter 410 is all 1/ (F2 × 2
n3), therefore the phase difference in the plurality of inhibit signal P1 ~ Pn between adjacent two inhibit signals is all 1/ (F2 × 2
n3).Note that this is only an embodiment, but not limit to the actual set mode of the retardation of each delay-level in phase shifter 410.
Multiplexer 420 can according to the value of this second control signal Ctl_2, and one of them selecting the plurality of inhibit signal P1 ~ Pn is as output.Such as, in one embodiment, when the value of this second control signal Ctl_2 is 0, multiplexer 420 can export a logic " 0 " signal; When the value of this second control signal Ctl_2 is 1, multiplexer 420 can select inhibit signal P1 as output; When the value of this second control signal Ctl_2 is 2, multiplexer 420 can select inhibit signal P2 as output; And when the value of this second control signal Ctl_2 is 2
n3when-1, multiplexer 420 can select inhibit signal Pn as output, and the rest may be inferred.Then, the output of this first pulse-width modulation signal PWM1 and multiplexer 420 can be carried out a logic OR computing, to produce this second pulse-width modulation signal PWM2 by pulse-width adjustment unit 140 or door 430.
From aforementioned, when the value of this second control signal Ctl_2 is 0, or this second pulse-width modulation signal PWM2 that door 430 exports can be identical in fact with this first pulse-width modulation signal PWM1.But when the value of this second control signal Ctl_2 is not 0, due to this first pulse-width modulation signal PWM1 and multiplexer 420 can't overlap completely during both high logic levels of an inhibit signal Pi (i=1 ~ n) of selecting, therefore or the pulsewidth of this second pulse-width modulation signal PWM2 that exports of door 430 can be greater than the pulsewidth of this first pulse-width modulation signal PWM1.In other words, this second control signal Ctl_2 that the pulse-width adjustment unit 140 of the present embodiment exports according to control module 120, determines whether the output pulse width increasing PWM circuit 130, to form this second pulse-width modulation signal PWM2.
Next in step 250, this second pulse-width modulation signal PWM2 that audio-frequency power amplifier 100 can utilize control circuit 102 to produce carrys out driving power output stage 160.The function mode utilizing a pulse-width modulation signal to control a power output stage is known technology, does not add explanation at this.
In the control circuit 102 of audio-frequency power amplifier 100, if the modulating signal M0 of the N4 bit directly produced with the triangular integration modulator 310 of control module 120 is used as the input signal of PWM circuit 130, then the frequency of operation of PWM circuit 130 must be promoted to 2
n4× F1.This by significantly increase PWM circuit 130 manufacture on degree of difficulty and cost.It can thus be appreciated that, the modulating signal M0 that control module 120 utilizes determining means 320 to be exported by triangular integration modulator 310 resolves into the mode of bit number the first lower control signal Ctl_1 and the second control signal Ctl_2, effectively can reduce the operating frequency of PWM circuit 130, and then reduce the degree of difficulty and cost that manufacture.On the other hand, pulse-width adjustment unit 140 due to control circuit 102 can finely tune the output pulse width of PWM circuit 130 according to this second control signal Ctl_2, therefore the resolution of the second pulse-width modulation signal PWM2 exported, PWM circuit 130 can be in close proximity to 2
n4the resolution of the pulse-width modulation signal that the modulating signal M0 of foundation N4 bit produces under the operating frequency of × F1.In other words, the framework of aforementioned control circuit 102 when not affecting audio-frequency power amplifier 100 overall efficiency, can significantly reduce the frequency of operation of PWM circuit 130.From another angle, compare with the same known control circuit of PWM circuit 130 that uses, aforesaid control circuit 102 has preferably output pulse width resolution, therefore effectively can promote the usefulness of audio-frequency power amplifier.
Please refer to Fig. 5, its illustrate into control module 120 of the present invention second embodiment simplify after calcspar.In the present embodiment, control module 120 comprises the first triangular integration modulator 510 of a N2 bit and the second triangular integration modulator 520, wherein N4=N2+N3 of a N4 bit.First triangular integration modulator 510 is used for carrying out one first trigonometric integral modulation to this oversampling signal Ds, to produce the first control signal Ctl_1 of N2 bit.Second triangular integration modulator 520 is used for carrying out one second trigonometric integral modulation to this oversampling signal Ds, to produce a modulating signal of N4 bit, and utilizes the N3 of this modulating signal low bit to be used as the second control signal Ctl_2.Due to the first control signal Ctl_1 of the N2 bit that the first triangular integration modulator 510 produces, N2 high bit of this modulating signal produced with the second triangular integration modulator 520 is identical in fact, therefore the control module 120 shown in Fig. 5 is equivalent in fact the embodiment of earlier figures 3.In the case, pulse-width adjustment unit 140 can realize by the embodiment of Fig. 4 equally.
In the foregoing embodiments, this second control signal Ctl_2 that pulse-width adjustment unit 140 exports according to control module 120, determines whether the output pulse width increasing PWM circuit 130, to produce this second pulse-width modulation signal PWM2.But this is only an embodiment, but not limit to actual execution mode of the present invention.For the control module 120 shown in Fig. 3, when determining means 320 receives the modulating signal M0 of the N4 (=N2+N3) bit that triangular integration modulator 310 exports, value representated by N2 in this modulating signal M0 high bit can be added 1 by determining means 320, using the value as this first control signal Ctl_1, and by 2
n3deduct this N3 the value representated by low bit, using the value as this second control signal Ctl_2.Compared to aforesaid embodiment, the value of the first control signal Ctl_1 in the present embodiment is comparatively large, therefore the one first pulse-width modulation signal PWM1 ' that PWM circuit 130 meeting output pulse width is wider.In the case, the embodiment that pulse-width adjustment unit 140 can illustrate with Fig. 6 realizes.
As shown in Figure 6, the pulse-width adjustment unit 140 of the present embodiment includes phase shifter 610, multiplexer 620 and one and door (AND gate) 630.The function mode of phase shifter 610 is identical in fact with the phase shifter 410 in earlier figures 4, for for purpose of brevity, is not repeated.In this embodiment, when the value of this second control signal Ctl_2 is 0, multiplexer 620 can export a logic " 1 " signal; When the value of this second control signal Ctl_2 is 1, multiplexer 620 can select inhibit signal P1 as output; When the value of this second control signal Ctl_2 is 2, multiplexer 620 can select inhibit signal P2 as output; And when the value of this second control signal Ctl_2 is 2
n3when-1, multiplexer 620 can select inhibit signal Pn as output, and the rest may be inferred.
Be used for this first pulse-width modulation signal PWM1 ' and the output of multiplexer 620 to carry out a logic and operation, to produce this second pulse-width modulation signal PWM2 with door 630.Specifically, when the value of this second control signal Ctl_2 is 0, this second pulse-width modulation signal PWM2 exported with door 630 can be identical in fact with this first pulse-width modulation signal PWM1 '.But when the value of this second control signal Ctl_2 is not 0, the pulsewidth of this second pulse-width modulation signal PWM2 exported with door 630 can be less than the pulsewidth of this first pulse-width modulation signal PWM1 '.In other words, this second control signal Ctl_2 that the pulse-width adjustment unit 140 of the present embodiment exports according to control module 120, determines whether the output pulse width reducing PWM circuit 130, to form this second pulse-width modulation signal PWM2.
Refer again to Fig. 3, in another embodiment, when the determining means 320 of control module 120 receives the modulating signal M0 of the N4 (=N2+N3) bit that triangular integration modulator 310 exports, determining means 320 can produce the first control signal Ctl_1 of a N2+1 bit according to the N2 of this modulating signal M0 high bit, wherein N2 the high bit of this first control signal Ctl_1 is N2 the high bit of this modulating signal M0, and the least significant bit of this first control signal Ctl_1 (LSB) is fixed as 1.In this example, the value representated by the N3 of this modulating signal M0 low bit can be deducted 2 by determining means 320
n3-1, to produce the second control signal Ctl_2 of a N3 bit, wherein the highest significant position unit (MSB) of this second control signal Ctl_2 is a symbol bit (sign bit).For example, suppose that N3 equals 3, if the value of the N3 of this modulating signal M0 representated by low bit is 7, then the value of this second control signal Ctl_2 that determining means 320 exports is 3, and meaning and bit sequence are " 011 "; If the N3 of this modulating signal M0 the value representated by low bit is 4, then the bit sequence of this second control signal Ctl_2 is " 000 "; If the value of the N3 of this modulating signal M0 representated by low bit is 1, then the bit sequence of this second control signal Ctl_2 that determining means 320 exports is " 101 "; And if the value of the N3 of this modulating signal M0 representated by low bit is 0, then the bit sequence of this second control signal Ctl_2 that determining means 320 exports is " 100 ".
In the present embodiment, PWM circuit 130 meeting output pulse width is between aforesaid pulse-width modulation signal PWM1 and PWM1 ' one first pulse-width modulation signal PWM1 between the two ".In the case, the embodiment that pulse-width adjustment unit 140 can illustrate with Fig. 7 realizes.
As shown in Figure 7, the pulse-width adjustment unit 140 of the present embodiment includes phase shifter 710, multiplexer 720 and a combinational logic 730.Phase shifter 710 is made up of m delay-level, is used for postponing this first pulse-width modulation signal PWM1 ", to produce m inhibit signal P1 ~ Pm, wherein m=2
n3-1.Multiplexer 720 can according to the value of this second control signal Ctl_2, and one of them selecting the plurality of inhibit signal P1 ~ Pm is as output.For convenience of description, illustrate with the example that aforementioned N3 equals 3 below.In this embodiment, m equals 4, and when the bit sequence of this second control signal Ctl_2 is " 000 ", multiplexer 720 can export a logic " 0 " signal; When the bit sequence of this second control signal Ctl_2 is " 001 " or " 101 ", multiplexer 720 can select inhibit signal P1 as output; When the bit sequence of this second control signal Ctl_2 is " 010 " or " 110 ", multiplexer 720 can select inhibit signal P2 as output; And when the bit sequence of this second control signal Ctl_2 is " 100 ", multiplexer 720 can select inhibit signal Pm as output, the rest may be inferred.Then, combinational logic 730 understands the symbol bit according to this second control signal Ctl_2, by this first pulse-width modulation signal PWM1 " carry out a logic and operation or a logic OR computing, to produce one second pulse-width modulation signal PWM2 with the output of multiplexer 720.
As shown in Figure 7, the combinational logic 730 of the present embodiment includes one or door 732, is used for this first pulse-width modulation signal PWM1 " carry out a logic OR (OR) computing, to produce one first signal S1 with the output of multiplexer 720; One with door 734, be used for this first pulse-width modulation signal PWM1 " carry out a logical AND (AND) computing, to produce a secondary signal S2 with the output of multiplexer 720; And a multiplexer 736, be used for according to the symbol bit in this second control signal Ctl_2 selects this first signal S1 and this secondary signal S2 that one of them is used as this second pulse-width modulation signal PWM2.In this example, if the symbol bit of this second control signal Ctl_2 is " 0 ", multiplexer 736 can export this first signal S1 and be used as this second pulse-width modulation signal PWM2, if and the symbol bit of this second control signal Ctl_2 is " 1 ", then multiplexer 736 can export this secondary signal S2 and be used as this second pulse-width modulation signal PWM2.From the above, this second control signal Ctl_2 that the pulse-width adjustment unit 140 of the present embodiment exports according to control module 120, increases or reduces the output pulse width of PWM circuit 130, to form this second pulse-width modulation signal PWM2.
Please refer to Fig. 8, its illustrate into control module 120 of the present invention the 3rd embodiment simplify after calcspar.In the present embodiment, control module 120 comprises the second triangular integration modulator 820 and determining means 830, wherein N4=N2+N3 of the first triangular integration modulator 810, N4 bit of a N2 bit.First triangular integration modulator 810 is used for carrying out one first trigonometric integral modulation to this oversampling signal Ds, to produce one first modulating signal M1 of N2 bit.Second triangular integration modulator 820 is used for carrying out one second trigonometric integral modulation to this oversampling signal Ds, to produce one second modulating signal M2 of N4 bit.Then, determining means 830 can produce the first control signal Ctl_1 according to this first modulating signal M1, and produces the second control signal Ctl_2 according at least one low bit of this second modulating signal M2.
In one embodiment, determining means 830 can produce the first control signal Ctl_1 of a N2+1 bit according to this first modulating signal M1, wherein N2 the high bit of this first control signal Ctl_1 is N2 the bit of this first modulating signal M1, and the least significant bit of this first control signal Ctl_1 (LSB) is fixed as 1.In addition, the value representated by the N3 of this second modulating signal M2 low bit also can be deducted 2 by determining means 830
n3-1, to produce the second control signal Ctl_2 of a N3 bit, wherein the highest significant position unit (MSB) of this second control signal Ctl_2 is a symbol bit.Because determining means 830 produces the mode of this first control signal Ctl_1 and this second control signal Ctl_2, be equivalent in fact aforesaid embodiment, therefore, the pulse-width adjustment unit 140 operated of arranging in pairs or groups with the control module 120 of Fig. 8 can realize by the embodiment of Fig. 7.
In implementation, also can an a low pass filter (such as wave digital lowpass filter be set between the oversampling unit 110 of aforementioned control circuit 102 and control module 120, figure does not show), be used for carrying out a low-pass filtering computing to the oversampling signal Ds that oversampling unit 110 exports, to increase the sampling point in oversampling signal Ds.Such as, this low pass filter can increase the sampling point number in oversampling signal Ds with interpolation method.From an angle, the running of this low pass filter can allow the signal output waveform after oversampling more smooth-going.Thus, the overall efficiency of control circuit 102 can be promoted further.Note that this low pass filter in fact also can be incorporated in same hardware cell with aforesaid oversampling unit 110 or control module 120.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (16)
1. a control circuit for power amplifier, it includes:
One oversampling unit, is used for carrying out oversampling to a digital input signals, to produce an oversampling signal;
One control module, is used for producing one first control signal and one second control signal according to this oversampling signal;
One PWM circuit, is used for producing one first pulse-width modulation signal according to this first control signal; And
One pulse-width adjustment unit, is used for adjusting according to this second control signal the pulsewidth of this first pulse-width modulation signal, to produce one second pulse-width modulation signal to control a power output stage of this power amplifier.
2. control circuit as claimed in claim 1, wherein this control module includes:
One triangular integration modulator, is used for carrying out a trigonometric integral modulation to produce one first modulating signal to this oversampling signal; And
One determining means, is used for producing this first control signal and this second control signal according to this first modulating signal.
3. control circuit as claimed in claim 2, wherein this determining means produces this first control signal according to the multiple high bit of this first modulating signal, and produces this second control signal according at least one low bit of this first modulating signal.
4. control circuit as claimed in claim 1, wherein this control module includes:
One first triangular integration modulator, is used for carrying out one first trigonometric integral modulation to this oversampling signal, to produce this first control signal; And
One second triangular integration modulator, be used for carrying out one second trigonometric integral modulation to this oversampling signal, to produce one second modulating signal, wherein the bit number of this second modulating signal is higher than this first control signal, and this second triangular integration modulator also utilizes at least one low bit of this second modulating signal to be used as this second control signal.
5. control circuit as claimed in claim 1, wherein this control module includes:
One first triangular integration modulator, is used for carrying out one first trigonometric integral modulation to this oversampling signal, to produce one the 3rd modulating signal;
One second triangular integration modulator, is used for carrying out one second trigonometric integral modulation to this oversampling signal, to produce one four modulating signal of bit number higher than the 3rd modulating signal; And
One determining means, is used for producing this first control signal according to the 3rd modulating signal, and produces this second control signal according at least one low bit of the 4th modulating signal.
6. control circuit as claimed in claim 1, wherein this pulse-width adjustment unit includes:
One phase shifter, is used for producing multiple inhibit signal according to this first pulse-width modulation signal;
One multiplexer, is coupled to this phase shifter, and one of them being used for selecting the plurality of inhibit signal according to this second control signal is as output; And
One logical circuit, is coupled to this multiplexer, is used for the output of this first pulse-width modulation signal and this multiplexer to carry out a logical operation, to produce this second pulse-width modulation signal.
7. control circuit as claimed in claim 1, wherein the bit number of this first control signal is lower than the bit number of this oversampling signal.
8. control circuit as claimed in claim 1, it separately includes a low pass filter, is used for increasing the sampling point of this oversampling signal.
9. control a method for a power output stage of a power amplifier, it includes:
Oversampling is carried out to a digital input signals, to produce an oversampling signal;
One first control signal and one second control signal is produced according to this oversampling signal;
One first pulse-width modulation signal is produced according to this first control signal; And
The pulsewidth of this first pulse-width modulation signal is adjusted, to produce one second pulse-width modulation signal to control this power output stage according to this second control signal.
10. method as claimed in claim 9, the step wherein producing this first control signal and this second control signal includes:
One trigonometric integral modulation is carried out to this oversampling signal, to produce one first modulating signal; And
This first control signal and this second control signal is produced according to this first modulating signal.
11. methods as claimed in claim 10, wherein include according to the step that this first modulating signal produces this first control signal and this second control signal:
Multiple high bit according to this first modulating signal produces this first control signal; And
At least one low bit according to this first modulating signal produces this second control signal.
12. methods as claimed in claim 9, the step wherein producing this first control signal and this second control signal includes:
One first trigonometric integral modulation is carried out to this oversampling signal, to produce this first control signal;
One second trigonometric integral modulation is carried out to this oversampling signal, to produce one second modulating signal of bit number higher than this first control signal; And
At least one low bit of this second modulating signal is utilized to be used as this second control signal.
13. methods as claimed in claim 9, the step wherein producing this first control signal and this second control signal includes:
One first trigonometric integral modulation is carried out to this oversampling signal, to produce one the 3rd modulating signal;
One second trigonometric integral modulation is carried out to this oversampling signal, to produce one four modulating signal of bit number higher than the 3rd modulating signal;
This first control signal is produced according to the 3rd modulating signal; And
At least one low bit according to the 4th modulating signal produces this second control signal.
14. methods as claimed in claim 9, the step wherein producing this second pulse-width modulation signal includes:
Postpone this first pulse-width modulation signal to produce multiple inhibit signal.
15. methods as claimed in claim 9, the step wherein producing this second pulse-width modulation signal includes:
Postpone this first pulse-width modulation signal to produce multiple inhibit signal;
One of them of the plurality of inhibit signal is selected according to this second control signal; And
According to this second control signal, this first pulse-width modulation signal and a selected inhibit signal are carried out at least one logical operation, to produce this second pulse-width modulation signal.
16. methods as claimed in claim 9, wherein include according to the step that this oversampling signal produces this first control signal and this second control signal:
Before producing this first control signal and this second control signal according to this oversampling signal, a low-pass filtering treatment is carried out to this oversampling signal.
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| DE102012219244A1 (en) * | 2012-10-22 | 2014-04-24 | Robert Bosch Gmbh | Method of power controller of electrical consumer with power output stage, involves changing duty ratio of pulse width modulation (PWM) so that actual output power correspond to target power |
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| US7209002B2 (en) * | 2002-12-20 | 2007-04-24 | Sony Corporation | Audio amplifier |
| US7292171B2 (en) * | 2004-02-06 | 2007-11-06 | Anagram Technologies Sa | Method and device for the version of digital signals with heterogeneous formats and application thereof to the digital amplification of audio signals |
| CN1777022A (en) * | 2004-11-08 | 2006-05-24 | 三星电子株式会社 | Digital audio amplifier, an audio system including the same, and a method of amplifying an audio signal |
| CN1992532A (en) * | 2005-12-30 | 2007-07-04 | 联发科技股份有限公司 | Delta-sigma dac |
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| CN101527547A (en) | 2009-09-09 |
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