CN101529557B - 用于将间距倍增大于2的因数的单个间隔物工艺及相关中间ic结构 - Google Patents

用于将间距倍增大于2的因数的单个间隔物工艺及相关中间ic结构 Download PDF

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CN101529557B
CN101529557B CN2007800379938A CN200780037993A CN101529557B CN 101529557 B CN101529557 B CN 101529557B CN 2007800379938 A CN2007800379938 A CN 2007800379938A CN 200780037993 A CN200780037993 A CN 200780037993A CN 101529557 B CN101529557 B CN 101529557B
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戴维·H·韦尔斯
米尔扎菲尔·K·阿巴切夫
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Abstract

本发明提供用于将间距倍增大于2的因数的单个间隔物工艺。在一个实施例中，在衬底上方形成n(其中n≥2)层堆叠心轴(150b)、(140a)，所述n层中的每一者包含彼此大致平行的多个心轴(150b)、(140a)。层n处的心轴(150b)在层n-1处的心轴(140a)上方且平行于心轴(140a)，且层n处的邻接心轴之间的距离大于层n-1处的邻接心轴之间的距离。同时在心轴(150b)、(140a)的侧壁上形成间隔物(185)。蚀刻掉心轴(150b)、(140a)的暴露部分且将由间隔物(185)界定的线图案转移到衬底(110)。

Description

用于将间距倍增大于2的因数的单个间隔物工艺及相关中间IC结构
相关申请案交叉参考
本申请案涉及并以全文引用方式并入以下专利申请案：韦尔斯(Wells)在2005年6月9日提出申请的第11/150,408号美国专利申请案；桑特(Sant)等人在2005年6月2日提出申请的第11/144,543号美国专利申请案；及韦尔斯在2005年9月1日提出申请的第11/217,270号美国专利申请案；及阿巴切夫(Abatchev)等人在2005年5月23日提出申请的第11/134,982号美国专利申请案。 
技术领域
本发明在若干实施例中一般来说涉及用于半导体制作的掩蔽技术，且更特定来说涉及包括间距倍增的掩蔽技术。 
背景技术
由于许多因素(其中包括对增加的便携性、计算能力、存储器容量及能量效率的需求)，集成电路的大小正不断减小。形成集成电路的组成特征(例如，电装置及互连线)的大小也持续降低以促进此大小减小。 
降低特征大小的趋势在集成电路(IC)工业中较明显，举例来说，在例如动态随机存取存储器(DRAM)、快闪存储器、静态随机存取存储器(SRAM)及铁电(FE)存储器等存储器电路或装置中。集成电路存储器的其它实例包括MRAM(包括磁阻元件)、可编程熔丝存储器、可编程导体存储器(包括金属掺杂硫属化物玻璃元件)、SRAM、SDRAM、EEPROM及其它易失性及非易失性存储器方案。举一个实例，DRAM常规上包含数百万个相同的电路元件，称作存储器单元。DRAM存储器单元常规上包括两个电装置：存储电容器及存取场效晶体管。每一存储器单元是可存储一个数据位(二进制数字)的可寻址位置。可通过晶体管将位写入到单元且可通过感测电容器中的电荷读取所述位。通过降低包含存储器单元的电装置的大小及存取存储器单元的导线的大小，存储器装置可制造得更小。另外，可通过将更多的存储器单元装配于存储器装置中的给定区域内来增加存储容量。 
常规上使用其中首先在半导体衬底上方的临时层中形成界定特征的图案且随后使用常规蚀刻化学物将所述图案转移到所述衬底的工艺来形成所述特征(例如，导线)。通常使用光刻法来图案化光可定义(或光致抗蚀剂)层内的此类特征。在光刻 法中，使用包括引导光(或辐射)穿过具有对应于将要在衬底中形成的特征图案的图案的光罩的工艺来在所述光可定义层中形成所述特征图案。 
可通过“间距”的概念来描述特征的大小，间距被定义为两个相邻特征中的相同点之间的距离。这些特征通常由邻近特征之间的间隔界定。间隔通常由例如绝缘体等材料填充。因此，对于规则的图案(例如，成阵列)，可将间距视为特征的宽度与所述特征的一个侧上分隔所述特征与相邻特征的间隔的宽度的和。然而，由于例如光学及光(或辐射)波长等因素，光刻技术各自具有最小间距，低于此最小间距，特定光刻技术便不能够可靠地形成特征。因此，给定光刻技术的最小间距限制是进一步减小特征大小的阻碍。 
“间距倍增”或“间距加倍”是一种用于使光刻技术的能力延伸超出其最小间距的建议方法。间距倍增方法图解说明于图1A-1F中且描述于颁发给劳雷(Lowrey)等人的第5,328,810号美国专利中，此专利的全部揭示内容以引用的方式并入本文中。参照图1A，在光致抗蚀剂层中以光刻方式形成线10图案，所述光致抗蚀剂层上覆于可消耗材料层20上，而可消耗材料层20又上覆于衬底30上。如图1B中所示，然后使用蚀刻(例如各向异性蚀刻)将图案转移到层20，从而形成占位符或心轴40。可剥离光致抗蚀剂线10且可以各向同性方式蚀刻心轴40以增加相邻心轴40之间的距离，如图1C中所示。随后在心轴40上方沉积间隔物材料层50，如图1D中所示。然后在心轴40的侧上形成间隔物60，即延伸或经原始形成而从另一材料的侧壁延伸的材料。所述间隔物形成是通过以方向性间隔物蚀刻从水平表面70及80优先蚀刻间隔物材料而完成，如图1E中所示。然后移除剩余的心轴40，仅留下间隔物60，其一起充当用于图案化的掩模，如图1F中所示。因此，如果给定间距先前包括界定一个特征及一个间隔的图案，那么相同宽度现在包括两个特征及两个间隔，其中所述间隔由(例如)间隔物60界定。因此，有效地降低了可通过光刻技术实现的最小特征大小。 
尽管在以上实例中间距实际上被减半，但常规上将此间距减小称作间距“加倍”或更一般来说，称作间距“倍增”。因此，常规上，将间距“倍增”某一因数实际上涉及使间距减小所述因数。因此，可在两个相反意义上使用间距：规则图案中相同元件之间的距离及固定线性距离中特征的数量。间距倍增(或间距加倍)假设后一种意义，即，如果间距加倍，那么在其中光刻法仅界定一个特征及间隔的区域中界定两个特征及间隔。 
在2005年6月9日提出申请颁发给韦尔斯(“Wells”)的第11/150,408号美国专利申请案揭示用于使用间隔物作为后续间隔物的心轴来形成间距倍增的特征的方法。根据本文中所揭示的方法，在衬底上方的心轴的侧壁上形成第一组间隔物。基于所述侧壁位置来选择所述间隔物的宽度，使得所述间隔物在所需位置处居中。移除所述心轴且使用所述间隔物作为后续间隔物形成的心轴。然后在所述第一组间隔物上沉积第二材料且回蚀刻所述第二材料以形成第二组间隔物。所述第二组间隔物的宽度经选择，使得这些间隔物也在其所需位置处居中。移除所述第一组间隔物且使用所述第二组间隔物作为用于蚀刻衬底的掩模。相应地，实现间距倍增因数4，且因此此技术可扩展到间距倍增因数8、16等。
作为另一实例，在2005年6月2日提出申请颁发给桑特等人(“Sant”)的第11/144,543号美国专利申请案揭示用于使用间隔物形成的多个级来形成间距倍增的特征的方法。根据本文中所揭示的方法，使用多个间距倍增的间隔物来形成具有具有异常小的临界尺寸的特征的掩模图案。移除在多个心轴周围形成的每一对间隔物中的一者且在剩余间隔物周围沉积由两种互选择性可蚀刻材料形成的交替层。然后蚀刻由所述材料中的一者形成的层，留下由所述材料中的另一者形成的垂直延伸层，其形成掩模图案。作为替代方案，不是沉积交替层，而是在剩余间隔物周围沉积无定形碳，此后在所述无定形碳上形成间隔物对的多个循环，从而移除所述间隔物对中的一者并沉积无定形碳层。可重复所述循环以形成所需图案。 
针对间距倍增使用多个间隔物形成步骤的方法产生较大的处理成本。举例来说，韦尔斯的第11/150,408号美国专利申请案的工艺两次形成间隔物以实现间距倍增因数4。另外，形成紧密特征需要使用高分辨率光学扫描仪，其可增加处理成本。举例来说，具有约100nm的分辨率的248纳米(nm)光学扫描仪在提出申请时花费约$20,000,000，且具有约65nm的分辨率的193nm扫描仪花费约$30,000,000。另外，当前可与193nm扫描仪一同使用的光致抗蚀剂材料不如可供248nm扫描仪使用的那些光致抗蚀剂材料强健，因此对现有光致抗蚀剂掩模上的间隔物形成增加限制。 
相应地，有利地形成低于光刻技术的最小间距的特征，同时使处理步骤的数量最小化，且最终使处理时间及成本最小化。相应地，有利地准许间距倍增到的程度的灵活性。 
发明内容
根据本发明的实施例，提供其中使用单个间隔物步骤来完成间距倍增因数2n的方法，从而提供处理时间及成本的巨大灵活性及节约。另外，可使用较不昂贵的光学扫描仪(例如，365nm扫描仪)来执行根据实施例的方法，从而增加处理成本上的额外节约。 
根据本发明的实施例，在衬底上方提供n(其中n≥2)层堆叠心轴。所述衬底可包含硅晶片，另一半导电材料的晶片或包括半导电材料层及一个或一个以上插入层(例如，硬掩模层)的另一体衬底。所述n层心轴中的每一者可包含彼此大致平行的多个心轴。在一个实施例中，所述心轴界定平行线。层n处的心轴可被安置在层n-1处的心轴上方，安置在层n-1处的心轴上且相对于层n-1处的所述心轴居中且与层n-1处的心轴直接接触。层n处的邻近心轴之间的横向距离或间隔大于层n-1处的邻近心轴之间的横向距离或间隔。接下来，同时在所述心轴周围形成间隔物，且移除所述心轴的暴露部分，从而留下间隔物图案。然后，将所述间隔物图案用于处理。举例来说，随后可提供蚀刻化学物以将所述间隔物图案转移到下伏的衬底。此步骤可需要将所述间隔物图案转移到上覆于所述衬底上的一个或一个以上硬掩模层且随后移除所述间隔物。根据本发明实施例的方法的间距可倍增因数2n。举例来说，在两层心轴(n＝2)的情况下，所述间距倍增因数4，且在三层心轴(n＝3)的情况下，所述间距倍增因数6、8等。 
在一个实施例中，所述衬底包含上部层间电介质(ILD)层且通过所述掩模处理 形成镶嵌沟槽。在此种情况下，间隔物图案包含具有连接回路端的伸长线，且所述方法进一步包含在将间隔物图案转移到所述ILD中之前阻断所述回路端。在另一实施例中，所述衬底包含导体(例如，Si、多晶硅、A1、W、WSix、Ti、TiN等)且所述间隔物图案包含具有连接回路端的伸长线。在此种情况下，在将所述间隔物图案转移转移到所述导体之前或之后移除所述回路端。 
实施例的方法可用于形成间距倍增因数4、6等的特征(例如，线)图案。此类特征可充当各种装置中的组件，例如具有规则的电装置阵列的装置，且尤其是易失性及非易失性存储器装置(例如，DRAM、ROM或快闪存储器(包括NAND快闪存储器)的存储器单元阵列的线阵列及逻辑阵列。 
应了解，当材料的蚀刻速率比暴露给相同蚀刻剂的其它材料的蚀刻速率大至少约2倍时，认为所述材料选择性地或优先地可蚀刻。在某些实施例中，所述蚀刻速率比暴露给相同蚀刻剂的其它材料的蚀刻速率大至少约10倍、大至少约20倍或大至少约40倍。在本发明实施例的背景下，使用“选择性”来表示针对给定蚀刻剂一个或一个以上材料相对于一个或一个以上其它材料的蚀刻速率的蚀刻速率。作为实例，对于包含第一层及第二层的衬底，对包含所述第一层的材料具有选择性的蚀刻化学物以大致比所述第二层大的速率来蚀刻所述第一层。 
将在两种情况的背景下论述本发明的实施例。在第一种情况下，在衬底中形成间距倍增因数4的特征图案。在第一种情况下，在衬底中形成间距倍增因数6的特征图案。应了解，本文中所提供的方法可用于形成间距倍增大于6的因数的特征。作为实例，根据实施例的方法可用于形成间距倍增因数8、10等的特征。 
现在将参照图式，其中各图式中相同的编号指代相同的部件。应了解，所述图式及其中的特征未必按比例绘制。此外，尽管以下说明指定特定材料，但所属领域的技术人员将易于了解，只要合适的选择性蚀刻化学物可供所说明的转移步骤使用，可采用具有更少或更多数量的硬掩模及临时层(其之间有或没有额外的蚀刻终止层)的其它材料组合。 
在一个实施例中，提供一种用于制作集成电路的方法。所述方法包含：在衬底上方提供第一心轴，所述第一心轴具有第一宽度；及大致在所述第一心轴上方提供第二心轴，所述第二心轴具有比所述第一宽度小的第二宽度。同时在所述第一及第二心轴的侧壁上形成间隔物。选择性地移除所述心轴的相对于所述间隔物的至少若干部分以形成由所述间隔物界定的间隔物图案，且将所述间隔物图案转移到所述衬底。 
在另一实施例中，提供一种用于使用分层的心轴来形成沿一个维度间距倍增因数2n的线图案的方法。所述方法包含：在衬底上方提供n层堆叠心轴，其中n≥2，所述n层中的每一者包含多个彼此大致平行的伸长心轴，其中层n处邻近心轴之间的距离大于层n-1处邻近心轴之间的距离。同时在所述心轴的侧壁上形成间隔物。 
在再一实施例中，提供一种部分形成的集成电路(“IC”)。所述部分形成的IC包含：衬底上方的第一心轴，所述第一心轴具有第一宽度(A)；及所述第一心轴上方的第二心轴，所述第二心轴具有第二宽度(B)，其中A＞B。所述部分形成的IC进一步包含所述心轴的侧壁上的间隔物，所述间隔物具有间隔物宽度(C)，其中  C ≤ ( A - B ) 2 .
在另一实施例中，掩蔽工艺包括在两个或两个以上堆叠膜上方界定图案。将所述图案转移到两个或两个以上堆叠膜中。相对于所述两个或两个以上堆叠膜中的下部膜减小至少上部膜中的元件的尺寸以产生两个或两个以上堆叠的心轴。同时在所述堆叠心轴的侧壁上形成间隔物。 
附图说明
根据对实施例的详细说明且根据附图将更好地了解本发明，所述详细说明及附图仅图解说明本发明而不限定本发明，且附图中： 
图1A-1F是根据现有技术间距加倍方法的用于形成导线的掩蔽图案的序列的示意性截面侧视图； 
图2A-2F是根据本发明实施例的用于形成间距倍增因数4的特征图案的工艺的示意性截面侧视图； 
图3-12示意性地图解说明根据本发明实施例的类似于图2A-2F的方法的用于形成间距倍增因数4的线图案的方法； 
图3是根据本发明实施例的部分形成的集成电路的示意性截面侧视图，其从顶部到底部显示光可定义层、临时层、硬掩模层、转移层及衬底； 
图4A及4B是根据本发明的实施例图3的部分形成的集成电路在线图案在所述光可定义层中形成之后的示意性截面侧视图及俯视平面图； 
图5是根据本发明的实施例图4A及4B的部分形成的集成电路在所述线图案被转移到所述临时层之后的示意性截面侧视图； 
图6A及6B是图5的部分形成的集成电路在所述光可定义层被以各向同性方式蚀刻(或修整)之后的示意性截面侧视图及俯视平面图。根据本发明的实施例，包含所述临时层及光可定义层的线界定第一及第二心轴； 
图7是根据本发明的实施例图6A及6B的部分形成的集成电路在间隔物材料被保形地毯覆沉积在所述衬底上方之后的示意性截面侧视图； 
图8是根据本发明的实施例图7的部分形成的集成电路在所述间隔物材料被蚀刻以在所述心轴的侧壁上形成间隔物之后的示意性截面侧视图； 
图9是根据本发明的实施例图8的部分形成的集成电路在第二心轴被蚀刻掉之后的示意性截面侧视图； 
图10是根据本发明的实施例图9的部分形成的集成电路在第一心轴的暴露部分被蚀刻掉从而在硬掩模层上方留下线图案之后的示意性截面侧视图； 
图11是根据本发明的实施例图10的部分形成的集成电路在所述线图案被转移到所述硬掩模层及所述转移层之后的示意性截面侧视图； 
图12A及12B是根据本发明的实施例图11的部分形成的集成电路在所述线图案被转移到所述衬底且所述硬掩模及转移层被移除之后的示意性截面侧视图及俯视平面图； 
图12C是根据本发明的实施例图12A及12B的部分形成的集成电路在所述线的终端或“回路”已被移除之后的示意性俯视平面图； 
图13A-13H是根据本发明实施例的用于形成间距倍增因数6的特征图案的工艺的示意性截面侧视图； 
图14-22B示意性地图解说明根据本发明实施例的类似于图13A-13H的方法的用于形成间距倍增因数6的线图案的方法； 
图14是根据本发明实施例的部分形成的集成电路的示意性截面侧视图，其从底部到顶部显示衬底、转移层、第一硬掩模层、第二硬掩模层、第三硬掩模层及光可定义层； 
图15A及15B是根据本发明的实施例图14的部分形成的集成电路在线图案在所述光可定义层中形成之后的示意性截面侧视图及俯视平面图； 
图16是根据本发明的实施例图15A及15B的部分形成的集成电路在所述线图案被转移到所述第二及第三硬掩模层之后的示意性截面侧视图； 
图17是图16的部分形成的集成电路在堆叠心轴由各向同性及选择性蚀刻不同地修整之后的示意性截面侧视图。根据本发明的实施例，包含所述第二硬掩模层、第三硬掩模层及光可定义层的线界定第一、第二及第三心轴； 
图18是根据本发明的实施例图17的部分形成的集成电路在间隔物材料被保形地毯覆沉积在所述衬底上方之后的示意性截面侧视图； 
图19是根据本发明的实施例图18的部分形成的集成电路在所述间隔物材料被蚀刻以在所述心轴的侧壁上形成间隔物之后的示意性截面侧视图； 
图20是根据本发明的实施例图19的部分形成的集成电路在所述第一、第二及第三心轴的暴露部分被蚀刻掉从而在所述第一硬掩模层上方留下线图案之后的示意性截面侧视图； 
图21是根据本发明的实施例图20的部分形成的集成电路在所述线图案被转移到所述第一硬掩模层及所述转移层之后的示意性截面侧视图； 
图22A及22B是根据本发明的实施例图21的部分形成的集成电路在所述线图案被转移到所述衬底、所述硬掩模及转移层被移除且所述线的终端被蚀刻掉以留下隔离的线之后的示意性截面侧视图及俯视平面图；及 
图23A-23C是根据本发明实施例的部分形成的集成电路的示意性俯视平面图，其显示据以提供到根据图2-22B的方法形成的线的接触的方法。 
应了解，所述图式及其中的特征未按比例绘制。 
具体实施方式
间距倍增因数4
参照图2A，在一实施例中，在安置在多个层上方的光可定义层81中形成特征图案，所述多个层从顶部到底部包括第一硬掩模层82、第二硬掩模层83、第三硬掩模层84及衬底85。所述衬底可包括将要图案化或掺杂的晶片的顶部半导体层或一部分、将要图案化的导电层或将要图案化的绝缘体以形成(例如)镶嵌特征。尽管所图解说明的实施例包含第一、第二及第三硬掩模层82-84，但应了解，可如需提供其它层。第三硬掩模层84也可称作“蚀刻终止”或“转移层”。另外，尽管编号为第一、第二及第三(从顶部到底部)，但可容易地以相反顺序使用所述术语。 
应了解，所述方法实施例可用于图案化半导体晶片上方的导电层(例如，Si、多晶硅、Al、W、WSix、Ti、TiN等)以形成导线，图案化半导体晶片或半导体晶片上方的绝缘体(例如，SiO2)以形成镶嵌特征。 
参照图2B，使用对包含第一及第二硬掩模层82及83的材料具有选择性的蚀刻化学物来将所述特征图案转移到第一及第二硬掩模层82及83。也就是说，所述蚀刻化学物以比包围层(例如，暴露的第三硬掩模层84)快的速率蚀刻第一及第二硬掩模层82及83。所述图案转移可同时移除光可定义层81，或可在单独的步骤中将其移除。接下来，各向同性地蚀刻(或“修整”)第一硬掩模层82，如图2C中所示。包含第一及第二硬掩模层82及83的特征分别界定多个第一心轴86及多个第二心轴87。所述第一心轴平行于所述第二心轴延伸。尽管未显示，在其它布置中，如果需要增加第二心轴87之间的间隔那么也可修整所述第二心轴，但其保持宽于上覆的第一心轴86。 
在所图解说明的实施例中，第一及第二心轴86及87是定向于页的平面中的平行线。每一第一心轴86可具有比对应的下伏第二心轴87的第二宽度小的第一宽度。可大致将第一心轴86安置在第二心轴87上。在一实施例中，第一心轴86相对于第二心轴87居中。 
接下来，参照图2D，同时在第一及第二心轴86及87的侧壁上形成间隔物88。如所属技术中已知，可通过保形沉积及间隔物层的水平部分的各向异性(或方向性)选择性移除来形成此类间隔物。 
参照图2E，蚀刻第一及第二心轴86及87的暴露部分89以形成间隔物图案90。然后，可使用间隔物图案90作为硬掩模。举例来说，随后可将图案90转移到第三硬掩模层84(如图2F中所示)，从而在第三硬掩模层84中形成线84a图案。因此，间距倍增因数4(相对于在光可定义层中形成的特征图案)的特征图案在所述衬底上方形成。第三硬掩模层84将充当将线84a图案转移到衬底85的掩模。应了解，此最低级的硬掩模是任选的，但在创建低轮廓、短掩模特征时有利，以最小化纵横比决定蚀刻(ARDE)的效应及/或原本因直接使用图2E的结构作为掩模来处理衬底85而产生的微负载效应。 
参照图3-12，在本发明的实施例中，图解说明用于形成间距倍增因数4的特征的工艺。除采用初始光可定义层作为心轴层中的一者以外，所述工艺类似于图2A-2F的工艺。图3显示部分形成的集成电路100的截面侧视图。 
继续参照图3，在衬底110上提供各种掩蔽层120-150。将使用层120-150来形成用于图案化衬底110的掩模，如下文所论述。可基于化学物及工艺条件的考虑来为本文中所论述的各种图案形成及图案转移步骤选择上覆于衬底110上的层120-150的材料。由于最顶部的选择性可定义层150与衬底110之间的层可用于将图案转移到衬底110，因此可选择选择性可定义(例如，光可定义)层150与衬底110之间的层120-140中的每一者，使得可相对于其它暴露材料选择性地对其进行蚀刻。由于上覆于衬底110上的层120-150的目标是允许在衬底110中形成经良好界定的图案，因此应了解，如果使用合适的材料、选择性蚀刻化学物及/或工艺条件，那么可替代层120-150中的一者或一者以上。另外，应了解，可在衬底110上方添加额外掩蔽层以形成相对于衬 底110具有改善的蚀刻选择性的掩模。举例来说，如果层150是硬掩模层，那么可在层150上方提供额外的光可定义层(未显示)。本文中所论述的各种层的实例性材料包括氧化硅(例如，SiO2)、金属氧化物(例如，Al2O3)、氮化硅(Si3N4)、多晶硅(polySi)、无定形硅(a-Si)、无定形碳(a-C)及电介质抗反射涂布(DARC，富硅氮氧化硅)，其中每一者可相对于其它材料中的至少三者可靠且选择性地蚀刻。 
继续参照图3，集成电路100从底部到顶部包含衬底110、转移层120、硬掩模层130、另一硬掩模层(在本文中还称作“临时层”)140及光可定义(或光致抗蚀剂)层150。衬底110可以是硅晶片、另一半导电材料的晶片或包括半导电材料层的另一体衬底。在某些实施例中，衬底110可包含额外的层及特征(未显示)。光致抗蚀剂层150可由任何光致抗蚀剂材料形成，包括所属技术中已知的光致抗蚀剂材料。光致抗蚀剂层150可与(例如)157nm、193nm、248nm或365nm波长的光学扫描仪、193nm波长的浸没系统、极紫外系统(包括13.7nm系统)或电子束光刻系统兼容。合适的光致抗蚀剂材料的实例包括对氟化氩(ArF)敏感的光致抗蚀剂(即适合与ArF光源一同使用的光致抗蚀剂)，及对氟化氪(KrF)敏感的光致抗蚀剂(即适合与KrF光源一同使用的光致抗蚀剂)。在其它实施例中，层150及任何后续抗蚀剂层可由可通过纳米压印光刻法图案化的抗蚀剂形成，例如通过使用模型或机械力来图案化所述抗蚀剂。作为一个实例，光致抗蚀剂150可包含(例如)化学放大抗蚀剂材料，例如来自富士胶卷奥林株式会社(FUJIFILM OLIN Co.，Ltd)的FEP-171或来自东京应化工业株式会社(Tokyo Ohka Kogyo Co.，Ltd)的EP-009。 
根据本发明的实施例，采用较长波长的光学扫描仪用于实现处理成本的减小。根据本发明实施例的方法实现使用分辨率限制大于150nm或大于200nm的光刻系统来得到所述分辨率限制的一半、四分之一、六分之一等的特征大小。举例来说，可使用248nm的光学扫描仪来实现使用157nm的扫描仪或甚至更小可获得的相同特征间隔(例如，线或沟槽间隔)。 
继续参照图3，基于为其它层及衬底110选择的材料来选择层120-150中的每一者的材料，所有所述材料经选择使得选择性蚀刻化学物可供下文中所说明的蚀刻步骤使用。作为实例，在层150为光致抗蚀剂层的情况下，临时层140可由硅(例如，无定形硅)形成，硬掩模层130可由氮化硅(Si3N4)形成，且转移层120可由无定形碳或多晶硅/二氧化硅双分子层形成。表1列举层120-150中的每一者的材料的合适组合。应了解，层120-150中的每一者的其它材料也是可行的。 
表1. 
Figure G2007800379938D00081
Figure G2007800379938D00091
如果层150不是光致抗蚀剂层(组合2-5)，那么可在硬掩模层120-150的最顶部上方提供光致抗蚀剂层。举例来说，如果层150由a-C形成，那么可在所述a-C层上方提供光可定义层(除其它层以外，如果需要)。尽管在表1中提供材料与层的某些组合的实例，但应了解，材料与层的其它组合归属于本发明实施例的范围内。 
可使用所属技术中已知的任何沉积技术来施加转移层120、硬掩模层130及临时层140，所述沉积技术包括但不限于旋涂沉积、化学气相沉积(CVD)、数字CVD、原子层沉积(ALD)、等离子增强型ALD(PEALD)及物理气相沉积(PVD)。通常通过旋转涂敷来施加光可定义层150。 
已形成所需的层堆叠120-150时，接下来通过间距倍增来形成间隔物图案。在下文所说明的实施例中，根据表1的组合选择层120-150。尽管下文提供的蚀刻化学物适用于此组合，但应了解可将所述蚀刻化学物应用于其它组合。 
参照图4A及4B，在光可定义层150中形成包含间隔或沟槽175的图案170，所述间隔或沟槽可被由光可定义材料形成的特征150a定界。图4B是进行中(或部分形成)的集成电路100在图案170在光可定义层150中形成之后的示意性俯视平面图。图4A是沿图4B的线4A-4A截取的截面图。可使用248nm或193nm的光通过(例如)光刻法来形成沟槽175，其中将光可定义层150暴露给穿过光罩的辐射且然后使其显影。在被显影之后，剩余的光致抗蚀剂材料形成掩模特征，例如线150a。 
如图所示，特征150a可包含平行且伸长的线，其中其平行长度是其宽度的至少10倍，更通常是其宽度的至少100倍。尽管其大部分长度平行，但从图25A-25C(在下文中说明)的说明应了解，所述线可包括特别用以促进接触的弯曲或转弯。所述特征对于形成(例如)用作存储器阵列上的逻辑中的导线的规则线阵列最有用。 
参照图5，将光可定义层150中的图案170转移到临时层140，从而创建对应的线140a。在所图解说明的实施例中，“a”指示间距。可使用对层140及150的材料具有选择性的各向异性(或方向性)蚀刻来完成此转移。在一个实施例中，所述图案转移包含使用相对于层130及150对层140的材料具有选择性的蚀刻化学物。可使用(例如)溴化氢(HBr)等离子来完成所述图案转移。在所图解说明的实施例中，所述蚀刻化学物不显著地移除包含层130的材料，其在所图解说明的实施例中充当蚀刻终止。 
参照图6A及6B，通过相对于线140a及硬掩模层130进行各向同性及选择性蚀刻以形成线150b来“修整”线150a。图6B是集成电路100在线150a的蚀刻之后的示意性俯视平面图。图6A是沿图6B的线6A-6A截取的截面图。在一个实施例中，所述各向同性蚀刻不蚀刻层130及线140a。另一选择为，也可通过同一蚀刻或单独的蚀刻更小程度地修整下伏线140a。基于层130及线140a及150a的材料来选择蚀刻化 学物。可使用(例如)O2/Cl2、O2/HBr等离子或O2/SO2/N2等离子来各向同性蚀刻所图解说明光致抗蚀剂的线150a。 
继续参照图6A及6B，线140a及150b分别界定第一及第二心轴。心轴140a及150b将充当间隔物的占位符(参见下文)。 
接下来，参照图7及8，同时在心轴140a及150b的侧壁上形成间隔物。 
参照图7，保形地在暴露的表面(包括硬掩模层130及第一及第二心轴140a及150b的顶部及侧壁)上方保形毯覆沉积间隔物材料层180。层180可具有约等于将要从层180形成的所需间隔物宽度的厚度，从而计及因后续处理步骤(例如，间隔物蚀刻或心轴移除)而可发生的任何尺寸改变。层180可由(例如)氧化物(SiO2、Al2O3、HfO2)或氮氧化硅形成。间隔物层180可相对于硬掩模层130及第一及第二心轴140a及150a选择性地可蚀刻。 
接下来，参照图8，间隔物层180经受各向异性(或方向性)蚀刻以从部分形成的集成电路100的水平表面优先移除间隔物材料。在SiCO2间隔物材料的情况下，可使用(例如)采用含CF4、CHF3及/或CH2F2等离子的反应性离子蚀刻(RIE)来执行此种方向性蚀刻(还称作间隔物蚀刻)。所述蚀刻化学物可对包含间隔物层180的材料具有选择性。 
继续参照图8，间隔物185的宽度由“B”表示，第一心轴140a的宽度由“C”表示且第二心轴150b的宽度由“D”表示。在一个实施例中，“B”可小于或等于(C-D)/2。在另一实施例中，“B”可小于或等于(C-D)/3。在再一实施例中，“B”可约等于(C-D)/4。在某些实施例中，“B”经选择以具有大约相等的线/间隔图案。在一个实施例中，“B”约等于“D”。间隔物宽度“B”由用于形成间隔物185的处理条件(例如，沉积厚度、蚀刻化学物、暴露时间)确定。 
应了解，图8中所示特征的位置及宽度将控制最终形成的掩模特征的位置及宽度(参见图10及11)及衬底110中的最终图案(参见图12A及12B)。 
接下来，参照图9及10，选择性地移除第一及第二心轴140a及150b的暴露部分(即，心轴140a及150b未被间隔物185覆盖的若干部分)以留下自支撑的间隔物。所述自支撑间隔物界定间隔物图案190。所述图式显示延伸进并延伸出所述页的线图案190的截面图。在一个实施例中，使用选择性地移除第一及第二心轴140a及150b的单个各向异性蚀刻化学物来执行心轴移除。在所图解说明的实施例中，使用第一蚀刻化学物移除第二心轴150b的暴露部分，此后使用第二蚀刻化学物移除第一心轴140a的暴露部分来执行心轴移除。作为实例，如果第一心轴140a由无定形硅形成且第二心轴150b由光致抗蚀剂材料形成，那么可使用含氧的等离子蚀刻心轴150b且使用HBr等离子蚀刻心轴140a。如包含硬掩模层130的材料(例如，Si3N4)，氧化硅间隔物185将抵抗两个蚀刻。 
接下来，参照图11，将间隔物图案190转移到层120及130，从而形成线120a及130a。可针对每一层使用选择性掩模蚀刻化学物连续完成(即，转移到层130，此 后转移到层120)或使用同一蚀刻化学物同时完成图案转移。作为实例，如果层130由Si3N4形成，那么所述蚀刻化学物可包含含氟的等离子，例如CHF3/O2/He等离子或C4F8/CO/Ar等离子。作为另一实例，如果层130由Al2O3或HfO2形成，那么可使用含BCl3的等离子。随后可使用可对层120的材料具有选择性的方向性蚀刻来蚀刻转移层120。作为实例，如果层120由无定形碳形成，那么可使用含硫磺及氧的等离子，例如SO2/O2等离子。 
如按从图10到11的顺序所图解说明，可在通过掩模蚀刻衬底110进行处理之前移除间隔物185及第一心轴140a的剩余部分以减小掩模特征的纵横比。举例来说，在间隔物185包含氧化硅(例如，SiO2)且第一心轴140a包含无定形硅的情况下，可使用湿式或干式蚀刻执行间隔物移除。取决于所选择的移除化学物，可在硬掩模层130的蚀刻之后但在蚀刻转移层120之前执行间隔物/心轴移除。可相对于硬掩模及转移层120、130选择性地移除心轴。 
接下来，参照图12A及12B，其中线120a及130a充当掩模，将图案190转移到衬底110以形成线191与衬底110中的间隔或沟槽192交替的图案190。图12B是集成电路100在图案转移之后的示意性俯视平面图。图12A是沿图12B的线12A-12A截取的截面图。尽管在所图解说明的实施例中，线120a及130a充当用于到衬底110的图案转移的掩模，但应了解，可移除线130a且线120a可充当所述掩模。可使用基于衬底的材料的蚀刻化学物来将图案190转移到所述衬底。作为实例，如果所述衬底包含硅，那么可使用各向异性蚀刻(例如，BCl3/Cl2或碳氟化合物等离子蚀刻)来通过形成于转移层120中的图案选择性地蚀刻衬底110。如果所述衬底在硅晶片上方包含SiO2(ILD)，那么可使用碳氟化合物等离子蚀刻化学物来形成镶嵌特征。如果所述衬底包含金属(例如，Al)，那么可使用基于氯的等离子来形成导线。随后可选择性地移除线120a及130a。作为替代方案，可使用在衬底110的顶表面处停止的化学机械抛光(CMP)来移除线120a及130a。 
继续参照图12B，可在阵列的端处通过回路端线195来连结线191。回路端线195是心轴线的终端处间隔物沉积的结果。注意，在上部心轴上的收缩或修整工艺期间，所述上部心轴在x及y两个方向(以及垂直)上收缩，从而产生所图解说明的同心间隔物回路。当然，当界定存储器阵列的线时，与其宽度相比，所述线比所显示的尺寸长得多。如果需要个别线，那么执行单独的掩模及蚀刻步骤(未显示)以移除间隔物图案(图10或11)或衬底110中的所得线191的终端回路端。举例来说，可施加掩模以保护线191(使终端及线195不被覆盖)且使用蚀刻化学物来移除线195。随后移除保护性掩模以给出图12C中所图解说明的线191图案190。另一选择为，对于镶嵌工艺，在转移到下部层之前(图11或12A及12B)，保护性掩模可阻断间隔物图案的端(图10或11)。 
因此，使用单个间隔物形成步骤在衬底110中形成间距倍增因数4的线191(例如，导线)图案190。如果集成电路100在间距倍增之前每一间隔“a”包括一个心轴 (参见图5)，那么在间距之后，间隔“a”包含四个线。 
应了解，线191的图案190在外围处可具有各种集成电路组件，例如焊接垫及未间距倍增的特征(例如，线)。在后续处理步骤中，可形成到线191的互连。 
在一个实施例中，线191彼此之间可间隔约50及100纳米(nm)。在另一实施例中，线191彼此之间可间隔约20及50nm。在某些实施例中，所述线之间的间隔可经选择以避免所述线之间的电短路。 
尽管已使用图3-12中所图解说明的工艺来形成线，但应了解，所述工艺可用于形成镶嵌特征。在此种情况下，衬底110可以是绝缘体(例如，SiO2)且间距倍增因数4的间隔192代表将要在所述绝缘体中形成的沟槽的位置，其可填充有导电材料。 
间距倍增因数6
将论述用于形成间距倍增因数6的特征(例如，线、间隔)图案的方法的实施例。 
参照图13A，在一实施例中，在安置在多个掩蔽层上方的光可定义层201中形成特征图案210，所述多个层从顶部到底部包括第一硬掩模层202、第二硬掩模层203、第三硬掩模层204、第四硬掩模层205及衬底206。如在先前的实施例中，所述衬底可包括将要图案化或掺杂的晶片的顶部半导体层或部分、将要图案化的导电层或将要图案化的绝缘体以形成(例如)镶嵌特征。在所图解说明的实施例中，所述特征是垂直于页的平面定向的线。尽管所图解说明的实施例包含第一、第二第三及第四硬掩模层202-205，但应了解，可提供其它硬掩模及临时层，例如额外的插入蚀刻终止层。 
应了解，本发明实施例的方法可用于图案化半导体晶片上方的导电层(例如，Si、多晶硅、Al、W、WSix、Ti、TiN等)以形成导线，图案化半导体晶片或半导体晶片上方的绝缘体(例如，SiO2)以形成镶嵌特征。 
参照图13B，使用单个蚀刻或一系列选择性蚀刻将特征图案210转移到第一、第二及第三硬掩模层202-204。接下来，参照图13C，各向同性地修整第一硬掩模层202。所述蚀刻化学物选择性地修整包含第一硬掩模层202的材料。所述各向同性蚀刻在第一硬掩模层202中形成改变的特征图案211。接下来，在第一硬掩模层202充当掩模的情况下，使用对包含第三硬掩模层203的材料具有选择性的各向异性(或方向性)蚀刻化学物来将所述改变的特征图案211转移到第二硬掩模层203，如图13D中所图解说明。接下来，参照图13E，各向同性且选择性地蚀刻(相对于第二及第三硬掩模层203及204)第一硬掩模层202。 
尽管参照特定的蚀刻顺序来说明图13B-13E，但所属领域的技术人员应了解可到达图13E的结构的其它蚀刻顺序。 
间距倍增工艺的此级处的线分别在第一、第二及第三硬掩模层202-204中界定第一、第二及第三心轴212-214。在一个实施例中，至少对于其大部分长度来说，所述第二及第三心轴平行于所述第一心轴延伸。接下来，在心轴212-214上保形地沉积间隔物材料且对其进行各向异性蚀刻以形成心轴212-214周围的间隔物215，如图13F中所示。接下来，在心轴212-214充当掩模的情况下，各向异性蚀刻心轴212-214的 暴露部分217以形成相对于在光可定义层201中形成的线(参见图13A)间距倍增因数6的线图案216，如图13G中所示。换句话说，在其中光刻法已界定一个线及一个间隔的间隔(图13A)中，现在界定六个线及六个间隔(图13G)。 
接下来，参照图13H，使用对包含第四硬掩模层205的材料具有选择性的蚀刻化学物来将线图案216转移到第四硬掩模层205。第四硬掩模层(或转移层)205将充当用于到衬底206(未显示)的后续图案转移或所述衬底的通过掩模的其它处理(例如，氧化、氮化、电掺杂、自对准硅化等)的所述掩模。 
图14-21图解说明根据本发明的另一实施例的用于形成间距倍增因数6的特征的工艺，其中光致抗蚀剂加倍以作为最顶部心轴。 
参照图14，部分形成的集成电路300从底部到顶部包含衬底310、转移层320、第一硬掩模层330、第二硬掩模层340、第三硬掩模层350及光可定义材料层360。转移层320将充当用于到衬底310的图案转移的最终掩模。在随后的处理步骤中，将在层340-360中形成心轴，其中层360中的心轴由光可定义材料形成。然而，如在图13A-13H中，层360可以是硬掩模层且集成电路300进一步包含上覆于层360上的光可定义层。 
继续参照图14，衬底310可包括将要图案化或掺杂的晶片的顶部半导体层或部分、将要图案化的导电层或将要图案化的绝缘体以形成(例如)镶嵌特征。光致抗蚀剂层360可由任何光致抗蚀剂材料(包括所属技术中已知的光致抗蚀剂材料)形成，且可与157nm、193nm、248nm或365nm波长的光学扫描仪、193nm波长的浸没系统、极紫外系统(包括13.7nm系统)或电子束光刻系统兼容。 
基于化学物及工艺条件的考虑来为本文中所论述的各种图案形成及图案转移步骤选择上覆于衬底310上的层320-360的材料。层320-360中的每一者可经选择，使得可相对于下文中所论述步骤的其它暴露材料对所述层进行选择性蚀刻。由于上覆于衬底310上的层320-360的目标是允许在衬底310中形成经良好界定的图案，因此应了解，如果使用合适的材料、化学物及/或工艺条件，那么可替代层320-360中的一者或一者以上。另外，应了解，可在衬底310上方添加额外掩蔽层以形成相对于衬底310具有改善的蚀刻选择性的掩模，例如额外的插入蚀刻终止层。作为实例，在层360由光可定义材料形成的情况下，层350可由BARC、旋涂有机膜或无定形碳形成；层340可由无定形硅形成；层330可由Si3N4形成；且层320可由无定形碳形成。所属领域的技术人员应了解，层320-360中的每一者的其它组合及排列也是可行的。 
参照图15A及15B，在光可定义层360中形成包含间隔或沟槽375的图案370，所述间隔或沟槽可被由光可定义材料形成的特征360a定界。图15B是进行中(或部分形成)的集成电路300在图案370在光可定义层360中形成之后的示意性俯视平面图。图15A是沿图15B的线15A-15A截取的截面图。可使用248nm或193nm的光通过(例如)光刻法来形成沟槽375，其中将光可定义层360暴露给穿过光罩的辐射且然后使其显影。层360可由具有比层350高的蚀刻速率(相对于所使用的特定化学 物)的材料形成(参见下文)。一般来说，较低分辨率的光刻系统(例如，248nm)系统可用于所图解说明的工艺，但仍实现较好的特征大小。在一个实施例中，层360由248nm抗蚀剂形成。在所图解说明的实施例中，间距由“E”指示。 
如图所示，特征360a可包含平行且伸长的线，其中其平行长度是其宽度的至少10倍，更通常是其宽度的至少100倍。尽管其大部分长度平行，但从图23A-23C(在下文中说明)的说明应了解，所述线可包括特别用以促进接触的弯曲或转弯。所述特征对于形成(例如)用于存储器装置中的规则线阵列最有用。 
参照图16，将光可定义层360中的线360a图案370转移到第二及第三掩模层340及350，从而创建线340a及350a。可使用对层340及350的材料具有选择性的各向异性(或方向性)蚀刻来完成此转移。在一个实施例中，所述图案转移包含使用对层350的材料具有选择性的第一蚀刻化学物，此后使用对层340的材料具有选择性的蚀刻化学物。在另一实施例中，可使用单个蚀刻化学物来蚀刻层340及350。作为实例，可使用SO2/O2/Ar/N2等离子蚀刻层350，此后使用HBr等离子蚀刻层340来完成图案转移。在所图解说明的实施例中，所述蚀刻化学物不显著地移除包含层330的材料，其在所图解说明的实施例中充当蚀刻终止。作为替代方案，可使用穿过层340及350的溅射蚀刻(例如，Ar溅射蚀刻)来完成图案转移，在此情况下将对溅射进行定时以不蚀刻层330。 
参照图17，通过相对于线340a及层330进行各向同性及选择性蚀刻以形成线360c及350b来修整线360a及350a。通过选择层360a及350a的材料的正确组合(参见图16)及适当的修整化学物，可在一个修整步骤中实现从图16到图17的转变，如所图解说明。如果层350a及350b是有机的，那么可使用O2/Cl2、O2/HBr或O2/SO2/N2等离子。另一选择为，可在多个修整步骤中不同程度地各向同性且选择性地修整不同级处的不同心轴材料以到达图17的结构。 
接下来，参照图18及19，同时在心轴340a及350b及360c的侧壁上形成间隔物。 
参照图18，保形地将间隔物材料层380保形毯覆沉积在集成电路300的暴露表面上方，所述暴露表面包括层330及心轴340a、350b及360c的顶部及侧壁。层380可具有约等于将要形成的所需间隔物385宽度的厚度(参见图19)，从而计及因后续处理步骤(例如，间隔物蚀刻或心轴移除)而可发生的任何尺寸改变。对于上述材料组合，层380可由(例如)氧化物(例如，SiO2、Al2O3、HfO2)或氮氧化硅形成。更一般来说，间隔物层380可相对于硬掩模层330及心轴340a、350b及360c选择性地可蚀刻。 
参照图19，间隔物层380经受各向异性(或方向性)蚀刻以从部分形成的集成电路300的水平表面移除间隔物材料。所述蚀刻化学物可对间隔物层380的材料具有选择性。针对所选择的材料组合，可使用(例如)采用含CF4、CHF3及/或NF3的等离子的RIE来执行此种方向性蚀刻(还称作间隔物蚀刻)。 
继续参照图19，间隔物385的宽度由“F”表示，第一心轴340a的宽度由“G”表示，第二心轴350b的宽度由“H”表示且第三心轴360c的宽度由“I”表示。间隔物宽度“F”将确定在衬底310中形成的特征之间的间隔。在一个实施例中，“F”可小于或等于(H-I)/2。在另一实施例中，“F”可小于或等于(H-I)/3。在再一实施例中，“F”可约等于(H-I)/4。“F”可经选择以便甚至获得线/间隔宽度。在一个实施例中，“G”与“H”之间的差(即，G-H)约等于“H”与“I”之间的差(即，H-I)。“I”可约等于“F”。间隔物宽度“F”由用于形成间隔物385的处理条件(例如，沉积厚度、蚀刻化学物、蚀刻时间)确定。 
应了解，图19中所示特征的位置及宽度将控制最终形成的掩模特征的位置及宽度(参见图20及21)及衬底310中的最终图案(参见图22A及22B)。 
接下来，参照图19-21，选择性地移除心轴340a、350b及360c的暴露部分(即，心轴340a、350b及360c不被间隔物385覆盖的若干部分)以留下自支撑的间隔物385。自支撑间隔物385界定间隔物图案390，其可界定将要在衬底310中形成的伸长线图案。所图解说明的实施例是延伸进并延伸出所述页的线图案390的截面图。可使用(例如)对层340-360中的至少一者具有选择性的蚀刻化学物或多个选择性蚀刻化学物来蚀刻所述心轴。作为实例，可使用SO2/O2/Ar/N2RIE蚀刻心轴350b及360c，此后使用HBr RIE等离子蚀刻心轴340a来完成图案转移。 
接下来，参照图21，将间隔物图案390转移到层320及330，从而形成线320a及330a。可使用对每一层具有选择性的蚀刻化学物连续完成(即，层330，此后是层320)或使用同一蚀刻化学物或物理(溅射蚀刻)同时完成图案转移。作为实例，如果层330由Si3N4形成，那么可使用含氟的等离子，例如CHF3/O2/He或C4F8/CO/Ar等离子。作为另一实例，如果层330由Al2O3或HfO2形成，那么可使用含BCl3的等离子。随后可使用可对包含层320的材料具有选择性的方向性蚀刻来蚀刻转移层320。作为实例，如果层320由BARC或无定形碳形成，那么可使用含硫磺的等离子，例如SO2/O等离子。 
如按从图20到21的顺序所图解说明，可在通过掩模处理(例如，蚀刻衬底)之前移除间隔物385及第一及第二心轴340a及350b的剩余部分，以减小掩模特征的纵横比。举例来说，如果间隔物385包含氧化硅(例如，SiO2)，第一心轴340a包含无定形硅且第二心轴350b包含无定形碳，那么可使用湿式或干式蚀刻(例如，湿式缓冲氧化物蚀刻或使用基于氟的等离子的干式蚀刻)来执行间隔物移除。作为替代方案，可使用旋涂填充物及化学物机械抛光(CMP)来移除间隔物385及心轴340a及350b。硬掩模层330可充当蚀刻终止阻挡层以保护转移层320内的图案390。取决于所选择的移除化学物，可在硬掩模层330的蚀刻之后但在蚀刻转移层320之前执行间隔物/心轴移除。可相对于硬掩模层330及转移层320选择性地移除心轴。 
接下来，参照图22A及22B，其中线320a及330a充当掩模，将图案390转移到衬底310以形成线391与衬底310中的间隔或沟槽392交替的图案390。图22B是集 成电路300在图案转移及用以移除线391的终端的单独掩模及蚀刻步骤之后的示意性俯视平面图(参见下文)。图22A是沿图22B的线22A-22A截取的截面图。尽管在所图解说明的实施例中，线320a及330a充当用于到衬底310的图案转移的掩模，但应了解，可移除线330a且线320a可充当所述掩模。 
继续参照图22A及22B，如果将要蚀刻的衬底是半导体晶片或导体，那么可使用各向异性蚀刻(例如，BCl3/Cl2等离子蚀刻)来完成图案转移，以通过在转移层320中形成的图案选择性地蚀刻衬底310。随后选择性地移除线320a及330a。作为替代方案，可使用化学机械抛光(CMP)来移除线320a及330a。 
执行后续掩模及蚀刻步骤以移除线391的终端。也就是说，施加掩模以保护线391(使终端不被覆盖)且使用蚀刻化学物来移除所述终端。随后移除所述保护性掩模以给出图22B中所图解说明的线391图案390。另一选择为，对于镶嵌工艺，在转移到下部层之前，保护性掩模可阻断间隔物回路的端(参见图12B及所附论述)。 
因此，线图案相对于形成于光可定义层360中的图案(参见图15A)间距倍增因数6。在集成电路300在间距倍增之前每一间隔“E”包括一个心轴及一个间隔或沟槽(参见图15A)的情况下，在间距倍增之后，间隔“E”包含六个线391及六个间隔或沟槽392。 
在一个实施例中，线390彼此之间可间隔约50及100纳米(nm)。在另一实施例中，线390彼此之间可间隔约20及50nm。在某些实施例中，所述线之间的间隔可经选择以避免所述线之间的电短路。 
参照图23A-23C，其图解说明用于形成到使用方法实施例形成的线的接触的步骤序列。所图解说明的序列是间距倍增因数4的线的接触形成的实例；然而，所属领域中的技术人员应了解，本文所教示的原理也可用于形成到间距倍增因数6、8等的线的接触。 
图23A是部分形成的集成电路400在形成心轴410及415之后的示意性俯视平面图。所述心轴界定伸长且间距倍增的线。所述间距倍增的线邻接未间距倍增的特征(例如，导线、接触或垫)。集成电路400可类似于图6A及6B中所示的集成电路。心轴415上覆于心轴410上，所述心轴由间隔420定界。心轴上覆于硬掩模层422(通过间隔420可看到)、转移层(未显示)及衬底425(参见图23C)上。所述衬底包含上覆于半导体晶片425上的导电层(例如，Si、多晶硅、Al、W、WSix、Ti、TiN等)(参见图23C)。集成电路400在心轴410及415的终端处包含回路或弯曲430。 
根据以上说明应了解，最初图案化(例如，通过光刻法)的垂直堆叠的心轴410、415具有相同的宽度。然而，在差别收缩或修整之后，使得上部心轴415比下部心轴410窄。相应地，选择具有较窄区段416的初始图案，使得所述修整工艺从那些较窄的区段416完全移除所述上部心轴，从而留下下部心轴410的没有任何上覆上部心轴的区段。此外，剩余下部心轴410包括此较窄区段416中下部心轴410的线之间的相对较宽的间隔窗口。在图23A的图解说明中，显示每一较窄区段416中有两个此类邻近窗口。如根据后续图式将了解，区段416中的较窄桥及宽窗口两个特征促进间距倍增的特征到未间距倍增的特征(例如，接触)的电连接。
此外，将图案的其它区段417制造得比所述线宽。在修整之后，上部心轴415保持比在阵列区段中宽。如根据后续图式将了解，在此类较宽区段417中形成的间隔物间隔得更远，从而也促进间距倍增的线使用未间距倍增的特征(例如，接触)的单独电连接。因此，如由界定阵列中的线的宽区段417、窄区段416及的中间区段中的三个不同宽度表明，初始图案包括沿所述图案变化的线宽度，以促进将由侧壁间隔物界定的特征之间的电连接。 
参照图23B，通过在心轴410及415上方保形毯覆沉积间隔物材料，此后通过方向性间隔物蚀刻(优先蚀刻毯覆保形间隔物层的水平段)以形成间隔物图案来形成间隔物431。间隔物431由图23B中心轴410、415的边缘上的厚黑色线代表。可执行修整及间隔物蚀刻，使得其不蚀刻硬掩模层422。点线箭头423指示将在那里切割(用于常规蚀刻)或阻断(用于镶嵌制作)导线426的位置(参见图23C)。掩模特征440(其可在图23C的导线426被界定之后由单独的接触掩模界定)充当将在图案转移到上覆于衬底425上的导电层之后形成的接合垫460的位置(参见下文)。所图解说明的箭头形状423跨越上述间隔的较宽窗口，使得常规光刻法可准确地放置阻断或切割掩模。 
接下来，参照图23C，将间隔物图案转移到上覆于衬底425上的导电层，且移除下伏于图23B中所示的箭头的线的若干部分以形成隔离的导线426。图23C的集成电路进一步包含用于建立到线426的电接触的接合垫460。 
尽管已使用图23A-23C中所图解说明的序列常规地蚀刻导线，但应了解，所述序列可用于蚀刻镶嵌特征的沟槽或绝缘(例如，SiO2)或半导电(例如，硅)衬底中的线。 
尽管已在某些实施例中图解说明了间距倍增的特征，但应了解，可随间距倍增的特征形成未间距倍增的特征(例如，焊接垫)。在某些情况下，未间距倍增的特征可上覆于间距倍增的特征上。 
因此，所属领域的技术人员应了解，可在不背离本发明的范围的情况下对上文所说明的方法及结构作出各种其它省略、添加及修改。举例来说，且并非限制，通过在线阵列(例如，在存储器阵列中)的背景下说明，本文中所教示的间距倍增技术将应用于各种各样的背景下。举例来说，本文中所教示的技术可应用于光学元件(例如，衍射光栅)、MEMS结构、边缘射极等。在这些应用中的某些应用中，不需要到间距倍增特征的电连接，从而甚至进一步简化所述应用。本文中所教示的方法用于将特征大小延伸到光可定义大小以下，但甚至应用于光学分辨率不受限制的情况，以采用较不昂贵的光刻系统。此外，应了解，本文中所说明的技术可延伸到更大数量的心轴级，且可与采用多个间隔物沉积步骤的技术组合，且可多次重复所述工艺以实现更复杂的图案。所有此类修改及改变既定归属于所附权利要求书所界定的本发明的范围内。 

Claims (53)

1.一种用于制作集成电路的方法，其包含：
在衬底上方提供第一心轴，所述第一心轴具有第一宽度；
在所述第一心轴上方提供第二心轴，所述第二心轴具有比所述第一宽度小的第二宽度且由与所述第一心轴不同的材料形成；
同时在所述第一及第二心轴的侧壁上形成间隔物；
选择性地移除所述第一心轴及所述第二心轴的相对于所述间隔物的至少若干部分以形成由所述间隔物界定的间隔物图案；及
通过由所述间隔物图案界定的掩模处理所述衬底。
2.如权利要求1所述的方法，其中处理包含蚀刻以将所述间隔物图案转移到所述衬底。
3.如权利要求2所述的方法，其进一步包含将所述间隔物图案转移到下部硬掩模层及在处理之前移除所述间隔物。
4.如权利要求3所述的方法，其中所述衬底包含上部层间电介质层且通过所述掩模处理形成镶嵌沟槽。
5.如权利要求4所述的方法，其中所述间隔物图案包含具有连接的回路端的伸长线，且所述方法进一步包含在处理之前阻断所述回路端。
6.如权利要求3所述的方法，其中在所述衬底上方提供所述第一心轴包含在导体上方提供所述第一心轴。
7.如权利要求6所述的方法，其中所述间隔物图案包含具有连接的回路端的伸长线，且所述方法进一步包含在处理之前移除所述回路端。
8.如权利要求1所述的方法，其中提供所述第二心轴包含提供平行于所述第一心轴延伸的所述第二心轴。
9.如权利要求1所述的方法，其中提供所述第二心轴包含提供相对于所述第一心轴居中的所述第二心轴。
10.如权利要求1所述的方法，其中同时形成所述间隔物提供具有比所述第一宽度小的第三宽度的间隔物。
11.如权利要求1所述的方法，其中提供所述第二心轴包含使用分辨率限制大于200nm的光刻法。
12.如权利要求1所述的方法，其进一步包含在所述第二心轴上提供第三心轴，所述第三心轴具有第三宽度。
13.如权利要求12所述的方法，其中提供所述第三心轴包含提供具有比所述第二宽度小的所述第三宽度的所述第三心轴。
14.如权利要求13所述的方法，其中提供所述第三心轴包含提供相对于所述第二心轴居中的所述第三心轴。
15.如权利要求1所述的方法，其中选择性地移除包含移除所述第一心轴的若干部分。
16.如权利要求1所述的方法，其中选择性地移除包含留下所述第一心轴的直接在所述第二心轴的所述侧壁上的间隔物下方的若干部分。
17.如权利要求1所述的方法，其中形成间隔物包含在所述衬底的表面上毯覆沉积间隔物材料。
18.如权利要求1所述的方法，其中同时形成间隔物包含提供具有小于或等于所述第一宽度的半倍减去所述第二宽度的半倍的宽度的间隔物。
19.如权利要求1所述的方法，其中提供所述第一心轴包含图案化光致抗蚀剂层，且其中提供所述第二心轴包含通过经图案化的光致抗蚀剂层蚀刻一层第二心轴材料。
20.如权利要求19所述的方法，其进一步包含在蚀刻所述一层第二心轴材料之后各向同性地蚀刻所述经图案化的光致抗蚀剂层。
21.一种用于使用分层的心轴沿一个维度形成间距倍增因数2n的线图案的方法，其包含：
在衬底上方提供n层堆叠心轴，其中n≥2，所述n层中的每一者包含多个伸长心轴，所述多个伸长心轴对于其大部分长度而言彼此平行，其中层n处的心轴在层n-1处的心轴上方且平行于层n-1处的所述心轴，其中层n处的邻近心轴之间的距离大于层n-1处的邻近心轴之间的距离，其中直接相邻的心轴由不同的材料形成；及
同时在所述心轴的侧壁上形成间隔物。
22.如权利要求21所述的方法，其中提供n层堆叠心轴包含提供层n处的与层n-1处的心轴直接接触的心轴。
23.如权利要求21所述的方法，其中提供n层堆叠心轴包含提供层n处的在层n-1处的心轴上方居中的心轴。
24.如权利要求21所述的方法，其进一步包含选择性地移除所述心轴的相对于所述间隔物的至少若干部分以形成由所述间隔物界定的间隔物图案。
25.如权利要求24所述的方法，其进一步包含将所述间隔物图案转移到所述衬底以形成所述间距倍增因数2n的线图案。
26.如权利要求25所述的方法，其中将所述间隔物图案转移到所述衬底包含形成界定沟槽的所述线图案。
27.如权利要求21所述的方法，其中提供n层堆叠心轴包含提供界定线的心轴。
28.如权利要求21所述的方法，其中提供n层堆叠心轴包含提供层n处的比层n-1处的个别心轴窄的个别心轴。
29.如权利要求21所述的方法，其进一步包含在所述衬底与所述心轴之间提供一个或一个以上硬掩模层。
30.如权利要求21所述的方法，其进一步包含在所述衬底与所述心轴之间提供转移层。
31.如权利要求21所述的方法，其中在所述衬底上方提供n层堆叠心轴包含在半导体晶片上方提供n层堆叠心轴。
32.如权利要求31所述的方法，其中在所述衬底上方提供n层堆叠心轴包含在所述半导体晶片上方包含层间电介质层的衬底上方提供n层堆叠心轴。
33.一种部分形成的集成电路，其包含上覆于衬底上的掩模，所述掩模包含：
所述衬底上方的第一心轴，所述第一心轴具有第一宽度A，及所述第一心轴上方的第二心轴，所述第二心轴具有第二宽度B，其中A＞B，其中所述第一心轴由与所述第二心轴不同的材料形成；及
所述第一心轴及所述第二心轴的侧壁上的间隔物，所述间隔物具有间隔物宽度C，其中
Figure FSB00000387658100031
34.如权利要求33所述的部分形成的集成电路，其中所述第二心轴在所述第一心轴上方。
35.如权利要求33所述的部分形成的集成电路，其中
Figure FSB00000387658100032
36.如权利要求35所述的部分形成的集成电路，其中
Figure FSB00000387658100033
37.如权利要求33所述的部分形成的集成电路，其中所述第二心轴相对于所述第一心轴居中。
38.如权利要求33所述的部分形成的集成电路，其进一步包含所述第二心轴上方的第三心轴，所述第三心轴具有第三宽度，其中所述第三宽度小于所述第二宽度。
39.如权利要求38所述的部分形成的集成电路，其中所述第三心轴相对于所述第二心轴居中。
40.如权利要求33所述的部分形成的集成电路，其中所述第一及第二心轴为平行线。
41.如权利要求33所述的部分形成的集成电路，其中所述间隔物界定间隔物图案。
42.如权利要求41所述的部分形成的集成电路，其中所述间隔物图案包含用于NAND快闪存储器的控制栅极堆叠的特征。
43.如权利要求41所述的部分形成的集成电路，其中所述间隔物图案包含逻辑阵列的特征。
44.如权利要求41所述的部分形成的集成电路，其中所述间隔物图案包含栅极阵列的特征。
45.如权利要求41所述的部分形成的集成电路，其中所述间隔物图案包含存储器阵列的特征。
46.如权利要求41所述的部分形成的集成电路，其中所述间隔物图案包含动态随机存取存储器(DRAM)装置的特征。
47.一种掩蔽工艺，其包含：
在两个或两个以上堆叠膜上方界定图案；
将所述图案转移到所述两个或两个以上堆叠膜中；
相对于所述两个或两个以上堆叠膜中的下部膜减小至少一上部膜的元件的尺寸以产生两个或两个以上堆叠心轴；及
同时在所述堆叠心轴的侧壁上形成侧壁间隔物。
48.如权利要求47所述的工艺，其中界定所述图案包含光刻法。
49.如权利要求47所述的工艺，其中界定所述图案包含形成窄区段，所述窄区段的宽度经选择以使得在减小尺寸时在所述窄区段中移除所述上部膜，而在减小尺寸之后在所述图案的其它区段中所述上部膜仍留作心轴。
50.如权利要求47所述的工艺，其中界定所述图案包含形成宽区段，所述宽区段的宽度经选择以分离形成于所述宽区段中的侧壁间隔物，使得光刻法可界定到由所述宽区段中的所述侧壁间隔物界定的特征的接触，而光刻法不能够单独地接触由所述图案的其它区段中的所述侧壁间隔物界定的特征。
51.如权利要求47所述的工艺，其中界定所述图案包含沿所述图案改变线的宽度以促进由所述侧壁间隔物界定的特征之间的电连接。
52.如权利要求47所述的工艺，其中界定所述图案包含在所述图案的窗口区段中的所述下部膜的邻近段之间包括窗口，以相对于在由所述图案的其它区段中的所述下部膜界定的心轴上形成的间隔物的间隙增加在由所述窗口区段中的所述下部膜界定的心轴上形成的间隔物的间隙。
53.如权利要求52所述的工艺，其中所述窗口区段包含邻近窗口，所述邻近窗口准许间隔物的横向间隙足以实现到由所述间隔物界定的特征的未间距倍增的接触。
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US8883644B2 (en) 2014-11-11
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US20080057692A1 (en) 2008-03-06
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US8557704B2 (en) 2013-10-15
US20150054168A1 (en) 2015-02-26
US20100029081A1 (en) 2010-02-04
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