CN101566669B - Semiconductor integrated circuit device, and device and method for reliability test thereof - Google Patents
Semiconductor integrated circuit device, and device and method for reliability test thereof Download PDFInfo
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Abstract
The invention discloses a semiconductor integrated circuit device and a device and a method for a reliability test thereof. The circuit device comprises an either-or circuit module, three triggers and a voter. The device realizes the function of a scan trigger while realizing triple module redundancy of a storage node, and improves the reliability and mensurability of a semiconductor integrated circuit chip with lower cost by a simple digital logic circuit.
Description
Technical field
The present invention relates to the SIC (semiconductor integrated circuit) technical field, particularly relate to highly-reliable semiconductor integrated circuit (IC) design field and test of semiconductor integrated circuit field, more particularly, the present invention relates to a kind of highly reliable conductor integrated circuit device and RTA reliability test assembly and method of testing.
Background technology
Design field at semiconductor integrated circuit chip, along with present integrated circuit scale enlarges day by day, the number of transistors of being held on the single IC for both is more and more, even functional module such as processor core, storer, DSP nuclear also is integrated into and forms SOC (System on Chip, SOC (system on a chip)) in the one chip.This makes the complexity of integrated circuit increase.And according to the basic concept in fault-tolerant field, complicated more system reliability is low more.On the other hand, the characteristic dimension of integrated circuit presents decline trend, and this has caused the probability that failure conditions such as electromigration, gate oxide breakdown take place to increase, thereby causes permanent fault; The integrated circuit that has small-feature-size simultaneously also is easier to be subjected to the influence of high energy particle ray etc., single particle effect occurs, forms the various faults that comprises " soft error ".
Above-mentioned reason makes reliability become the problem that must solve in the integrated circuit (IC) design.
The method of triplication redundancy is the memory nodes such as method, especially trigger of the raising IC reliability used always, the reliability that the method for triplication redundancy and voting can very effective raising integrated circuit (IC) chip.But because triplication redundancy makes that the fault of redundancy logic can't be sifted out, so reduced the reliability of system to a certain extent to the tolerance of mistake.
Field tests at semiconductor integrated circuit chip, the SIC (semiconductor integrated circuit) measurability is also along with the complexity increase of integrated circuit becomes more and more difficult, only adopt the covering of function vector to be difficult to filter out fault in the chip, the fault in the redundancy logic can't detect especially.In field tests, the method that the insertion scan chain is tested is by industry-wide adoption.Its method is to substitute conventional trigger with sweep trigger, and sweep trigger is connected in one or several scan chain, generates scan-data (also claiming the scanning vector) with particular tool, with scan clock scan-data is delivered on each sweep trigger.Observation scanning is exported the result and is compared with expected results then, thereby finds fault.Can generate multiple scan-data by tool using, thereby cover how possible mistake as far as possible.
But the expense of changing conventional trigger with sweep trigger is very large.In the circuit that adopts Scan Design, scanning element and its control circuit can account for 30% of the chip total area.Even in memory unit occupies the majority the microprocessor chip of area, scanning element and the shared silicon area of its control circuit remain very big with respect to combinational logic circuit.And scan testing methods commonly used can't be tested the mistake in the redundancy logic.
The way of triplication redundancy has improved the quantity of memory node in the integrated circuit greatly, thereby has increased chip area significantly.If the trigger of triplication redundancy is all replaced with sweep trigger, chip area can be bigger, and the increase of chip area more can bring the reduction of its reliability.
Summary of the invention
The object of the present invention is to provide a kind of conductor integrated circuit device and reliability device and method of testing, it has realized the function of sweep trigger when realizing triplication redundancy, save chip area, and improves the reliability of semiconductor integrated circuit chip.
A kind of conductor integrated circuit device comprises at least one RTA reliability test assembly, and described RTA reliability test assembly comprises an alternative circuit module, three triggers and a voting machine;
The output terminal of described alternative circuit module is connected respectively to the data input pin of described three triggers;
The output terminal of described three triggers is connected respectively to three input ends of described voting machine;
The clock end of described three triggers does not connect, and they are driven by the clock trees of three SIC (semiconductor integrated circuit) respectively.
Described clock trees is clock trees CK0, CK1, the CK2 of SIC (semiconductor integrated circuit).
Described voting machine is a kind of three input voting circuit devices.
Described three clock trees are carried out bifurcated and control in the starting point of this clock trees then by clock of a pin input of conductor integrated circuit device.
Described three clock trees are by a plurality of pins input of conductor integrated circuit device, control separately each clock unlatching, close with being connected of other clocks.
Described integrated circuit (IC) apparatus also comprises at least one scan chain, and described scan chain gets up the output of the data of each grade RTA reliability test assembly with the scan-data input link of next stage RTA reliability test assembly.
Described conductor integrated circuit device is the semiconductor digital integrated circuit.
For realizing that the object of the invention also provides a kind of RTA reliability test assembly of conductor integrated circuit device, comprises an alternative circuit module, three triggers and a voting machine;
The output terminal of described alternative circuit module is connected respectively to the data input pin of described three triggers;
The output terminal of described three triggers is connected respectively to three input ends of described voting machine;
The clock end of described three triggers does not connect, and they are driven by the clock trees of three SIC (semiconductor integrated circuit) respectively.
For realizing that the object of the invention more provides a kind of method for testing reliability of conductor integrated circuit device, comprises the steps:
Steps A, three clock trees opening and closing states of control SIC (semiconductor integrated circuit) are by the scan chain of SIC (semiconductor integrated circuit), to the trigger initialize of reliability device;
Step B, the closed portion clock, unlatching also connects remaining clock, carries out sweep test.
Step C, repeating step A up to finishing the test combination, test out the fault in the SIC (semiconductor integrated circuit) to the operation of step B.
In the described steps A, the described trigger initialize of giving comprises the steps:
Under scanning mode, three clock trees of SIC (semiconductor integrated circuit) are all opened and connection, put normal value " 0 " and scan the long enough time at the scan chain input end, thereby give all trigger initializes " 0 ".
Among the described step B, carry out sweep test, comprise the steps:
Close clock CK0, open and connection clock CK1 and CK2, carry out sweep test.
In the described steps A, the described trigger initialize of giving comprises the steps:
Under scanning mode, earlier all trigger initializes " 0 ", turn off CK0 then, put normal value " 1 " and scan the long enough time at the scan chain input end, final result is that the trigger initial value of CK0 correspondence is " 0 ", the initial value of other triggers is " 1 ".
Among the described step B, carry out sweep test, comprise the steps:
Close clock CK0 and CK1, open clock CK2, carry out sweep test.
Among the described step C, test out the fault in the SIC (semiconductor integrated circuit), comprise the steps:
If the test result of all test combinations is all consistent, then prove absolutely not have fault in the chip;
If have the test result under arbitrary or several combination inconsistent, illustrate to have fault.
The invention has the beneficial effects as follows: the reliability device and the method for testing of SIC (semiconductor integrated circuit) of the present invention, realized the sweep test of the SIC (semiconductor integrated circuit) of triplication redundancy reliability reinforcing has been solved the problem that can't detect the redundancy logic mistake in the common sweep test with less area overhead.Thereby reach the purpose that improves the semiconductor integrated circuit chip reliability.
Description of drawings
Fig. 1 is the RTA reliability test assembly circuit diagram of conductor integrated circuit device of the present invention;
Fig. 2 is the workflow diagram of method of testing of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, a kind of conductor integrated circuit device of the present invention and RTA reliability test assembly thereof and method of testing are further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Conductor integrated circuit device of the present invention and RTA reliability test assembly thereof and method of testing, with the less area cost, when improving the memory node reliability, by control respectively to clock, fault in the redundancy logic can be detected, thereby guarantee the reliability of SIC (semiconductor integrated circuit).
To achieve these goals, the invention provides a kind of conductor integrated circuit device, comprise scan chain, it also comprises at least one RTA reliability test assembly, as shown in Figure 1, this RTA reliability test assembly comprises 11, three triggers of an alternative circuit module 12,13 and 14, and a voting machine 15.
Comprise scan chain in the conductor integrated circuit device, scan chain gets up the output of the data of each grade RTA reliability test assembly with the scan-data input link of next stage RTA reliability test assembly.
The output terminal of alternative circuit module 11 is connected respectively to the data input pin of three triggers 12,13 and 14;
Three triggers 12,13 and 14 output terminal are connected respectively to three input ends of voting machine 15;
Three triggers 12,13 are not connected with 14 clock end, and they are driven by clock trees CK0, CK1 and the CK2 of three SIC (semiconductor integrated circuit) respectively;
Described alternative circuit module, trigger and voting machine all are typical circuit in the integrated circuit (IC) design field.
The alternative circuit module is a circuit module commonly used in the existing reliability testing circuit, is used under scanning mode, and its data output is from scan data input terminal; And in normal operation, it is exported from data input pin.The effect that is the alternative circuit module is that the selection integrated circuit (IC) apparatus is to work or work in normal operation under the reliability testing state.
Described voting machine can be any three input voting circuit devices.
The effect of voting machine comes from the notion of triplication redundancy, so-called triplication redundancy data in other words is stored in three positions, if the data of a certain position are because certain reason is wrong, so because the existence of voting machine is arranged, output time these three positions data through voting, can finally provide correct data (mistake of two correct VS=correct result).
As a kind of embodiment, described three clock trees CK1, CK2, CK3 can carry out bifurcated and control in the starting point of this clock trees then by clock of a pin input of semiconductor integrated circuit chip device.
As another kind of embodiment, described three clock trees CK1, CK2, CK3 can be generated by additive method, by the input of a plurality of pins, can control separately each clock unlatching, close and it and being connected of other clocks.
Described RTA reliability test assembly is the memory circuit of triplication redundancy when operate as normal, plays the effect of trigger.
Described RTA reliability test assembly can be realized the sweep test of flowing water inter-stage combinational circuit and the test of redundancy logic self by controlling three clock trees ends respectively under scanning mode.
Described conductor integrated circuit device can be the semiconductor digital integrated circuit of various functions and type.
The present invention also provides a kind of SIC (semiconductor integrated circuit) method for testing reliability, below in conjunction with Fig. 2 the SIC (semiconductor integrated circuit) method for testing reliability course of work of the present invention is described in detail.This method comprises the following steps:
Step S100, three clock trees opening and closing of control SIC (semiconductor integrated circuit) state by the scan chain of SIC (semiconductor integrated circuit), is given the trigger initialize of RTA reliability test assembly under scanning mode;
As a kind of mode that can implement (mode M), can be under scanning mode (promptly " scan enable " is high), three clock trees of SIC (semiconductor integrated circuit) are all opened and connection, put normal value " 0 " and scan the long enough time at the scan chain input end, thereby give all trigger initializes " 0 ".
The mode (mode N) that can implement as another kind, also can be under scanning mode (promptly " scan enable " is high), earlier all trigger initializes " 0 ", turn off CK0 then, put normal value " 1 " and scan the long enough time at the scan chain input end, to be trigger 12 initial values be final result " 0 ", and trigger 13 and 14 initial value are " 1 ".
The unlatching of three clocks of SIC (semiconductor integrated circuit), close and be connected, be the existing integrated circuits designing technique, thereby describe in detail no longer one by one in the present invention.
Step S200, the closed portion clock, unlatching also connects remaining clock, carries out sweep test;
If adopt mode M to carry out initialize among the step S100, then can close clock CK0, open and connection clock CK1 and CK2, adopt common scan testing methods to carry out sweep test.
If adopt mode N to carry out initialize among the step S100, then can close clock CK0 and CK1, open clock CK2, adopt common scan testing methods to carry out sweep test.
Common scan testing methods is industry existing integrated circuits scan testing methods, thereby is not described in detail in the present invention.
Step 300, repeating step S100 up to finishing the test combination, tests out the fault in the SIC (semiconductor integrated circuit) to the operation of step S200.
If the test result of all test combinations is all consistent, then prove absolutely not have fault in the chip;
If there is the test result under arbitrary or several combination inconsistent, there is fault in explanation at least, and concrete failure location needs more scan test vector.
The generation of scan test vector is the part of common scan testing methods, is industry existing integrated circuits scan test vector generation method, thereby is not described in detail in the present invention.
In embodiments of the present invention, complete test combination can be following combination:
As another embodiment, complete test combination also can be following combination:
Conductor integrated circuit device of the present invention and RTA reliability test assembly thereof and method of testing, with the less area cost, when improving the memory node reliability, by control respectively to clock, fault in the redundancy logic can be detected, thereby guarantee the reliability of SIC (semiconductor integrated circuit).Adopt SIC (semiconductor integrated circuit) of the present invention can realize the high reliability and the high measurability of system with simple numerical logical circuit and less cost.
SIC (semiconductor integrated circuit) method for testing reliability of the present invention is realized simply only need adopting general DLC (digital logic circuit) to finish to the reinforcing of reliability, is simple and easy to use.
In conjunction with the accompanying drawings to the description of the specific embodiment of the invention, others of the present invention and feature are conspicuous to those skilled in the art by above.
More than specific embodiments of the invention are described and illustrate it is exemplary that these embodiment should be considered to it, and be not used in and limit the invention, the present invention should make an explanation according to appended claim.
Claims (18)
1. a conductor integrated circuit device is characterized in that, comprises at least one RTA reliability test assembly, and described RTA reliability test assembly comprises an alternative circuit module, three triggers and a voting machine;
The output terminal of described alternative circuit module is connected respectively to the data input pin of described three triggers;
The output terminal of described three triggers is connected respectively to three input ends of described voting machine;
The clock end of described three triggers does not connect, and they are driven by the clock trees of three SIC (semiconductor integrated circuit) respectively.
2. integrated circuit (IC) apparatus according to claim 1 is characterized in that, described clock trees is clock trees CK0, CK1, the CK2 of SIC (semiconductor integrated circuit).
3. integrated circuit (IC) apparatus according to claim 1 is characterized in that, described voting machine is a kind of three input voting circuit devices.
4. according to each described integrated circuit (IC) apparatus of claim 1 to 3, it is characterized in that described three clock trees are carried out bifurcated and control in the starting point of described clock trees then by clock of a pin input of conductor integrated circuit device.
5. according to each described integrated circuit (IC) apparatus of claim 1 to 3, it is characterized in that described three clock trees are by a plurality of pins input of conductor integrated circuit device, control separately each clock unlatching, close with being connected of other clocks.
6. according to each described integrated circuit (IC) apparatus of claim 1 to 3, it is characterized in that, also comprise at least one scan chain, described scan chain gets up the output of the data of each grade RTA reliability test assembly with the scan-data input link of next stage RTA reliability test assembly.
7. integrated circuit (IC) apparatus according to claim 6 is characterized in that, described conductor integrated circuit device is the semiconductor digital integrated circuit.
8. the RTA reliability test assembly of a conductor integrated circuit device is characterized in that, comprises an alternative circuit module, three triggers and a voting machine;
The output terminal of described alternative circuit module is connected respectively to the data input pin of described three triggers;
The output terminal of described three triggers is connected respectively to three input ends of described voting machine;
The clock end of described three triggers does not connect, and they are driven by the clock trees of three SIC (semiconductor integrated circuit) respectively.
9. the RTA reliability test assembly of conductor integrated circuit device according to claim 8 is characterized in that, described voting machine is a kind of three input voting circuit devices.
10. according to Claim 8 or the RTA reliability test assembly of 9 described conductor integrated circuit devices, it is characterized in that, described three clock trees are carried out bifurcated and control in the starting point of described clock trees then by clock of a pin input of conductor integrated circuit device.
11. according to Claim 8 or the RTA reliability test assembly of 9 described conductor integrated circuit devices, it is characterized in that, described three clock trees are by a plurality of pins input of conductor integrated circuit device, control separately each clock unlatching, close with being connected of other clocks.
12. the method for testing reliability of a conductor integrated circuit device is characterized in that, comprises the steps:
Steps A, three clock trees opening and closing states of control SIC (semiconductor integrated circuit), by the scan chain of SIC (semiconductor integrated circuit), under scanning mode to the trigger initialize of reliability device;
Step B, the closed portion clock, unlatching also connects remaining clock, carries out sweep test.
13. method for testing reliability according to claim 12 is characterized in that, also comprises the steps:
Step C, repeating step A up to finishing the test combination, test out the fault in the SIC (semiconductor integrated circuit) to the operation of step B.
14., it is characterized in that in the described steps A, the described trigger initialize of giving comprises the steps: according to claim 12 or 13 described method for testing reliability
Under scanning mode, three clock trees of SIC (semiconductor integrated circuit) are all opened and connection, put normal value " 0 " and scan the long enough time at the scan chain input end, thereby give all trigger initializes " 0 ".
15. method for testing reliability according to claim 14 is characterized in that, among the described step B, carries out sweep test, comprises the steps:
Close clock CK0, open and connection clock CK1 and CK2, carry out sweep test.
16., it is characterized in that in the described steps A, the described trigger initialize of giving comprises the steps: according to claim 12 or 13 described method for testing reliability
Under scanning mode, all trigger initializes " 0 ", turn off clock CK0 then earlier, put normal value " 1 " and scan the long enough time at the scan chain input end, final result is that the trigger initial value of clock CK0 correspondence is " 0 ", and the initial value of other triggers is " 1 ".
17. method for testing reliability according to claim 16 is characterized in that, among the described step B, carries out sweep test, comprises the steps:
Close clock CK0 and CK1, open clock CK2, carry out sweep test.
18. method for testing reliability according to claim 13 is characterized in that, among the described step C, tests out the fault in the SIC (semiconductor integrated circuit), comprises the steps:
If the test result of all test combinations is all consistent, then prove absolutely not have fault in the chip;
If have the test result under arbitrary or several combination inconsistent, illustrate to have fault.
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102323539B (en) * | 2011-07-29 | 2013-06-19 | 清华大学 | Method for generating delay fault test vector set |
| CN102606331A (en) * | 2012-03-20 | 2012-07-25 | 西安航天动力试验技术研究所 | Triple-redundancy voting control system and triple-redundancy voting control method |
| CN102820879A (en) * | 2012-08-17 | 2012-12-12 | 中国电子科技集团公司第五十八研究所 | Radiation-proof triple-modular redundancy circuit structure |
| CN108020769A (en) * | 2016-10-28 | 2018-05-11 | 深圳市中兴微电子技术有限公司 | A kind of method and apparatus of integrated circuit testing |
| CN109212408B (en) * | 2017-06-29 | 2021-04-02 | 龙芯中科技术股份有限公司 | Scanning unit, and output control method and device of redundant trigger |
| CN108055031B (en) * | 2017-12-14 | 2021-04-13 | 北京时代民芯科技有限公司 | Self-recovery triple modular redundancy structure for resisting single-particle soft error accumulation |
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Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |