CN101567392B - Thin-film transistor - Google Patents

Thin-film transistor Download PDF

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Publication number
CN101567392B
CN101567392B CN2009101417694A CN200910141769A CN101567392B CN 101567392 B CN101567392 B CN 101567392B CN 2009101417694 A CN2009101417694 A CN 2009101417694A CN 200910141769 A CN200910141769 A CN 200910141769A CN 101567392 B CN101567392 B CN 101567392B
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film
silicon oxide
oxide film
silicon
mentioned
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CN101567392A (en
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若松贞次
菊池亨
桥本征典
仓田敬臣
浅利伸
斋藤一也
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Ulvac Inc
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Ulvac Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Abstract

A thin-film transistor has a gate insulation layer excellent in characteristics and high in reliability with good productivity ensured, and a production method therefore. The thin-film transistor comprises, formed on a substrate (9), an active layer (11) having a source region (17), a channel region (18) and a drain region (19), a gate electrode layer (16), and a gate insulation layer (15) formed between the active layer (11) and the gate electrode layer (16), wherein the gate insulation layer (15) is formed of a first silicon oxide film (12) formed on the active layer (11) side, a second silicon oxide film (14) formed on the gate electrode layer (16) side, and a silicon nitride film (13) formed between the first silicon oxide film (12) and the second silicon oxide film (14).

Description

Thin-film transistor
The application is to be that April 25, application number in 2005 are dividing an application of 200580000956.0 application the applying date.
Technical field
The present invention relates to thin-film transistor and the manufacture method thereof of silicon oxide film as gate insulation layer.
Background technology
In the device of existing LCD (LCD) or organic electroluminescent (OLED) etc., utilized that the film that is made of amorphous silicon (a-Si) or silicon nitride film (SiNx) or silicon oxide film (SiOx) etc. is formed, the non-crystalline silicon tft (a-SiTFT) as thin-film transistor, low temperature polycrystalline silicon TFT (LTPS-TFT).Especially, compare with non-crystalline silicon tft, low temperature polycrystalline silicon TFT can have higher mobility, and can be transparent and have on the substrate of insulating properties such as the glass substrate and make.
As the typical structure of low temperature polycrystalline silicon TFT, can enumerate coplanar type transistor as shown in Figure 18.
The transistorized structure of coplanar type is formed with the polysilicon membrane that becomes active layer 101 as shown in Figure 18 on the glass substrate 100 with the transparency and insulating properties.This active layer 101 is divided into source region 102, channel region 103, the drain region 104 that has formed by having mixed n type or p type impurity; Be formed with insulating barrier 105 in the mode that covers this active layer 101, on channel region 103, be formed with gate electrode 106.In addition, on interlayer insulating film 107, source electrode 108 and drain electrode 109 have been disposed.
But in the manufacturing process of low temperature polycrystalline silicon TFT, the semiconductor element that is utilized must be large-area, and what therefore use is cheap glass substrate; Because the thermal endurance of this glass substrate is not enough, therefore must manufacturing under than the technological temperature of lower temperature (generally following about 600 ℃).
On the other hand, in the manufacturing process of the silicon TFT that uses monocrystalline silicon substrate, form silicon oxide film as gate insulating film by this monocrystalline substrate surface of high temperature in water vapour atmosphere or in the oxygen atmosphere (about 900 ℃~1000 ℃) oxidation.This gate insulating film that forms by thermal oxidation is the very high film of defective quality seldom in film, and owing to the interface of active layer and gate insulating film also remains under the state of cleaning, so the interfacial characteristics of gate insulating film and silicon substrate is also good.
To this, though in the manufacture method of above-mentioned existing low temperature polycrystalline silicon TFT, be difficult to obtain the good gate insulating film of interfacial characteristics, but in recent years, even proposed in low temperature polycrystalline silicon TFT, also can obtain the manufacture method (for example with reference to patent document 1: the spy opens bulletin flat 10-163193 number) of the good gate insulating film of interfacial characteristics.
The manufacture method of the gate insulating film of above-mentioned patent document 1 is to form oxide-film deposit catalyst metals afterwards, the method for heat-treating in the oxidizing atmosphere below 600 ℃ on polysilicon membrane.
But, in the manufacture method of the existing low temperature polycrystalline silicon TFT of above-mentioned patent document 1, comprise the operation of coated catalysts metal and form the operation of insulating barrier by heat treatment, also comprise and consider its practicality and the operation removed from active layer of catalyst metals the most at last, so its productivity is not good.
In addition, in the manufacturing process of existing low temperature polycrystalline silicon TFT (coplanar type transistor) as shown in Figure 18, before forming gate insulation layer 105, the patterning operation of active layer 101 (source region 102, drain region 104 and channel region 103) is necessary.Therefore, the interface of this active layer 101 and gate insulation layer 105 is difficult to obtain the good characteristic as the manufacturing process of above-mentioned silicon TFT.
Consequently, can produce catching and scattering of charge carrier, problem such as exist the skew (shift) of the threshold voltage of one of characteristic as low temperature polycrystalline silicon TFT to become big or subthreshold value swing (S value) change is big.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of thin-film transistor and manufacture method thereof that when guaranteeing good productivity ratio, has the gate insulation layer of good characteristic and high reliability.
In order to achieve the above object, the active layer that contains active area, drain region, channel region, gate electrode layer that thin-film transistor of the present invention comprises on substrate, and the gate insulation layer that between active layer and gate electrode layer, forms, it is characterized in that: gate insulation layer comprises the 1st silicon oxide film that is formed in contact with active layer, and the silicon nitride film that is formed in contact between the 1st silicon oxide film and gate electrode layer, with the 1st silicon oxide film.
The feature of thin-film transistor of the present invention also is: except above-mentioned structure, also contain the 2nd silicon oxide film between silicon nitride film and gate electrode layer.
The feature of thin-film transistor of the present invention also is: active layer is formed by polysilicon.
The feature of thin-film transistor of the present invention also is: the ratio of the thickness of the 1st silicon oxide film, silicon nitride film is 4~5: 1~2.
The feature of thin-film transistor of the present invention also is: the ratio of the thickness of the 1st silicon oxide film, silicon nitride film, the 2nd silicon oxide film is 4~5: 1~2: 4~5.
The feature of thin-film transistor of the present invention also is: the thickness of the 1st silicon oxide film is more than or equal to 40nm and smaller or equal to 50nm.
The feature of thin-film transistor of the present invention also is: the thickness of silicon nitride film is more than or equal to 10nm and smaller or equal to 20nm.
The feature of thin-film transistor of the present invention also is: the bed thickness of gate insulation layer integral body is more than or equal to 50nm and smaller or equal to 200nm.
Method of manufacturing thin film transistor of the present invention is characterised in that and comprises: the operation that forms active layer at substrate surface; On active layer, form the operation of the 1st silicon oxide film; On the 1st silicon oxide film, form the operation of silicon nitride film; And the operation that on silicon nitride film, forms gate electrode layer.
The feature of above-mentioned method of manufacturing thin film transistor of the present invention also is: except said structure, the operation that forms gate electrode layer is the operation that forms gate electrode layer on silicon nitride film after formation the 2nd silicon oxide film.
The feature of above-mentioned method of manufacturing thin film transistor of the present invention also is: in the operation that forms the 1st silicon oxide film, in the reaction vessel of having adjusted pressure, import at least a carrier of oxygen of executing that the 1st of silicon atom is executed silicon gas, contained oxygen atom that contains at every turn respectively, form silicon oxide film by plasma CVD method then; In forming the operation of silicon nitride film, in the reaction vessel of having adjusted pressure, import respectively at every turn at least a contain the 2nd of silicon atom execute silicon gas, contain nitrogen-atoms execute nitrogen or diluent gas, form silicon nitride film by plasma CVD method then.
The feature of above-mentioned method of manufacturing thin film transistor of the present invention also is: the 1st to execute silicon gas be any one the gas of selecting from the group of being formed by tetraethoxy ortho-silicate (salt), hexamethyldisilazane (hexamethyldislazane), monosilane, disilane; Executing carrier of oxygen is any one gas of selecting from the group of being made up of oxygen, nitrous oxide, ozone, carbon dioxide, water.
The feature of method of manufacturing thin film transistor of the present invention also is: the 1st executes silicon gas and the above-mentioned proportion of composing of executing carrier of oxygen is 1: 30~50.
The feature of method of manufacturing thin film transistor of the present invention also is: the pressure during the silicon oxide film film forming is 80~200Pa, and substrate temperature is 330~430 ℃.
The feature of method of manufacturing thin film transistor of the present invention also is: the 2nd to execute silicon gas be any one the gas of selecting from the group of being formed by tetraethoxy ortho-silicate, hexamethyldisilazane, monosilane, disilane; Executing nitrogen is any one gas of selecting from the group of being made up of ammonia, nitric oxide, hydrazine.
The feature of method of manufacturing thin film transistor of the present invention also is: the 2nd execute silicon gas, execute nitrogen, the proportion of composing of diluent gas is 1: 10~25: 10~30.
The feature of method of manufacturing thin film transistor of the present invention also is: the pressure during the silicon nitride film film forming is 200~400Pa, and substrate temperature is 330~430 ℃.
The feature of method of manufacturing thin film transistor of the present invention also is: when utilizing plasma CVD method to form the 1st silicon oxide film, the 2nd silicon oxide film, silicon nitride film respectively, the frequency of the high frequency voltage that adds on electrode is 27.1MHz.
The membrane according to the invention transistor can reduce threshold voltage and S value thereof, can have excellent characteristic.
In addition, the transistorized manufacture method of membrane according to the invention, can guarantee good productivity, can reduce simultaneously the defect concentration at the interface of defective in the film of gate insulation layer and gate insulation layer and silicon thin film significantly, acquisition has the thin-film transistor of the gate insulation layer of good interface characteristic.
Description of drawings
Fig. 1 is manufacture method according to the embodiment of the present invention and the generalized section as the multi-crystal TFT of thin-film transistor that forms.
Fig. 2 is the generalized section of plasma CVD equipment that is used to form the gate insulation layer of multi-crystal TFT of the present invention.
Fig. 3 is the film-forming process information drawing separately of gate insulation layer of the present invention and existing gate insulation layer.
Fig. 4 is the film-forming temperature when the 1st, the 3rd silicon oxide film that forms as gate insulation layer of the present invention and the graph of a relation of film forming speed.
Fig. 5 is film-forming temperature when forming as the 1st, the 3rd layer of gate insulation layer of the present invention silicon oxide film and the graph of a relation of Dit, Vfb.
Fig. 6 is when forming as the 1st, the 3rd layer of gate insulation layer of the present invention silicon oxide film, with respect to the oxygen ratio of components of executing silicon gas and the graph of a relation of film forming speed.
Fig. 7 is oxygen ratio of components when forming as the 1st, the 3rd layer of gate insulation layer of the present invention silicon oxide film and the graph of a relation of Dit, Vfb.
Fig. 8 is when forming as the 1st, the 3rd layer of gate insulation layer of the present invention silicon oxide film, the graph of a relation of distribution in operation pressure and film forming speed and the real estate.
Fig. 9 is when forming as the 2nd layer of gate insulation layer of the present invention silicon nitride film, as the graph of a relation of the ammonia of executing nitrogen with respect to the ratio of components of executing silicon gas and film forming speed.
Figure 10 is the ratio of components of the ammonia when forming as the 2nd layer of gate insulation layer of the present invention silicon nitride film and the graph of a relation of Dit, Vfb.
Figure 11 is when forming as the 2nd layer of gate insulation layer silicon nitride film, executes nitrogen with respect to the graph of a relation that distributes in the ratio of components of executing silicon gas and film forming speed and the real estate.
Figure 12 is the graph of a relation that distributes in operation pressure when forming as the 2nd layer of gate insulation layer of the present invention silicon nitride film and film forming speed and the real estate.
Figure 13 is the film-forming temperature when forming as the 2nd layer of gate insulation layer of the present invention silicon nitride film and the graph of a relation of film forming speed.
Figure 14 is film-forming temperature when forming as the 2nd layer of gate insulation layer of the present invention silicon nitride film and the graph of a relation of Dit, Vfb.
Figure 15 is in each silicon oxide film of the 1st, the 2nd layer as gate insulation layer of the present invention, the graph of a relation of thickness and Dit, Vfb.
Figure 16 is in the 2nd layer silicon nitride film as gate insulation layer of the present invention, the graph of a relation of thickness and Dit, Vfb.
Figure 17 is in each multi-crystal TFT that uses gate insulation layer of the present invention and existing gate insulation layer, the figure of subthreshold value swing (S value) and threshold voltage (Vth).
Figure 18 is the generalized section as the multi-crystal TFT of thin-film transistor that the manufacture method by existing example forms.
Embodiment
Below, the present invention will be described according to illustrated execution mode.
Fig. 1 is the generalized section as the low temperature polycrystalline silicon TFT (hereinafter referred to as multi-crystal TFT) of thin-film transistor that expression forms as utilizing manufacture method of the present invention, wherein, (a) the expression gate insulation layer is three long-pending layer by layer structures of the 1st silicon oxide film, silicon nitride film and the 2nd silicon oxide film; (b) the two-layer laminated structure of expression the 1st silicon oxide film and silicon nitride film.
With reference to Fig. 1 (a), the thin-film transistor of present embodiment comprises the active layer 11 that comprises source region 17, drain region 19, channel region 18, gate electrode layer 16 and at the gate insulation layer 15 of active layer 11 and 16 formation of gate electrode layer on substrate 9; The 2nd silicon oxide film 14 that gate insulation layer 15 is included in the 1st silicon oxide film 12 that active layer 11 1 sides form, forms in gate electrode layer 16 1 sides, and the silicon nitride film 13 that between the 1st silicon oxide film 12 and the 2nd silicon oxide film 14, forms.
So the thin-film transistor of the present embodiment of structure can reduce threshold voltage and S value.
In addition, shown in Fig. 1 (b),,, also can not form the 2nd silicon oxide film shown in Fig. 1 (a) as long as satisfy the insulating properties of gate insulating film even gate insulation layer is the two-layer structure of the 1st silicon oxide film and silicon nitride film.
Next illustrates the manufacturing installation of present embodiment.
Fig. 2 is the generalized section of plasma CVD apparatus that is used to form the gate insulation layer of this multi-crystal TFT.
Be provided with the gas importation 3 of a plurality of sources of the gas (not shown) that connecting gas bomb etc. on the top of the reaction vessel 2 of this plasma CVD apparatus 1; Be provided with the discharge portion 4 that is connecting vacuum pump (not shown) etc. in the bottom of reaction vessel 2.In reaction vessel 2, relatively be provided with 2 flat upper electrodes 5 and lower electrode 6; The upper electrode 5 that is positioned at the top is connected on the external high frequency power supply 8 by carrying out pulse modulated modulator 7 to High frequency power; Be provided with substrate to be filmed 9 on the lower electrode 6 below being positioned at, and lower electrode 6 is also used as the substrate holder.8 pairs of upper electrodes 5 of high frequency electric source apply the 27.12MHz high frequency voltage.In addition, also can be 13.56MHz as high frequency voltage, but the high frequency voltage of above-mentioned 27.12MHz help improving the gas cracking efficiency.
The structure of upper electrode 5 is as follows: have hollow space 5a so that shower plate 10 is set on its positive side (facing to a side of lower electrode 6); To be connected the front end of gas importation 3 with the mode that this hollow space 5a is communicated with; Unstrpped gas formed a plurality of gases spray 10a from the shower plate 10 are sprayed equably towards the substrate 9 on the lower electrode 6.In addition, the structure of lower electrode 6 has been built-in is heated to the heater (not shown) of assigned temperature with the substrate of being laid 9, and keeps earthing potential in film forming procedure.
Manufacture method to multi-crystal TFT of the present invention describes below.
At first, utilize decompression hot CVD method or plasma CVD method etc. on substrate 9, to form after the noncrystalline silicon fiml of thickness for 50nm, by irradiation chlorination xenon (XeCl) excimer laser (wavelength 308nm) or KrF (KrF) excimer laser (wavelength 248nm), can make the amorphous silicon membrane crystallizationization and obtain polysilicon (Poly-Si) as the crystallinity silicon fiml.Use photoetching or etching with its patterning, form active layer 11.
Then, the substrate 9 that has formed active layer 11 is arranged on the lower electrode 6 in the reaction vessel 2 of above-mentioned plasma CVD apparatus 1, carries out resistance heating so that substrate 9 is heated to set point of temperature to heater (not shown) energising.At this moment, by discharge portion 4 exhausts reaction vessel 2 is adjusted to the pressure of regulation.
Then, by gas importation 3, in reaction vessel 2, introduce by executing the silane-based gas of tetraethoxy ortho-silicate (TEOS) etc. of silicon gas and oxygen etc. and execute the mist (unstrpped gas) that carrier of oxygen is formed, mist is sprayed equably from the substrate 9 that a plurality of gas vent 10a of shower plate 10 face toward on the electrode 6 as the 1st.At this moment, apply the high frequency voltage of 27.12MHz to upper electrode 5 from high frequency electric source 8, discharge takes place so that above-mentioned mist plasma in the space between upper electrode 5 and lower electrode 6, forming thickness on active layer 11 is the 1st silicon oxide film 12 of conduct the 1st insulating barrier of 40~50nm.
In addition, when forming the 1st silicon oxide film 12, execute silicon gas except the silane-based gas that above-mentioned tetraethoxy ortho-silicate (TEOS) waits as the 1st, also can use any gas of from group, selecting by for example monosilane and disilane composition; As executing carrier of oxygen, except oxygen, also can use from by any one gas of selecting the group that for example nitrous oxide, ozone, carbon dioxide, water are formed.
Then, similarly introduce by as the 2nd monosilane (SiH that executes silicon gas 4) mist formed of the diluent gas of executing nitrogen and nitrogen etc. of the silane-based gas that waits and ammonia etc., and utilize discharge to wait to make above-mentioned mist ionization, thereby on the 1st silicon oxide film 12 with the thickness formation of 10~20nm silicon nitride film 13 as the 2nd insulating barrier.
In addition, when forming silicon nitride film 13, execute silicon gas as the 2nd, except monosilane, also can use from by any one gas of selecting the group that for example tetraethoxy ortho-silicate, hexamethyldisilazane and disilane are formed; As the above-mentioned nitrogen of executing, except ammonia, also can use from by any one gas of selecting the group that for example nitric oxide, diamine are formed.
Then, the mist of the gas system that input is identical with the 1st silicon oxide film 12, and utilize discharge to make above-mentioned mist plasma, thus the formation thickness is the 2nd silicon oxide film 14 of conduct the 3rd insulating barrier of 50nm on silicon nitride film 13.Then, use photoetching and etching, form gate insulation layer 15 its patterning.Details as the gate insulation layer 15 of feature of the present invention illustrates after a while.
If satisfying, the insulating properties of gate insulating film also can not form the 2nd silicon oxide film 14.
In addition, the mist that as the mist that forms the 1st, 2 silicon oxide films 12,14, uses respectively, executes select the carrier of oxygen at least a and mix with regulation content from silane-based gas; As the mist that forms silicon nitride film 13, the mist that uses respectively from silane-based gas, executes select nitrogen, the diluent gas at least a and mix with regulation content.
Secondly, on above-mentioned gate insulation layer 15 (the 2nd silicon oxide film 14), utilize after the thickness formation aluminium film of sputtering method with 250nm, utilize sputtering method to form the molybdenum film of 50nm.Make the scandium that contains 0.2% weight in this aluminium film.Be the thrust that forms the needle-like that is called as projection (hillock) or burr (whisker) in the later operation in order to be suppressed at like this.Then, use photoetching and etching that its patterning is formed gate electrode 16.
After gate electrode 16 formed, mixing was used to form the impurity (being used to give a kind of impurity of conduction type) in source/drain region.Here, in order to obtain n channel-type thin-film transistor, carry out the doping of P (phosphorus) by the plasma doping method.Doping is annealed after finishing, and carries out the annealing of the activate of impurity and the damage of mixing.In above-mentioned operation, be formed self-aligned source region 17, channel region 18 and drain region 19 respectively.
Secondly, on gate electrode 16 and gate insulation layer 15, by CVD method (plasma CVD method, hot CVD method, ECR plasma CVD method etc.), with the thickness formation silicon oxide film 20 of 250nm.Then, by using photoetching and etching to form contact hole and having formed after the insulating barrier 21, use sputtering method to form the molybdenum film with the thickness of 50nm, the thickness with 300nm forms the aluminium film then, and form source electrode 22 and drain electrode 23, thereby obtain multi-crystal TFT of the present invention shown in Figure 1.
Secondly, the membrance casting condition of utilizing the gate insulation layer of the present invention 15 that above-mentioned catalyst CVD device 1 makes etc. is described.
The thickness of gate insulation layer 15 of the present invention is the 1st layer (the 1st silicon oxide film 12): the 2nd layer (silicon nitride film 13): the 3rd layer of (the 2nd silicon oxide film 14)=50nm: 10nm: 50nm; Its film-forming process condition separately as shown in Figure 3.In order to compare, employed with the gate insulation layer of existing multi-crystal TFT, be that the typical film-forming process condition of silicon oxide film of raw material is also shown in Figure 3 in the lump with TEOS.Film thickness distribution in film forming speed, the real estate is the result under the situation that is of a size of film forming on the glass substrate of 730mm * 920mm.In addition, Vfb (unit: V) be the flat band voltage of the index of the defect level in the conduct expression gate insulation layer; Dit (unit: cm -2EV -1) be interface energy level density as the index of the defect concentration at the interface of expression gate insulation layer and silicon thin film.The substrate of this moment uses the Si[001 of P type] single-crystal wafer (Na=2 * 10 15Cm -3).
As shown in Figure 3, under the situation of existing gate insulation layer, be about 80nm/min as the film forming speed of the silicon oxide film of unstrpped gas with TEOS, the film thickness distribution in real estate (10mm end) is about ± 7.5%.In addition, when this thickness is 110nm, Vfb=-1.5-2.0V, Dit=8 * 10 11Cm -2EV -1
In view of the above, from the test result shown in Fig. 4~Fig. 6 described later as can be known, the film-forming process condition of gate insulation layer in the present invention is that the whole film forming speed of gate insulation layer is about 78~83nm/min, and the film thickness distribution (10mm end) in the real estate is about ± 5.5~7.0%.In addition, be under the situation of 110nm at this thickness, Vfb=-1.0~-1.5V, Dit=4.3 * 10 10~9.6 * 10 10Cm -2EV -1
Fig. 4 is when being illustrated in formation as the 1st, the 3rd layer silicon oxide film (the 1st, the 2nd silicon oxide film 12,14), the test result of the relation of film-forming temperature and film forming speed; Fig. 5 is illustrated in when forming silicon oxide film (the 1st, the 2nd silicon oxide film 12,14), the test result of film-forming temperature and Dit, Vfb relation.In Fig. 5, a is Dit, and b is Vfb.
From test result shown in Figure 4 as can be known, if film-forming temperature rises, then film forming speed reduces, and productivity reduces.In addition, from test result shown in Figure 5 as can be known, if film-forming temperature rises, then Dit reduces, and the defect concentration at interface descends; But, during more than or equal to 430 ℃ of left and right sides, Dit roughly becomes definite value at film-forming temperature.On the other hand, if film-forming temperature rises, then Vfb rises, and the defect level in the layer reduces; But film-forming temperature is more than or equal to 430 ℃ the time, and Vfb becomes definite value.Consider that from the heat resisting temperature of substrate and the situation of device materials film-forming temperature is preferably smaller or equal to about 450 ℃.
Therefore, in order to keep high silicon oxide film (the 1st, the 2nd silicon oxide film 12,14) film forming speed when the film forming, reduce Dit, to improve Vfb, preferably film forming in the scope about 330 ℃~430 ℃.
Fig. 6 is illustrated in when forming silicon oxide film (the 1st, the 2nd silicon oxide film 12,14), with respect to the test result of the oxygen ratio of components of giving silicon gas and film forming speed relation; Fig. 7 is illustrated in when forming silicon oxide film (the 1st, the 2nd silicon oxide film 12,14) test result of the relation of oxygen ratio of components and Dit, Vfb.In Fig. 7, a is Dit, and b is Vfb.
From the result shown in Fig. 6 as can be known, if the oxygen ratio of components increases, then film forming speed reduces, and productivity reduces.From the result shown in Fig. 7 as can be known, if the carrier of oxygen ratio of components increases, Dit reduces, and the defect concentration at interface reduces; Dit sharply reduces smaller or equal to 30 o'clock at the oxygen ratio of components, but at the oxygen ratio of components more than or equal to roughly becoming definite value at 50 o'clock.On the other hand, if the oxygen ratio of components increases, then Vfb rises, and the defect level in the layer reduces; But, Vfb the oxygen ratio of components sharply rose smaller or equal to 30 o'clock and at the oxygen ratio of components more than or equal to roughly becoming definite value at 50 o'clock.
Therefore, in order to keep high silicon oxide film (the 1st, the 2nd silicon oxide film 12,14) film forming speed and to reduce Dit, raising Vfb, preferably with respect to film forming in the scope of oxygen ratio of components about 30~50 of executing silicon gas.
Fig. 8 is illustrated in when forming silicon oxide film (the 1st, the 2nd silicon oxide film 12,14), the test result of distribution relation in operation pressure and film forming speed and the real estate.In Fig. 8, a is a film forming speed, and b distributes in the real estate.From this test result as can be known, if operation pressure increases, then film forming speed reduces.In addition, being distributed in operation pressure in the real estate is to have minimum value near the 125Pa.
Therefore, in order to distribute in the real estate that reduces silicon oxide film (the 1st, the 2nd silicon oxide film 12,14), preferred film forming in operation pressure is scope about 80~200Pa.
Fig. 9 is illustrated in when forming silicon nitride film (as the silicon nitride film 13 of the 2nd insulating barrier), with respect to executing silicon gas, as the test result of the relation of the ratio of components of the ammonia of executing nitrogen and film forming speed; Figure 10 is illustrated in when forming silicon nitride film (as the silicon nitride film 13 of the 2nd insulating barrier), the test result of ammonia ratio of components and Dit, Vfb relation.In Figure 10, a is Dit, and b is Vfb.
From the test result shown in Fig. 9 as can be known, if the ammonia ratio of components increases, then film forming speed reduces, and productivity descends.From the test result shown in Figure 10 as can be known, if the ammonia ratio of components increases, then Dit reduces, and the defect concentration at interface reduces; The ammonia ratio of components about reaching 20 till, Dit sharply reduces, and roughly becomes definite value at the ammonia ratio of components more than or equal to 20 o'clock Dit.On the other hand, if the ammonia ratio of components increases, then Vfb rises, the minimizing of the defect level in the layer; Arrive till about 20 up to the ammonia ratio of components, Vfb sharply increases, and at the ammonia ratio of components more than or equal to roughly becoming definite value at 20 o'clock.
Therefore, in order to keep high silicon nitride film (as the silicon nitride film 13 of the 2nd insulating barrier) film forming speed when the film forming, reduce Dit, to improve Vfb, preferred film forming when the ammonia ratio of components is in the scope about 10~25.
Figure 11 is that nitrogen (diluent gas) is with respect to the test result of the relation that distributes in the ratio of components of executing silicon gas and film forming speed and the real estate when forming silicon nitride film (as the silicon nitride film 13 of the 2nd dielectric film).In Figure 11, a is a film forming speed, and b distributes in the real estate.
From the test result shown in Figure 11 as can be known, if the nitrogen ratio of components increases, then film forming speed reduces.And, be distributed in the nitrogen ratio of components near having minimum value at 20 o'clock in the real estate.Therefore, in order to distribute in the real estate that reduces silicon nitride film (as the silicon nitride film 13 of the 2nd insulating barrier), preferred film forming when the nitrogen ratio of components is in the scope about 10~30.
Figure 12 is illustrated in when forming silicon nitride film (as the silicon nitride film 13 of the 2nd insulating barrier), the test result of the relation between distributing in operation pressure and film forming speed and the real estate.In Figure 12, a is a film forming speed, and b distributes in the real estate.
From the test result shown in Figure 12 as can be known, if operation pressure rises, then film forming speed reduces, and has minimum value near being distributed in 250Pa in the real estate.Therefore, diminishing in order to distribute in the real estate that makes silicon nitride film (as the silicon nitride film 13 of the 2nd insulating barrier), is film forming in the scope about 200~400Pa the time at operation pressure preferably.
Figure 13 is when being illustrated in silicon nitride film (as the silicon nitride film 13 of the 2nd insulating barrier) formation, the test result that concerns between film-forming temperature and the film forming speed; Figure 14 is when expression forms silicon nitride film (as the silicon nitride film 13 of the 2nd insulating barrier), the test result that concerns between film-forming temperature and Dit, the Vfb.In Figure 14, a is Dit, and b is Vfb.
From the test result shown in Figure 13 as can be known, if film-forming temperature rises, then film forming speed reduces, and productivity descends.In addition, from the test result shown in Figure 14 as can be known, if film-forming temperature rises, then Dit reduces, and interface defect density reduces; But during more than or equal to 430 ℃ of left and right sides, Dit roughly becomes definite value at film-forming temperature.On the other hand, if film-forming temperature rises, then Vfb rises, and the defect level in the layer reduces; But Vfb roughly becomes definite value more than or equal to 430 ℃ of left and right sides the time.In addition, according to the heat resisting temperature of substrate, preferably smaller or equal to 450 ℃.
Therefore, in order to keep high silicon nitride film (as the silicon nitride film 13 of the 2nd insulating barrier) film forming speed when the film forming, reduce Dit, to improve Vfb, preferably film forming in the scope about 330 ℃~430 ℃.
Figure 15 is the test result that concerns between the thickness of the 1st, the 3rd layer (the 1st, the 2nd silicon oxide film 12,14) of the gate insulation layer 15 of expression among the present invention and Dit, the Vfb.Figure 16 is the test result that concerns between the thickness of the 2nd layer (silicon nitride film 13) of the gate insulation layer 15 of expression among the present invention and Dit, the Vfb.Among Figure 15, Figure 16, a is Dit, and b is Vfb.
From the test result shown in Figure 15, Figure 16 as can be known, thickness at the 2nd layer (silicon nitride film 13) is under the situation of 10~20nm, the thickness of 1st, the 3rd layer (the 1st, the 2nd silicon oxide film 12,14) can obtain good membranous gate insulation layer (Dit is low, and the Vfb height) respectively in the scope of 40~50nm.
And, comprise respectively under gate insulation layer 15 of the present invention and the situation making by the multi-crystal TFT of the existing gate insulation layer of forming as the silicon oxide film of unstrpped gas with TEOS, subthreshold value swing (S value, unit: V/dec) and threshold voltage (Vth, unit have been tested, and obtained the test result shown in Figure 17 V).At this moment, each gate insulation layer film-forming process condition is identical with situation among Fig. 3.
From the test result shown in Figure 17 as can be known, compare with the gate insulation layer (silicon oxide film) of existing single layer structure, utilize the gate insulation layer (the 1st silicon oxide film 12, silicon nitride film the 13, the 2nd silicon oxide film 14) 15 that forms 3-tier architecture of the present invention can produce the subthreshold value swing high-performance polycrystal silicon TFT that (S value) is little and threshold voltage (Vth) is low.
As mentioned above, manufacturing method according to the invention, both guaranteed good productivity, can access again and have advantageous characteristic (with low substrate temperature (smaller or equal to about 450 ℃) reduced significantly and the film of gate insulation layer in defective and with the interface defect density of silicon thin film) the multi-crystal TFT of gate insulation layer.

Claims (6)

1. thin-film transistor, have the active layer that comprises source region, drain region, channel region, gate electrode layer on the substrate and between above-mentioned active layer and gate electrode layer formed gate insulation layer, it is characterized in that:
The silicon nitride film that above-mentioned gate insulation layer comprises the 1st silicon oxide film that contacts with above-mentioned active layer and form and is formed in contact between the 1st silicon oxide film and above-mentioned gate electrode layer, with above-mentioned the 1st silicon oxide film, the thickness of above-mentioned the 1st silicon oxide film is more than or equal to 40nm, less than 50nm
The thickness of above-mentioned silicon nitride film is more than or equal to 10nm, smaller or equal to 20nm.
2. thin-film transistor according to claim 1 is characterized in that:
Have the 2nd silicon oxide film between above-mentioned silicon nitride film and above-mentioned gate electrode layer, the thickness of above-mentioned the 2nd silicon oxide film is more than or equal to 40nm, less than 50nm.
3. thin-film transistor according to claim 1 and 2 is characterized in that:
Above-mentioned active layer is formed by polysilicon.
4. thin-film transistor according to claim 1 is characterized in that:
Above-mentioned the 1st silicon oxide film is 4~5: 1~2 with the ratio of the thickness of above-mentioned silicon nitride film.
5. thin-film transistor according to claim 2 is characterized in that:
The ratio of the thickness of above-mentioned the 1st silicon oxide film, above-mentioned silicon nitride film, above-mentioned the 2nd silicon oxide film is 4~5: 1~2: 4~5.
6. thin-film transistor according to claim 1 and 2 is characterized in that:
The thickness of above-mentioned gate insulation layer integral body is more than or equal to 50nm, smaller or equal to 200nm.
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