CN101595615B - Structure and method for self protection of power device - Google Patents

Structure and method for self protection of power device Download PDF

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Publication number
CN101595615B
CN101595615B CN2008800025853A CN200880002585A CN101595615B CN 101595615 B CN101595615 B CN 101595615B CN 2008800025853 A CN2008800025853 A CN 2008800025853A CN 200880002585 A CN200880002585 A CN 200880002585A CN 101595615 B CN101595615 B CN 101595615B
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Prior art keywords
over current
current protection
chip
protection sheath
semiconductor power
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CN101595615A (en
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孙明
弗兰茨娃·赫尔伯特
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Chongqing Wanguo Semiconductor Technology Co., Ltd.
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Alpha and Omega Semiconductor Inc
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Abstract

A resetable over-current self-protecting semiconductor power device comprises a vertical power semiconductor chip and an over-current protection layer composed of current limiting material such as a PTC material. The over- current protection layer may be sandwiched between the vertical power semiconductor chip and a conductive plate, which could be a leadframe, a metal plate, a PCB plate or a PCB that the device is mounted on.

Description

In power device for structure and the method for self-protection
Technical field
The present invention relates to a kind of structure and method of protection device.Especially, the present invention relates to a kind of circuit structure and method of improvement, it protects power device to avoid the infringement brought by the caused overcurrent of short circuit with the electric conducting material with positive temperature coefficient.
Background technology
Under high power scenarios, power device usually can cause because of " short circuit " phenomenon losing efficacy, and now can cause damage for other assembly in the system of using this power device.Therefore, power device preferably can lose efficacy in (open circuit) state at open circuit, certainly, if what can avoid fully losing efficacy is better.And prevent from losing efficacy, can the outside of its part as device or device be realized by integrated protective circuit.A kind of special protection method applied in semiconductor device is; as shown in Figure 1A, before connection gasket (bond pads) engages, by meltability jockey (fusible link); as metal fuse or polysilicon fuse, be configured in inside conductor connection metal pattern.Yet as shown in Figure 1B, the defect that this kind of configuration has is, in the application of superelevation electric current, due to many fuses of needs and a plurality of connection gasket, makes crystallite dimension increase, and will produce extra-pay, and for manufacturing and running impacts.The another kind of shortcoming of using many fuses and a plurality of connection gasket to follow is that, if not every fuse all fuses between the emergence period (blow open) in overcurrent, the active region of the device that fuse is not fused will sustain damage.Moreover, other protective circuit, for example (fail-open) protective circuit of metal fuse, polysilicon fuse or other " failure bypass ", often can be unfavorable for the running of device or system.This fuse protection also has shortcoming, is exactly (re-settable) of this type of protection for resetting, even overcurrent situations disappears, once but the fuse damage, the connection of fuse also can wreck so.
In order to overcome above-mentioned restriction, use the material of positive temperature coefficient (PTC) as reducible over-current protection device.Known, various PTC materials are arranged, for example polymer positive-temperature-coefficient is counted material, and business-like product on the market have " polysilicon fuse " (Polyfuse), " polysilicon switch " (Polyswitch) and " many switches " (Multiswitch).These products can be made into the plastic products that are embedded with carbon particle.When plastic products, during in the state of cooling, whole carbon particles can contact with each other, and forms conductive path in device.When plastic products heat, expansion can impel carbon particle separately, and makes the resistance of device improve rapidly.As barium titanate (BaTiO 3) transistor, this kind of device has nonlinearity resistance/temperature response, and can be used as switch, rather than as the ratio temperature meter.United States Patent (USP) the 4th, 238, No. 812 and various data forms disclose the application of positive temperature coefficient, and this application provides the application of PTC material as commercial product.In addition, the effectiveness of PTC material also has been proved, and when temperature increase, the resistance of PTC material can promote 5 orders of magnitude.
Even PTC material is well-known for the application of the overcurrent protection of electronic device, but, when actual use PTC material, many technical restrictions and difficulty are still arranged.The positive temperature coefficient protective circuit can realize by the protective circuit device that is connected to load as shown in Figure 1 C usually, and this protective circuit device comprises PTC material, and PTC material has the resistance improved along with temperature.Yet, in order to reach the protection to device, need to utilize oneself's heating (self-heating) to improve temperature, and, need to provide I at device inside 2the voltage drop of R, and avoid fin may lower the effectiveness of device protection by special installation.At the same time, higher resistance may cause higher oneself's heating and reach better protection, yet, also can produce negative impact for this power system.Similarly, also may provide external heat source with the heating PTC material by increasing more circuit devcie, still, the circuit devcie of these increases will cause and limit and occupy a large amount of spaces current protection.
Therefore, in circuit design and element manufacturing field, still exist a kind of demand, need exactly to provide structure and the manufacture method of a kind of novelty and improvement, to solve above-mentioned difficulties.Especially, still have and need to provide a kind of brand-new structure with improvement to reach the positive temperature coefficient protection, make aforesaid various restriction and difficulty be solved.
Summary of the invention
Therefore; one aspect of the present invention is to provide a kind of resetted positive temperature coefficient protection structure of brand-new and improvement; therefore; temperature increase in electronic device can be applied on PTC material automatically; and; use the positive temperature coefficient protection can make the amplification minimum of dead resistance, with this, overcome difficulty and the restriction that the protection of aforementioned conventional positive temperature coefficient is caused.
More particularly; another aspect of the present invention is to provide a kind of positive temperature coefficient protection structure of brand-new and improvement; its positive temperature coefficient protection has large thermal coupling with heating component or zone in electronic device; simultaneously, this type of is coupling in the situation of coupling or the increase minimum of dead resistance provides.
Another aspect of the present invention is to provide a kind of positive temperature coefficient protection structure of brand-new and improvement, and it can be implemented with the standard packaging technology easily, thereby can avoid the adverse effect caused on manufacturing cost.
Another aspect of the present invention is to provide a kind of brand-new and positive temperature coefficient protection structure improvement, and it can be in the situation that need not increase package dimension and implement, thereby can reduce the potential adverse effect caused on manufacturing cost.
In brief, in a preferred embodiment, the invention discloses a kind of vertical semiconductor power device, it comprises semi-conductive substrate, the upper surface of this Semiconductor substrate and lower surface form a vertical current path, cross the electric current in this vertical current path in order to conduction flow.This semiconductor power device also comprises an over current protection sheath, and this over current protection sheath is comprised of the material that forms a vertical current path part, flows through the electric current of this over current protection sheath in order to restriction.In one embodiment, this over current protection sheath is comprised of reducible current limit material.In another embodiment, this over current protection sheath is comprised of the material of the resistance with positive temperature coefficient.In another embodiment, on the attached lower surface that is arranged on described Semiconductor substrate of this overcurrent protection laminating.In another embodiment, on the attached upper surface that is arranged on described Semiconductor substrate of this overcurrent protection laminating.In another embodiment, this over current protection sheath is arranged between Semiconductor substrate and conductive plate.In another embodiment, this over current protection sheath is arranged between Semiconductor substrate and conductive plate, and described conductive plate is as the lead frame of semiconductor power device.In another embodiment, this over current protection sheath is comprised of the material of the resistance with positive temperature coefficient (PTC), as a reducible current-limiting layer.In another embodiment, this over current protection sheath is patterned, the protection effect with optimization to device.In another embodiment, described vertical semiconductor power device includes a MOSFET chip with lower surface, and this lower surface is as drain electrode, to contact with described over current protection sheath.In another embodiment, described vertical semiconductor power device comprises bottom source MOSFET chip, and it has a lower surface, and this lower surface, as source electrode, contacts with described over current protection sheath.
The invention also discloses a kind of method that manufacture has the electronic device of integrated overcurrent protection.The method comprises the step that an over current protection sheath consisted of the current limit material is set.The method also comprises and connects first side of semiconductor chip to the overcurrent protection layer, and connects the step of a conductive plate to the second side of overcurrent protection layer.
After the detailed description of the preferred embodiment of reading below in conjunction with accompanying drawing, effect of the present invention and advantage are for the person of ordinary skill of the art, apparent beyond doubt.
The accompanying drawing explanation
Figure 1A～Fig. 1 C avoids the schematic diagram of the different over-current protection structure of the infringement that short circuit current causes in order to protection device in prior art;
Fig. 2 is the side sectional view that is provided with the standard vertical DMOS power MOSFET of positive temperature coefficient protection provided by the present invention;
Fig. 3 is the side sectional view that is provided with the standard vertical DMOS power MOSFET of positive temperature coefficient protection provided by the present invention, and this positive temperature coefficient protection structure is patterned PTC layer, to improve resistance;
Fig. 4 A is the side sectional view that is provided with the step-down controller of positive temperature coefficient protection provided by the present invention, and Fig. 4 B is the circuit diagram of Fig. 4 A;
Fig. 5 A is the side sectional view that is provided with the boost converter of positive temperature coefficient protection provided by the present invention, and Fig. 5 B is the circuit diagram of Fig. 5 A;
Fig. 6 A-1 and Fig. 6 A-2 are respectively cutaway view and the upward views with CSP encapsulation of the outer positive temperature coefficient protection covered of the encapsulation of being located at provided by the present invention; And
Fig. 6 B-1 and Fig. 6 B-2 are respectively cutaway view and the vertical views with CSP encapsulation of the positive temperature coefficient protection be located on user's printed panel outside provided by the present invention.
Embodiment
Fig. 2 is a kind of side sectional view of encapsulating structure of the semiconductor power component 100 that reaches improvement newly, as shown in the figure, standard vertical DMOS (double-diffused metal oxide semiconductor) power MOSFET (mos field effect transistor) is arranged on a printed circuit board (PCB) (PCB) 105.Printed circuit board (PCB) 105 supports a lead frame, this lead frame comprise one be arranged on the right gate terminal 110, it connects the gate liner (not showing especially) on chip 120, this lead frame also comprises a source terminal 115 that is arranged on the left side, in order to be connected to the one source pole metal (showing especially) on chip 120.And gate terminal 110 with source terminal 115 to being connected by some bonding lines 125 between chip 120.Bottom has the chip 120 of drain electrode, is for example power MOSFET, is arranged on positive temperature coefficient (PTC) layer 130, with chip pad 135, is connected, and this chip pad 135 is arranged on the center of lead frame and as drain lead.Then, utilize moulding compound 140 to hold and protect whole encapsulating structure.
Can pass through solder fluxes, conductive epoxy resin or other electric conducting material between MOSFET chip 120, PTC layer 130 and chip pad realizes connecting.In one embodiment, PTC layer 130 is a kind of PTC film, and it has the surface that conductive layer is formed on PTC layer, to facilitate the chip attachment process.Be positioned at the top of PTC film and following conductive metal layer, can utilize sputter, evaporation or plating mode to be formed on PTC material, it can and attach the surface that the chip of scolding tin and epoxy resin is complementary for copper, gold or other.In another embodiment, PTC layer 130 is applied in the back side of MOSFET wafer, and this MOSFET wafer, before being cut into independent chip, comprises several MOSFET chips 120.In another embodiment, before chip attaches, PTC layer 130 is applied on chip pad.In another embodiment, PTC layer 130 is a kind of conductive epoxy resin with positive temperature coefficient resistance material, for example, and the mixture of the powder of a kind of conductive epoxy resin and PTC material.
In operating process, between the source electrode at chip 120 upper surfaces and lower surface and drain electrode, form a vertical current path.This current path more vertically extends through PTC layer 130, plays the variable-resistance effect of connecting with MOSFET chip 120.The heat produced by MOSFET chip 120 can make the resistance of PTC layer 130 change.Under normal operation, certain heat that MOSFET chip 120 produces can by moulding compound 140, with lead frame, loss be around.The device running is under thermal equilibrium condition and maintain normal running temperature, with this understanding, the impedance of PTC layer 130 (impedance) is designed to maintain Low ESR.When overcurrent situations occurs, 120 of MOSFET chips can produce extra heat, cause the temperature of PTC layer 130 to raise, thus the degree that causes resistance to be brought up to making electric current dwindle.After overcurrent situations is eliminated, temperature will be got back to normal running temperature, and the resistance of PTC layer 130 can return to low resistance.Therefore, protection is reducible.Because resistance can improve along with the increase of power loss degree; perhaps can be along with the increase of the electric current of the protected device of flowing through and improve; rather than improve along with oneself's heating of PTC material itself; therefore; PTC material can have lower resistance under normal running temperature; and, along with the generation of the heat from protected device, increase its resistance.Therefore, under self-heating state, PTC material does not need to have high initial resistance can be able to effective execution.In addition, device can maintain encapsulating structure closely, and does not need to increase volume or complexity.
PTC layer 130 as shown in the figure can be made of comprising for example ceramic material of barium titanate that adulterates.Conducting polymer can example has the polymer of special filler in being dispersed in this way.This kind of PTC material for example successfully has been used in Application in manufacture, in the fuse of very thin layer, the thickness of about 0.5 micron.Layout based on PTC material, the performance of protection can optimization.Above disclosed utilization arranges the application of the structure of PTC material or layer conduct part electricity or heat conduction path, can extend to multiple assembly technology.The encapsulation based on lead frame as shown in Figure 2, PTC layer can be arranged between chip and lead frame chip pad zone.Directly attach the assembly of circuit board (COB) for chip, PTC layer can be inserted between chip and printed circuit board material.In the structure of chip size packages (CSP), PTC layer can be inserted between the part encapsulation of chip and chip scale package structure.Further, the current limit material of other kind, for example, when being triggered by high current density, can change into the phase-change material of current limit phase mutually from the electric current conduction, can substitute temperature coefficient materials at an easy rate and implement, and the while is without any need for architecture advances.
Fig. 3 is a kind of side sectional view with power semiconductor assembly encapsulation 100 ' of positive temperature coefficient pattern, and it has the resistance of increase, therefore increases thermal coupling and protection, the protection with optimization to device.This encapsulation 100 ' and the structural similarity shown in Fig. 2, except PTC layer 130 being patterned as to three section 130-1,130-2 and 131-3, and improved at the drain electrode of power mosfet chip 120 bottoms and the contact resistance between lead frame.The resistance that PTC layer increases can improve thermal coupling, and, along with the temperature raising of PTC layer 130 will increase resistance rapidly, can more effectively reach Limited Current when short-circuit conditions occurs, and therefore, provides preferably component protection.That PTC layer 130 also can further be patterned as is circular, striated or latticed etc.
By positive temperature coefficient being set as the part conductivity path with specific electrical resistance, PTC layer or PTC material can be applicable to Schottky diode, with the protection Schottky diode, in some application, can be able to heat dissipation (run-away).These application can comprise the boost converter that shows product, when carrying out when pin is tested pin, can avoid fire.Many power circuits, including but not limited to boosting and step-down power circuit, synchronous versus asynchronous step-down controller, adjuster, low-dropout regulator etc., also can be subject to the protection that is provided with the structure of PTC layer or fuse layer on electricity or heat conduction path disclosed in this invention.This PTC layer also can be applied to the vertical DMOS and vertical Schottky diode, bottom source lateral double diffusion metal oxide semiconductor, bottom anode Schottky assembly, IGBT etc. of standard.
Fig. 4 A and Fig. 4 B are side sectional view and the circuit diagrams with step-down controller 200 of positive temperature coefficient protection structure provided by the present invention.Step-down controller 200 is arranged on printed circuit board (PCB) 205.Step-down controller 200 comprises a Schottky diode 210, and this Schottky diode 210 has a bottom cathode 215 and a top anode (not showing especially in figure), and this top anode is connected to an earth terminal 225 of lead frame by a positive wire 220.In addition, step-down controller also comprises a high-pressure side field-effect transistor 230, this field-effect transistor 230 has a bottom source 235 and a top-side drain (not showing especially in figure), and this top-side drain connects by many Vcc/Vin end 245 that wire 240 is connected to lead frame.And field-effect transistor 230 also includes a gate liner, this gate liner is electrically connected to the gate lead of lead frame (not shown).In the 11/495th of application on July 28th, 2006, in No. 803 U.S. patent documents, disclose detailed description and the manufacture method of this field-effect transistor 230, and quoted as a reference herein.The bottom cathode 215 of Schottky diode 210 is realized being connected by PTC layer 250 with the bottom source 235 of high-pressure side field-effect transistor 230, and is connected to by this PTC layer 250 output 260 that is set directly at the lead frame on printed circuit board (PCB) 205.Because PTC layer 250 is parts of electricity and heat conduction path, the increase of conduction current will automatically cause the lifting of temperature, thereby causes the increase of the resistance of PTC layer 250.Therefore, step-down controller 200 is by PTC layer 250 and protected, and this PTC layer 250 has limited the electric current with field-effect transistor 230 by Schottky diode 210.
Fig. 5 A and Fig. 5 B are side sectional view and the circuit diagrams with boost converter 300 of positive temperature coefficient protection structure provided by the present invention.This boost converter 300 is arranged on a printed circuit board (PCB) 305.It includes a Schottky diode 310, and this Schottky diode 310 has a bottom anode 315 and top negative electrode (not showing especially in figure), and this top negative electrode is connected to the Vcc end 325 of lead frame by a negative electrode and source/drain polar conductor 320.And, boost converter 300 also comprises a low-pressure side field-effect transistor 330, this field-effect transistor 330 has a bottom drain 335 and a top source electrode and grid (not showing especially in figure), and this top source electrode is connected by many earth terminal 345 that wire 340 is connected to lead frame with grid.Field-effect transistor 330 also includes a gate liner, and this gate liner is electrically connected to the gate lead of lead frame (not shown).In the 11/495th of on July 28th, 2006 application, detailed description and the manufacture method of this field-effect transistor 330 disclosed in No. 803 U.S. patent documents, quote as a reference herein.The bottom anode 315 of Schottky diode 310 is realized being connected by PTC layer 350 with the bottom drain 335 of low-pressure side field-effect transistor 330, and is connected to by this PTC layer 350 output 360 that is set directly at the lead frame on printed circuit board (PCB) 305.Because PTC layer 350 is parts of electricity and hot conducting path, the increase of conduction current will automatically cause the lifting of temperature, so cause the increase of the resistance of PTC layer 350.Therefore, the boost converter 300 that comprises Schottky diode and low-pressure side field-effect transistor is protected by PTC layer 350, and this PTC layer 350 has limited the electric current with field-effect transistor 330 by Schottky diode 310.
Fig. 6 A-1 and Fig. 6 A-2 are cutaway view and the bottom views of the first structure of the wafer-level package with PTC layer protection provided by the present invention.In this embodiment; wrapper is containing the molten formula field-effect transistor (CSP-fuse-FET) 410 of a chip-scale; the molten formula field-effect transistor 410 of chip-scale has and the contacted drain electrode of a positive temperature coefficient protective layer 420; this positive temperature coefficient protective layer 420 is arranged between the drain electrode and conductive plate 425 of field-effect transistor 410, and wherein conductive plate 425 can be printed circuit board (PCB) or metal.The molten formula field-effect transistor 410 of this chip-scale has source electrode and the grid that some solder bumps 430 are connected to field-effect transistor 410, and this encapsulation 400 also comprises the ball grid array (ball grid array) 440 be arranged on conductive plate 425.As shown in Fig. 6 A-1 and Fig. 6 A-2, this structure is a kind of positive temperature coefficient structure be positioned in encapsulation " enclosing cover (lid) ".Fig. 6 B-1 and Fig. 6 B-2 are respectively cutaway view and the bottom views of the second structure of the wafer-level package with PTC layer protection provided by the present invention.In this embodiment; encapsulating structure 400 ' comprises the molten formula field-effect transistor (CSP-fuse-FET) 460 of a chip-scale; the molten formula field-effect transistor 460 of this chip-scale has and the contacted drain electrode of positive temperature coefficient protective layer 470, and this positive temperature coefficient protective layer 470 is arranged on the drain electrode and printed circuit board (PCB) 475 of field-effect transistor 460.And the molten formula field-effect transistor 460 of chip-scale has source electrode and the grid that several solder bumps 480 are connected to field-effect transistor 460, and encapsulate 400 ' and also comprise the ball grid array 490 be arranged on circuit board 475.As shown in Fig. 6 B-1 and Fig. 6 B-2, this structure is a kind of positive temperature coefficient structure be positioned on user's printed panel outside (customer board side).
The enforcement of positive temperature coefficient protection can further extend to the structure of the PTC material that is arranged on the conductive layer both sides.The convenient assembling of using conductive epoxy resin or scolding tin to attach of such structure.Moreover, be for example the conductive film of metal, copper, aluminium, titanium-nickel-Yin etc., can utilize sputter-deposited, evaporation or plating mode to form.Except using the positive temperature coefficient substrate protective under chip, PTC material can be added to chip attach material, for example adds epoxide resin material to, to simplify execution mode.In addition, before the silicon wafer cutting, silicon wafer can be bonded to PTC film.This step have been eliminated and have been separated the needs that are positioned at ptc material assembly under active equipment in order protecting, and has therefore obviously simplified processing procedure.
According to above, illustrate and accompanying drawing, the invention also discloses a kind of semiconductor power device, it at least comprises two semiconductor chips, and described semiconductor chip has a plurality of surfaces, in order to the electric current between at least two surfaces of conduction, using as current conduction path.Semiconductor power component also comprises an over current protection sheath, and it is component part current conduction path on a semiconductor chip at least, and wherein the current protection layer is comprised of the current limit material.In one embodiment, a plurality of semiconductor chip interconnection, as the multi-chip module (MCM) by the protection of over current protection sheath.In another embodiment, a plurality of semiconductor chips comprise a MOSFET chip and a diode, using as the step-down controller of being protected by the over current protection sheath.In another embodiment, a plurality of semiconductor chips comprise a MOSFET chip and a diode, using as the boost converter of being protected by the over current protection sheath.In another embodiment, but the over current protection sheath by the resetting current limiting material, formed.In another embodiment, the over current protection sheath is comprised of the material with positive temperature coefficient resistor.In another embodiment, the over current protection sheath is arranged between semiconductor chip and the conductive plate in order to the support semiconductor power device.In another embodiment, the over current protection sheath is arranged between Semiconductor substrate and the conductive plate as the semiconductor power device lead frame.In another embodiment, the over current protection sheath is arranged between semiconductor chip and conductive plate, and this conductive plate is printed circuit board (PCB) and supports, in order to support and to connect semiconductor power device.
Although the present invention is described in detail in the mode of preferred embodiment, should be appreciated that, these are open not in order to limit the present invention.After reading above-mentioned disclosed content, for a person skilled in the art, various to substitute and change be all apparent undoubtedly.Therefore, claim should be interpreted as comprising all not breaking away from the alternative of spirit and scope of the invention and change.

Claims (23)

1. a vertical semiconductor power device, it comprises Semiconductor substrate, and is formed on the semiconductor power chip on this Semiconductor substrate, is characterised in that:
Described semiconductor power chip has a upper surface and a lower surface, and this upper surface and this lower surface form a vertical current path, in order to guide this vertical current path of a current flowing;
Described semiconductor power chip is a MOSFET chip, and the lower surface of this semiconductor power chip is the bottom chip surface of MOSFET chip;
Described vertical semiconductor power device also comprises an over current protection sheath, and this over current protection sheath has positive temperature coefficient resistor, in order to limit an electric current by this over current protection sheath; There is a conductive film on this over current protection sheath, can utilize sputter-deposited, evaporation or plating mode to be formed on this over current protection sheath;
Described over current protection sheath connects upper surface or the lower surface of Semiconductor substrate by solder fluxes or conductive epoxy resin.
2. vertical semiconductor power device as claimed in claim 1, is characterized in that, described over current protection sheath is comprised of reducible current limit material, and when the temperature subnormal temperature of described MOSFET chip, this over current protection sheath has low resistance.
3. vertical semiconductor power device as claimed in claim 1, is characterized in that, described over current protection sheath is comprised of a material with positive temperature coefficient resistor, and its thickness is 0.5 micron.
4. vertical semiconductor power device as claimed in claim 1, is characterized in that, the capped one deck conductive plate that adheres to of described over current protection sheath, and this conductive plate is for the support semiconductor power chip.
5. vertical semiconductor power device as claimed in claim 1, is characterized in that, the capped one deck conductive plate that adheres to of described over current protection sheath, and this conductive plate is as a lead frame.
6. vertical semiconductor power device as claimed in claim 1, is characterized in that, described over current protection sheath is mixed with the dusty material with positive temperature coefficient resistor by epoxy resin to be formed.
7. vertical semiconductor power device as claimed in claim 1, is characterized in that, after described over current protection sheath is patterned, is divided into several discontinuous sections, component part vertical current path, the protection effect with optimization to device.
8. vertical semiconductor power device as claimed in claim 1, is characterized in that, the bottom chip surface of described MOSFET chip contacts with described over current protection sheath as drain electrode.
9. vertical semiconductor power device as claimed in claim 1, is characterized in that, the bottom chip surface of described MOSFET chip contacts with described over current protection sheath as source electrode.
10. a semiconductor power device, is characterized in that, comprises:
At least two semiconductor chips, be respectively formed on two Semiconductor substrate, each semiconductor chip has top chip surface and a bottom chip surface, and this top chip surface forms a vertical current path with this bottom chip surface, in order to guide this vertical current path of a current flowing;
One of them of described at least two semiconductor chips is a MOSFET chip with bottom chip surface;
One over current protection sheath, this over current protection sheath has positive temperature coefficient resistor, forms the part of current conduction path at least one MOSFET chip; There is a conductive film on this over current protection sheath, can utilize sputter-deposited, evaporation or plating mode to be formed on this over current protection sheath;
Described over current protection sheath connects upper surface or the lower surface of Semiconductor substrate by solder fluxes or conductive epoxy resin.
11. semiconductor power device as claimed in claim 10, is characterized in that, described at least two semiconductor chips interconnection, using as the multi-chip module of being protected by this over current protection sheath; The thickness of described over current protection sheath is 0.5 micron.
12. semiconductor power device as claimed in claim 10, is characterized in that, described at least two semiconductor chips comprise a MOSFET chip and a diode, using as the step-down controller of being protected by this over current protection sheath.
13. semiconductor power device as claimed in claim 10, is characterized in that, described at least two semiconductor chips comprise a MOSFET chip and a diode, using as the boost converter of being protected by this over current protection sheath.
14. semiconductor power device as claimed in claim 10, is characterized in that, described over current protection sheath is comprised of reducible current limit material, and when the temperature subnormal temperature of described MOSFET chip, this over current protection sheath has low resistance.
15. semiconductor power device as claimed in claim 10, is characterized in that, described over current protection sheath is comprised of a material with positive temperature coefficient resistor, and its thickness is 0.5 micron.
16. semiconductor power device as claimed in claim 10, is characterized in that, described over current protection sheath is mixed with the dusty material with positive temperature coefficient resistor by epoxy resin to be formed.
17. semiconductor power device as claimed in claim 10, is characterized in that, also comprises a conductive plate, described conductive plate covers on described over current protection sheath; Wherein, described overcurrent protection laminating is attached on the bottom chip surface of MOSFET chip.
18. semiconductor power device as claimed in claim 10, is characterized in that, also comprises a conductive plate as lead frame, described conductive plate covers on described over current protection sheath; Wherein, described overcurrent protection laminating is attached on the bottom chip surface of MOSFET chip.
19. semiconductor power device as claimed in claim 10, is characterized in that, also comprises a conductive plate be formed on printed circuit board (PCB), described conductive plate covers on described over current protection sheath; Wherein, described overcurrent protection laminating is attached on the bottom chip surface of MOSFET chip.
20. a method of manufacturing vertical semiconductor power device, is characterized in that, comprises following steps:
One over current protection sheath is set, and this over current protection sheath consists of the material with positive temperature coefficient resistor;
Utilize sputter-deposited, evaporation or plating mode to form a conductive film on this over current protection sheath;
The semiconductor power chip is connected to the first side of this over current protection sheath; Conductive plate is connected to the second side of this over current protection sheath;
Described semiconductor power chip is one to have the MOSFET chip on bottom chip surface;
Described over current protection sheath connects upper surface or the lower surface of Semiconductor substrate by solder fluxes or conductive epoxy resin.
21. method as claimed in claim 20; it is characterized in that, the step of described connection over current protection sheath further comprises: will be mixed with the dusty material with positive temperature coefficient resistor the overcurrent protection laminating formed by epoxy resin and be attached on the bottom chip surface of MOSFET chip.
22. method as claimed in claim 20, is characterized in that, before completing MOSFET chip attaching step,, before described MOSFET chip attaches on chip pad by each, covers one deck over current protection sheath on the chip pad of lead frame.
23. method as claimed in claim 20; it is characterized in that; before completing MOSFET chip attaching step; before the bottom chip surface label of described MOSFET chip by each is attached on chip pad, attach one deck over current protection sheath on the bottom chip surface of each described MOSFET chip.
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WO2008091648A3 (en) 2008-09-18
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US7999363B2 (en) 2011-08-16
CN101595615A (en) 2009-12-02

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