CN101599431B - Method for reducing polycrystalline silicon loss in mask etching process - Google Patents

Method for reducing polycrystalline silicon loss in mask etching process Download PDF

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Publication number
CN101599431B
CN101599431B CN2009100553812A CN200910055381A CN101599431B CN 101599431 B CN101599431 B CN 101599431B CN 2009100553812 A CN2009100553812 A CN 2009100553812A CN 200910055381 A CN200910055381 A CN 200910055381A CN 101599431 B CN101599431 B CN 101599431B
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layer
insulating barrier
mask
polysilicon
polycrystalline silicon
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CN101599431A (en
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董耀旗
孔蔚然
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

The invention provides a method for reducing polycrystalline silicon loss in a mask etching process, which is applied to the manufacture of a floating gate of a flash memory device. The method comprises the following steps: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a polycrystalline silicon layer on the insulating layer; forming a second insulating layer on the polycrystalline silicon layer; forming a mask layer on the second insulating layer; and carrying out dry plasma etching for the mask layer and stopping forming a groove on the second insulating layer. The method for reducing the polycrystalline silicon loss in the mask etching process can effectively reduce the polycrystalline silicon loss in the mask etching process in the floating grate manufacturing technology of the flash memory device, so the manufactured flash memory device has good electric performance.

Description

Reduce the method for polysilicon loss in the mask etching processing procedure
Technical field
Designing integrated circuit of the present invention is made the field, and is particularly related to the method that reduces the polysilicon loss in a kind of mask etching processing procedure.
Background technology
Flash memory is convenient with it, and storage density is high, and advantages such as good reliability become the focus of studying in the non-volatility memorizer.Since first flash memory products comes out from the 1980s; Development and the demand of each electronic product along with technology to storage; Flash memory is widely used in mobile phone, notebook, palmtop PC and USB flash disk etc. move with communication apparatus in; Flash memory is a kind of nonvolatile memory; Its operation principles is a switch of controlling the gate pole passage through the critical voltage that changes transistor or memory cell can be because of power interruptions disappear to reach the purpose of storage data, to make the data that are stored in the memory, and flash memory is a kind of special construction of electric erasable and programmable read-only memory.Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
Yet existing flash memory is in the high storage density of marching toward more; Owing to receive the restriction of program voltage; Improve storage density through reduction of device size and will face very big challenge, thereby the flash memory of development high storage density is the important motive force of flash memory technology development.Traditional flash memory owing to receive the restriction of structure, realizes that the program voltage of device further reduces to be faced with very big challenge in the high storage density of marching toward more.
Flash memory; It generally is (Stack-Gate) structure that is designed to have stacked gate; This structure comprises tunnel oxide, be used for the multi-crystal silicon floating bar of store charge, silicon oxide/silicon nitride/silicon oxide (Oxide-Nitride-Oxide, ONO) dielectric layer and be used for the polysilicon control grid utmost point of control data access between the grid of structure.
Figure 1A and Figure 1B are depicted as the manufacture method of floating boom in the prior art, on Semiconductor substrate 10, form oxidation insulating layer 11, polysilicon layer 12 and silicon nitride hard mask layer 13 successively, and wherein said polysilicon layer 12 is used to form floating boom; Then said silicon nitride hard mask layer 13 is carried out etching and forms groove, however in this etching processing procedure because etching just stops on the polysilicon layer 12 than difficulty, can cause polysilicon layer 12 to be etched usually and reduce thickness.Polysilicon layer 12 has thicker thickness in the prior art, for example is 700 dusts, and etching causes the loss of the right polysilicon layer 12 of 200 Izods, and final polysilicon layer thickness is 500 dusts.Please refer to Fig. 2 A and Fig. 2 B again, form oxidation insulating layer 21, polysilicon layer 22 and silicon nitride hard mask layer 23 on the Semiconductor substrate 20 successively.Development along with technology; Dwindling of flush memory device size, the thickness of said floating gate polysilicon also become thinner, and it is right that for example initial polysilicon layer 22 thickness become 300 Izods; Because the effect of etching makes that the final thickness of its floating gate polysilicon may be less than 100 dusts; So to make that it bears the electric charge ability relatively poor for the floating gate polysilicon of thickness, simultaneously since on the technology error of tens dusts make that its varied in thickness with respect to whole floating boom is very big, therefore cause the electric property of flush memory device unstable.
Summary of the invention
The present invention proposes to reduce in a kind of mask etching processing procedure the method for polysilicon loss, and the polysilicon loss that it can effectively reduce the mask etching processing procedure in the floating boom manufacture craft of flush memory device makes the flush memory device of processing have good electric property.
In order to achieve the above object, the present invention proposes to reduce in a kind of mask etching processing procedure the method for polysilicon loss, and the floating boom that is applied to flush memory device is made, and this method comprises the following steps:
Semi-conductive substrate is provided;
On said Semiconductor substrate, form first insulating barrier;
On said insulating barrier, form polysilicon layer;
On said polysilicon layer, form second insulating barrier;
On said second insulating barrier, form mask layer;
Said mask layer is carried out dry plasma etch and stops on said second insulating barrier forming groove.
Further, the material of said mask layer is a silicon nitride.
Further, the thickness of said mask layer is 500 dusts~10000 dusts.
Further, the thickness of said second insulating barrier is 20 dusts~600 dusts.
Further, the material of said first insulating barrier and second insulating barrier is a silica.
Further, this method also comprises:
Silicon oxide layer deposited on said groove and mask layer;
Said silicon oxide layer is carried out anisotropic dry etch, etching stopping on polysilicon layer, thereby form monox lateral wall at the sidewall of groove.
The present invention proposes to reduce in a kind of mask etching processing procedure the method for polysilicon loss; It has increased by second insulating barrier between polysilicon layer and mask layer; Therefore can effectively reduce the polysilicon loss of the mask etching processing procedure in the floating boom manufacture craft of flush memory device; Make floating gate polysilicon keep original thickness and can keep original electric charge ability of bearing, also make the flush memory device of finally processing have good electric property.
Description of drawings
Figure 1A, Figure 1B, Fig. 2 A and Fig. 2 B are depicted as the manufacture method sketch map of floating boom in the prior art.
Shown in Figure 3 for reducing the method flow diagram of polysilicon loss in the mask etching processing procedure of preferred embodiment of the present invention.
Fig. 4 A~Fig. 4 D is depicted as the method sketch map that reduces the polysilicon loss in the mask etching processing procedure of preferred embodiment of the present invention.
Embodiment
In order more to understand technology contents of the present invention, special act specific embodiment also cooperates appended graphic explanation following.
Please refer to Fig. 3, shown in Figure 3 for reducing the method flow diagram of polysilicon loss in the mask etching processing procedure of preferred embodiment of the present invention.The present invention proposes to reduce in a kind of mask etching processing procedure the method for polysilicon loss, and the floating boom that is applied to flush memory device is made, and this method comprises the following steps:
Step S100: semi-conductive substrate is provided;
Step S200: on said Semiconductor substrate, form first insulating barrier;
Step S300: on said insulating barrier, form polysilicon layer;
Step S400: on said polysilicon layer, form second insulating barrier;
Step S500: on said second insulating barrier, form mask layer;
Step S600: mask layer is carried out dry plasma etch and stop on second insulating barrier forming groove;
Step S700: silicon oxide layer deposited on said groove and mask layer;
Step S800: said silicon oxide layer is carried out anisotropic dry etch, etching stopping on polysilicon layer, thereby form monox lateral wall at the sidewall of groove.
The preferred embodiment according to the present invention, the material of said mask layer are silicon nitride, and the thickness of said mask layer is 500 dusts~10000 dusts.The thickness of said second insulating barrier is 20 dusts~600 dusts, and the material of said first insulating barrier and second insulating barrier is a silica.
Please refer to Fig. 4 A~Fig. 4 D again, Fig. 4 A~Fig. 4 D is depicted as the method sketch map that reduces the polysilicon loss in the mask etching processing procedure of preferred embodiment of the present invention.Among Fig. 4 A, semi-conductive substrate 100 is provided, its last time is formed with first insulating barrier 110, polysilicon layer 120, second insulating barrier 130 and mask layer 140, and wherein polysilicon layer 120 is used to form floating gate polysilicon.Please refer to Fig. 4 B again; Said mask layer 140 is carried out dry plasma etch and stops on said second insulating barrier 130 forming groove; Owing to increased by second insulating barrier 130, therefore can control the position of etching stopping preferably, if produce the part over etching as etching stop layer; The part of removing only can be second insulating barrier 130 also, and can not remove polysilicon layer 120.Then please refer to Fig. 4 C and Fig. 4 D, silicon oxide layer deposited 150 and said silicon oxide layer 150 carried out the anisotropic dry etch etching stopping on polysilicon layer 120 on said groove and mask layer 140, thus form monox lateral wall 160 at the sidewall of groove.Through deposition and etching oxidation silicon layer 150,, need not increase by second insulating barrier 130 that extra step stays with hard mask layer etching before removing afterwards because it has identical materials with second insulating barrier 130.
In sum; The present invention proposes to reduce in a kind of mask etching processing procedure the method for polysilicon loss; It has increased by second insulating barrier between polysilicon layer and mask layer; Therefore can effectively reduce the polysilicon loss of the mask etching processing procedure in the floating boom manufacture craft of flush memory device, make floating gate polysilicon keep original thickness and can keep original electric charge ability of bearing, also make the flush memory device of finally processing have good electric property.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.

Claims (4)

1. reduce the method that polysilicon loses in a mask etching processing procedure, the floating boom that is applied to flush memory device is made, and it is characterized in that this method comprises the following steps:
Semi-conductive substrate is provided;
On said Semiconductor substrate, form first insulating barrier;
On said insulating barrier, form polysilicon layer;
On said polysilicon layer, form second insulating barrier;
On said second insulating barrier, form mask layer;
Wherein, the material of said mask layer is a silicon nitride, and the material of said first insulating barrier and second insulating barrier is a silica.
Said mask layer is carried out dry plasma etch and stops on said second insulating barrier forming groove.
2. reduce the method for polysilicon loss in the mask etching processing procedure according to claim 1, it is characterized in that the thickness of said mask layer is 500 dusts~10000 dusts.
3. reduce the method for polysilicon loss in the mask etching processing procedure according to claim 1, it is characterized in that the thickness of said second insulating barrier is 20 dusts~600 dusts.
4. reduce the method for polysilicon loss in the mask etching processing procedure according to claim 1, it is characterized in that this method also comprises:
Silicon oxide layer deposited on said groove and mask layer;
Said silicon oxide layer is carried out anisotropic dry etch, etching stopping on polysilicon layer, thereby form monox lateral wall at the sidewall of groove.
CN2009100553812A 2009-07-24 2009-07-24 Method for reducing polycrystalline silicon loss in mask etching process Active CN101599431B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5104819A (en) * 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
US5907775A (en) * 1997-04-11 1999-05-25 Vanguard International Semiconductor Corporation Non-volatile memory device with high gate coupling ratio and manufacturing process therefor
US6773987B1 (en) * 2001-11-17 2004-08-10 Altera Corporation Method and apparatus for reducing charge loss in a nonvolatile memory cell
CN101197329A (en) * 2006-12-08 2008-06-11 中芯国际集成电路制造(上海)有限公司 SONOS flash memory and production method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5104819A (en) * 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
US5907775A (en) * 1997-04-11 1999-05-25 Vanguard International Semiconductor Corporation Non-volatile memory device with high gate coupling ratio and manufacturing process therefor
US6773987B1 (en) * 2001-11-17 2004-08-10 Altera Corporation Method and apparatus for reducing charge loss in a nonvolatile memory cell
CN101197329A (en) * 2006-12-08 2008-06-11 中芯国际集成电路制造(上海)有限公司 SONOS flash memory and production method thereof

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Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai