CN101615583B - Chip stacking structure forming method - Google Patents

Chip stacking structure forming method Download PDF

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Publication number
CN101615583B
CN101615583B CN200810125048XA CN200810125048A CN101615583B CN 101615583 B CN101615583 B CN 101615583B CN 200810125048X A CN200810125048X A CN 200810125048XA CN 200810125048 A CN200810125048 A CN 200810125048A CN 101615583 B CN101615583 B CN 101615583B
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chip
support plate
packaging body
layer
metal level
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CN200810125048XA
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CN101615583A (en
Inventor
黄成棠
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Chipmos Technologies Bermuda Ltd
Chipmos Technologies Inc
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Chipmos Technologies Bermuda Ltd
Chipmos Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

The invention relates to a chip packaging structure and a forming method thereof. The packaging structure comprises a chip, a packaging body, a first patterned protection layer, a metal layer, a second patterned protection layer, a plurality of patterned UBM layers and a plurality of conductive assemblies, wherein a plurality of soldering pads and adhesion layers are respectively arranged on an active surface and a back surface of the chip; the packaging body is annularly covered on four surfaces of the chip so as to expose the soldering pads of the chip out and is provided with a plurality of through holes; the first patterned protection layer is formed on the partial surface of the packaging body and the active surface of the partial chip and exposes the soldering pads and the through holes out; the metal layer is covered on the partial surface of the first patterned protection layer, and is electrically connected with the soldering pads and filled in the through holes; the second patterned protection layer is covered on the first patterned protection layer and a part of metal layer and exposes the partial surface of the metal layer out; the patterned UBM layers are formed on the partial surface of the exposed metal layer and the partial surface of the second patterned protection layer and are electrically connected with the metal layer; and the conductive assemblies are formed on the patterned UBM layers and electrically connected with the metal layer through the patterned UBM layers.

Description

The formation method of chip stack structure
Technical field
Relevant a kind of semiconductor package structure of the present invention and method, particularly relevant a kind of chip stack structure and method for packing.
Background technology
Semi-conductive technology has developed suitable rapidly, therefore microminiaturized semiconductor chip (Dice) must have the demand of diversified function, make semiconductor chip must in very little zone, dispose more I/o pad (I/O pads), thereby make the density of metal pin (pins) also improve fast.Therefore, early stage leaded package technology has been not suitable for the high-density metal pin; So develop the encapsulation technology that a kind of ball array (Ball Grid Array:BGA), the ball array encapsulation is except having than the more highdensity advantage of leaded package, and its tin ball also relatively is not easy infringement and distortion.
Popular along with 3C Product, for example: mobile phone (Cell Phone), PDA(Personal Digital Assistant) or iPod etc., all the System on Chip/SoC of many complexity must be put into a very little space, therefore be this problem of solution, a kind of being called " wafer-class encapsulation (wafer level package; WLP) " encapsulation technology develops out, and it can just encapsulate wafer earlier before cut crystal becomes one by one chip.United States Patent (USP) announces the 5th, 323, and No. 051 patent has promptly disclosed this " wafer-class encapsulation " technology.Yet, this " wafer-class encapsulation " technology is along with the increase of the weld pad on the chip active surface (pads) number, make that the spacing of weld pad (pads) is too small, except meeting causes the problem of signal coupling or signal interference, also can cause the problems such as reliability reduction of encapsulation because the weld pad spacing is too small.Therefore, after chip further dwindles again, make aforesaid encapsulation technology all can't satisfy.
For solving this problem, United States Patent (USP) announces the 7th, 196, disclosed a kind of wafer that will finish semiconductor process for No. 408, after test and cutting, with test result is that good chip (good die) reapposes on another substrate, and then carry out packaging process, so, make these chip chambers that reapposed have the spacing of broad, so (fan out) technology that stretches out is for example used in distribution that can the weld pad on the chip is suitable, therefore can effectively solve because of spacing too small, the problem that causes signal coupling or signal to disturb except meeting.
Yet, for making semiconductor chip that less and thin encapsulating structure can be arranged, before carrying out the wafer cutting, can carry out thinning to wafer earlier and handle, for example wafer is thinned to 2～20 mils (mil), and then cuts into chip one by one in back of the body mill (backside lapping) mode.This chip through the thinning processing through reconfiguring on another substrate, forms a packaging body with injection molded with a plurality of chips again; Because chip is very thin, make that packaging body also is very thin, so after packaging body disengaging substrate, the stress of packaging body itself can make packaging body generation warpage increases follow-up difficulty of carrying out cutting action.
In addition, after the wafer cutting, reconfigure when another support plate, be of a size of greatly because the size of new support plate is more original, therefore plant in the ball operation follow-up, can can't aim at, its encapsulating structure reliability reduces.
In addition, in the process of whole encapsulation, also can produce when planting ball, manufacturing equipment can produce local excessive pressure to chip, and may damage the problem of chip; Simultaneously, also may because the material of planting ball causes and chip on weld pad between resistance value become big, and influence the problems such as performance of chip.
Summary of the invention
Because the problem of planting ball aligning and packaging body warpage described in the background of invention the invention provides the method that a kind of chip reconfigures and encapsulates.
Another main purpose of the present invention is providing a kind of method for packing that reconfigures at chip, is that chip with different size size and function reconfigures the method for packing on a support plate.
In addition, the present invention also has a main purpose at the method for packing that provides a kind of chip to reconfigure, it can be reconfigured in the chip that 12 inch wafers are cut out on the chip containing rack, so can effectively use the sealed in unit that promptly has of 8 inch wafers, and need not to re-establish the sealed in unit of 12 inch wafers, can reduce the packaging cost of 12 inch wafers.
A main purpose more of the present invention makes that at the method for packing that provides a kind of chip to reconfigure the chip that encapsulates all is " known is normally functioning chip " (Known good die), can save encapsulating material, so also can reduce the technology cost.
According to the above, the present invention discloses a kind of method for packing of chip, comprises: a support plate is provided, has the front and the back side; Form packaging body on the front of support plate, and have a plurality of through holes in packaging body to expose the partial front of support plate; Attaching chip on support plate, be with the active surface of chip up, and the back side of chip is attached on the front of having exposed to the open air of support plate by adhesion layer; Form first patterned protection layer on packaging body and part active surface at chip, and expose chip active surface a plurality of weld pads and expose a plurality of through holes; Form metal level and cover partly on the first patterned protection layer and fill up a plurality of through holes, and form and electrically connect with a plurality of weld pads on the active surface of chip; The formation second patterned protection layer is on first patterned protection layer and cover the part metal level to expose the part surface of metal level; The UBM layer that forms a plurality of patternings and form to electrically connect with metal level on the part surface of the metal level that has exposed to the open air; Forming a plurality of conductive components, is that UBM layer and the metal level formation of a plurality of conductive components by a plurality of patternings is electrically connected; And remove support plate, to form a chip-packaging structure.
The present invention discloses a kind of encapsulating structure of chip again, comprising: chip, dispose a plurality of weld pads on its active surface and the back side has adhesion layer; Four faces that packaging body, its ring cover chip are with a plurality of weld pads of the active surface that exposes chip and have a plurality of through holes in packaging body; First patterned protection layer, it is formed on the active surface of the part surface of packaging body and partial chip, and exposes a plurality of weld pads and a plurality of through hole of the active surface of chip; Metal level, it is covered in the part surface of first patterned protection layer and forms and electrically connect and fill up a plurality of through holes with a plurality of weld pads on the active surface of chip; Second patterned protection layer, it is covered on first patterned protection layer and the part metal level and exposes the part surface of metal level; The UBM layer of a plurality of patternings, it is formed on the part surface of the part surface of the metal level that has exposed to the open air and second patterned protection layer, and forms with metal level and to electrically connect; And a plurality of conductive components, be formed on the UBM layer of a plurality of patternings and the UBM layer by a plurality of patternings forms electric connection with metal level.
The present invention discloses a kind of stack architecture of Chip Packaging in addition, comprises: a plurality of chips, and the back side that all disposes a plurality of weld pads and each chip on the active surface of each chip has adhesion layer; Packaging body, its ring cover each chip and expose each chip active surface a plurality of weld pads and have a plurality of through holes in packaging body; First patterned protection layer, it is formed on the part active surface of the part surface of packaging body and each chip, and exposes a plurality of weld pads of the active surface of each chip; Metal level, its many weld pads that cover on the active surface of the part surface of first patterned protection layer and each chip electrically connect to form, and fill up a plurality of through holes, the two ends of wherein running through the metal level of packaging body form the first conduction end points and the second conduction end points respectively; Second patterned protection layer, it is covered on first patterned protection layer and the part metal level and exposes the part surface of metal level; The UBM layer of a plurality of patternings, it is formed on the part surface of the part surface of the metal level that has exposed to the open air and second patterned protection layer, and forms with metal level and to electrically connect; A plurality of conductive components are formed on the UBM layer of a plurality of patternings and the UBM layer by a plurality of patternings forms electric connection with metal level; And chip stack structure, be that a plurality of second conduction end points on first chip are electrically connected on a plurality of conductive components of second chip.
According to above-described encapsulating structure, the present invention discloses a kind of method for packing of multicore sheet, comprises: support plate is provided, has the front and the back side; Form packaging body on the front of support plate, and have a plurality of through holes in packaging body to expose the partial front of support plate; Attaching a plurality of chips on support plate, is that the back side with each chip is attached on the front of having exposed to the open air of support plate by adhesion layer; Form first patterned protection layer on packaging body and part active surface at a plurality of chips, and expose a plurality of chips active surface a plurality of weld pads and expose a plurality of through holes; Form metal level and cover partly first patterned protection layer and fill up a plurality of through holes, and form and electrically connect with a plurality of weld pads on the active surface of chip; The formation second patterned protection layer is on first patterned protection layer and cover the part metal level to expose the part surface of metal level; The UBM layer that forms a plurality of patternings and electrically connects with metal level on the part surface of the metal level that has exposed to the open air; Forming a plurality of conductive components, is that UBM layer and the metal level formation of a plurality of conductive components by a plurality of patternings is electrically connected; Remove this support plate, to form a multichip packaging structure.
The present invention discloses a kind of encapsulating structure of multicore sheet again, comprises: a plurality of chips, and the back side that has a plurality of weld pads and each chip on the active surface of each chip has adhesion layer; Packaging body, its ring cover each chip and expose each chip active surface a plurality of weld pads and have a plurality of through holes in packaging body; First patterned protection layer, it is formed on the part active surface of the part surface of packaging body and each chip, and exposes a plurality of weld pads of this active surface of each chip; Metal level, its a plurality of weld pads that cover on the active surface of the part surface of first patterned protection layer and each chip electrically connect to form, and fill up a plurality of through holes, the two ends of wherein running through the metal level of packaging body form the first conduction end points and the second conduction end points respectively; Second patterned protection layer, it is covered on first patterned protection layer and the part metal level and exposes the part surface of metal level; The UBM layer of a plurality of patternings, it is formed on the part surface of the part surface of the metal level that has exposed to the open air and second patterned protection layer, and forms with metal level and to electrically connect; A plurality of conductive components are formed on the UBM layer of a plurality of patternings and the UBM layer by a plurality of patternings forms electric connection with metal level, to form first chip-packaging structure; And multi-chip stack structure, be with first encapsulating structure have mutually same structure second encapsulating structure a plurality of conductive components be electrically connected to first chip a plurality of first the conduction end points on.
Description of drawings
For can clearer understanding purpose of the present invention, characteristics and advantage, below conjunction with figs. is described in detail preferred embodiment of the present invention, wherein:
Fig. 1 represents the disclosed technology according to the present invention, is the schematic cross-section of expression one support plate;
Fig. 2 is disclosed technology according to the present invention, is illustrated in the schematic cross-section that forms packaging body on the support plate;
Fig. 3 is disclosed technology according to the present invention, and expression is seated in schematic cross-section on the support plate with packaging body with a plurality of chips;
Fig. 4 is disclosed technology according to the present invention, represents that a plurality of first patterned protection layer are formed on the schematic cross-section on the packaging body;
Fig. 5 is disclosed technology according to the present invention, and the expression metal level is formed on first protective layer and a plurality of weld pad and the schematic cross-section that forms a plurality of conductive poles simultaneously;
Fig. 6 is disclosed technology according to the present invention, and the metal wire sections of representing a plurality of patternings is formed on the schematic cross-section on the weld pad of packaging body and a plurality of chips;
Fig. 7 is disclosed technology according to the present invention, represents that second protective layer is formed on the schematic cross-section on the metal wire sections of a plurality of patternings;
Fig. 8 is disclosed technology according to the present invention, represents that a plurality of second patterned protection layer are formed on the schematic cross-section on the metal wire sections of a plurality of patternings;
Fig. 9 is disclosed technology according to the present invention, is illustrated in the schematic cross-section that forms the UBM layer of a plurality of patternings on the surface of the other end of metal wire sections of patterning of each fan-out that has exposed to the open air;
Figure 10 is disclosed technology according to the present invention, represents that a plurality of conductive components are formed on the schematic cross-section on the UBM layer of a plurality of patternings;
Figure 11 is disclosed technology according to the present invention, is the schematic cross-section that the one chip encapsulating structure of encapsulation is finished in expression;
Figure 12 is disclosed technology according to the present invention, is the schematic cross-section of the encapsulating structure of expression chip stack;
Figure 13 is disclosed technology according to the present invention, and expression is by the system in package that the chip constituted (System-In-Package of a plurality of difference in functionalitys and size; SIP) vertical view;
Figure 14 is disclosed technology according to the present invention, and expression is seated in schematic cross-section on the support plate with packaging body with the chip of different size and function;
Figure 15 is disclosed technology according to the present invention, represents that a plurality of first patterned protection layer are formed on the schematic cross-section on the packaging body;
Figure 16 is disclosed technology according to the present invention, and the expression metal level is formed on the schematic cross-section on a plurality of first patterned protection layer;
Figure 17 is disclosed technology according to the present invention, and the metal wire sections of representing a plurality of patternings is formed on the schematic cross-section on a plurality of first patterned protection layer;
Figure 18 is disclosed technology according to the present invention, represents that second protective layer is formed on the schematic cross-section on the metal wire sections of a plurality of patternings;
Figure 19 is disclosed technology according to the present invention, represents that a plurality of second patterned protection layer are formed on the schematic cross-section on the metal wire sections of a plurality of patternings;
Figure 20 is disclosed technology according to the present invention, is illustrated in the schematic cross-section that forms the UBM layer of a plurality of patternings on the surface of the other end of metal wire sections of patterning of each fan-out that has exposed to the open air; And
Figure 21 is disclosed technology according to the present invention, represents that a plurality of conductive components are formed on the UBM layer of a plurality of patternings, finish the schematic cross-section of the multichip packaging structure of encapsulation.
Embodiment
The present invention is the method for packing that a kind of chip reconfigures in this direction of inquiring into, a plurality of chips is reconfigured on the support plate with packaging body the method that encapsulates then.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, execution of the present invention does not limit the specific details that the those of ordinary skill of the mode of chip stack is familiar with.On the other hand, the detailed step of back segment operations such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet, for preferred embodiment of the present invention, can be described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, its with after claim be as the criterion.
In the semiconductor packages operation in modern times, all be a wafer (wafer) of having finished leading portion operation (Front End Process) to be carried out thinning earlier handle (Thinning Process), for example the thickness of chip is ground to 2～20 mils (mil) between; Then, carry out the cutting (sawing process) of wafer to form chip one by one; Then, use fetching device (pick and place) that chip one by one is positioned on another support plate one by one.Clearly, the street zone on the support plate is bigger than chip, therefore, and can be so that these chip chambers that reapposed have the spacing of broad, so distribution that can the weld pad on the chip is suitable.
At first, provide a wafer (not expression in the drawings) and on wafer, dispose a plurality of chips (not expression in the drawings),, have a plurality of weld pads (not expression in the drawings) on each chip at this.Then, Fig. 1 be expression provide a support plate 10 its have a positive and back side, the material of support plate 10 can be glass, quartz, pottery or circuit board in the present embodiment.Then, Fig. 2 is illustrated in the schematic cross-section that forms packaging body on the support plate.In Fig. 2, be that a packaging body 20 is formed on the support plate 10, and in packaging body 20, have a plurality of through holes 202 and 204 to expose the part surface of support plate 10 to the open air.In this enforcement, comprise in the step that forms packaging body 20 on the support plate 10: be coated with a macromolecular material (expression in the drawings) earlier on the front of support plate 10, and use a die device (not expression in the drawings) the macromolecular material pressing with a plurality of protrusion ribs (expression in the drawings).At this, a plurality of protrusion ribs on the die device each other between the interval can be the same or different, its objective is for the macromolecular material pressing after, form the different through hole of a plurality of depth-width ratios.
In addition, macromolecular material also can select to use injection molded (molding process) to be formed on the support plate 10.Similarly, a die device with a plurality of protrusion ribs is pressed together on the support plate 10 with macromolecular material, then, again with macromolecular material, epoxy resin mould closure material (Epoxy Molding Compound for example; EMC), inject the space of die device and support plate 10, make macromolecular material be formed on the support plate 10 with a plurality of protrusion ribs.
Then, after finishing the program of macromolecular material, can optionally carry out a baking program, so that macromolecular material solidifies to macromolecular material.Follow again, carry out demoulding program, the die device that will have a plurality of protrusion ribs with solidify after macromolecular material separate to form packaging body 20 by the formed a plurality of through holes 202 of a plurality of protrusion ribs and 204, wherein, a plurality of through holes 202 and 204 are the partial front that expose support plate 10, and the depth-width ratio of through hole 202 is greater than the depth-width ratio of through hole 204, therefore, through hole 202 can be put the district as chip in subsequent handling, in order to put chip (not expression in the drawings); And through hole 204 is in order to form the coupling assembling of a plurality of conductive poles (not expression in the drawings) as subsequent handling chips storehouse.
Then, use cutter (not being shown among the figure) on the surface of packaging body 20, to form many Cutting Roads 210, equally as shown in Figure 2.In this embodiment, the degree of depth of each Cutting Road 210 is 0.5～1 mil (mil), and the width of Cutting Road 210 then is 5 to 25 microns.In a preferred embodiment, this Cutting Road 210 can be mutual vertical interlaced, and the reference line when can be used as actual diced chip.
Then, Fig. 3 is that expression is seated in schematic diagram on the support plate with packaging body with a plurality of chips.At first, be that previous wafer is cut into a plurality of chips 30, then up with the active surface of each chip 30; Then, use fetching device (in figure, not showing) each chip 30 to be picked up and the back side of each chip 30 is seated on the partial front of the support plate 10 that has exposed by active surface; Because, all dispose a plurality of weld pads 302 on the active surface of each chip 30, therefore, fetching device can Direct Recognition goes out the position of each weld pad 302 on each chip 30 its active surface; When fetching device will be positioned over chip 30 on the support plate 10, can each chip 30 accurately be positioned on the front of having exposed to the open air of support plate 10 again by the position on the support plate 10, and be overlying on four faces of each chip 30 by packaging body 20 rings.Therefore, when a plurality of chips 30 reconfigure on support plate 10, just chip 30 can be positioned on the support plate 10 exactly; In addition, put a plurality of chips 30 again, the accuracy in the time of chip can be improved by the relative position in the chip configuration district reconfiguring by the chip configuration district that support plate 10 fronts of being exposed to the open air by a plurality of through holes 202 on the packaging body 20 are constituted.
In addition, in the present embodiment, on the back side of each chip 30, also comprise one deck adhesion layer 40, its objective is when go up in the front (chip disposal area) that each chip 30 is seated in the support plate 10 that has exposed to the open air, can make the back side of each chip 30 be fixed on the front of the support plate 10 that has exposed to the open air by adhesion layer 40, the material of this adhesion layer 40 is the rubber-like adhesion material, for example: silicon rubber (silicone rubber), silicones (silicone resin), elasticity PU, porous PU, acrylic rubber (acrylic rubber) or chip cutting glue.
Then, Fig. 4 is that a plurality of first patterned protection layer of expression are formed on the schematic cross-section on the packaging body.As shown in Figure 4, the formation method of a plurality of first patterned protection layer comprises: earlier first protective layer (not expression in the drawings) is covered on packaging body 20 and each chip 30; Then, utilize semiconductor technology again, form first patterned light blockage layer (not expression in the drawings) on first protective layer; Next, carry out etching step, remove partly first protective layer forming first patterned protection layer 502 on packaging body 20, and expose a plurality of weld pads 302 and a plurality of through hole 204 on the active surface of each chip 30.In this embodiment, the material of first protective layer is tin cream (paste) or two-stage thermosetting cement material (B-stage).
And then, after the position of a plurality of weld pads 302 of determining each chip 30, can use the traditional operation that reroutes (Redistribution Layer; RDL) on a plurality of weld pads 302 that each chip 30 is exposed to the open air; form the metal wire sections 602 of the patterning of a plurality of fan-outs; wherein a plurality of weld pads on the active surface of an end of the metal wire sections 602 of each patterning and each chip 30 302 electrically connect; and partly the other end of patterning metal line sections 602 is to be formed on the first patterned protection layer 502 in the fan-out mode, and fills up a plurality of through holes 204 simultaneously to form conductive pole 610.At this, the formation step of the metal wire sections 602 of a plurality of patternings comprises: form earlier a metal level 60 on first patterned protection layer 502 and cover the weld pad 302 that is exposed to the open air and fill up a plurality of through holes 204 to form a plurality of conductive poles 610, as shown in Figure 5; Then, carry out semiconductor technology, form another patterned light blockage layer (not expression in the drawings) on metal level 60; Be etched with and remove partly metal level 60; metal wire sections 602 with the patterning that forms a plurality of fan-outs; wherein an end of the metal wire sections 602 of part patterning electrically connects a plurality of weld pads 302 of the active surface of a plurality of chips 30; partly the other end of the metal wire sections 602 of a plurality of patternings is to be formed on the first patterned protection layer 502, as shown in Figure 6 in the fan-out mode.
Then, be to utilize semiconductor technology, on the metal wire sections 602 of the patterning of a plurality of fan-outs, form second protective layer 70, with the metal wire sections 602 of the patterning of the active surface that covers each chip 30 and each fan-out, as shown in Figure 7; Then, utilize semiconductor technology equally,, form a plurality of openings 704 on second protective layer 70 and on the surface of extending corresponding to the active surface outside to each chip 30 of the metal wire sections 602 of each patterning; Wherein, forming a plurality of openings 704 on a plurality of second patterned protection layer 702 comprises with the step on the surface of the metal wire sections 602 of the patterning that exposes each fan-out: utilize semiconductor technology, form a patterned light blockage layer (expression in the drawings) earlier above second protective layer 70; Then, be etched with and remove partly second protective layer 70, forming a second patterned protection layer 702, and form the surface of a plurality of openings 704, as shown in Figure 8 with the other end of the metal wire sections 602 of the patterning that exposes each fan-out.At this, the material of second protective layer can be tin cream (paste) or two-stage thermosetting cement material (B-stage) equally.
Then, Fig. 9 is to be illustrated in the schematic cross-section that forms the UBM layer of a plurality of patternings on the surface of the other end of metal wire sections of patterning of each fan-out that has exposed to the open air.As shown in Figure 9, be on the surface of the other end of the metal wire sections 602 of the patterning of each fan-out that exposes, form a UBM layer (expression in the drawings) in the mode of sputter (sputtering); Then, utilize semiconductor technology, on the UBM layer, form a patterned light blockage layer (not expression in the drawings), then, utilization is etched with and removes partly UBM layer,, on the surface of the metal wire sections 602 of the patterning of each fan-out that exposes, and electrically connect with the UBM layer 802 that forms the multiple bar chart caseization with the metal wire sections 602 of a plurality of patternings; The material of UBM layer 802 in the present embodiment can be Ti/Ni or Ti/W.
At last, on the UBM of each patterning layer 802, form a plurality of conductive components 90 again, so that as the chip 30 external contacts that electrically connect; Wherein, this conductive component 90 can be metal coupling (metal bump) or tin ball (solder ball); And can electrically connect with patterning metal line sections 602 by the UBM layer 802 of a plurality of patternings, as shown in figure 10.Then, remove support plate 10 and can carry out last cutting to packaging body afterwards.In the present embodiment, with one chip as the cutting unit, to form the chip finish packaging process one by one, as shown in figure 11.
Then, in Figure 12, be the schematic diagram of the encapsulating structure of expression chip stack.In the present embodiment, be to finish encapsulation and push-down stack on the chip 30 independently separately, its storehouse mode is to form by the conductive component 90 that the upper strata has been finished the conduction end points 610A of conductive pole 610 of chip 30 of encapsulation and the chip that lower floor has finished encapsulation to electrically connect, to form a stack architecture.Wherein, conduction end points 610A and the lower floor of conductive pole 610 that has finished the chip 30 of encapsulation on the upper strata finished and also comprised one between the conductive component 90 of chip of encapsulation and be connected weld pad 92.
Then, Figure 13 is system in package that the chip constituted (System-In-Package of expression by a plurality of difference in functionalitys and size; SIP) vertical view.At this, these chips are chips of different size and function, and it comprises micro treatmenting device (microprocessor means) 30A, storage arrangement (memory means) 30B or storage control device (memory controller means) 30C at least; Wherein have a plurality of weld pad 302A, 302B, 302C on the active surface of each chip 30A, 30B, 30C, and on weld pad 302A, the 302B of each chip 30A, 30B, 30C, 302C, form many strip metals line segment 602, electrically connect adjacent chip 30A, 30B, 30C and electrically connect with conductive component 90 with series connection or mode in parallel.
Figure 14 to Figure 21 is each flow chart of steps that expression forms system-in-package structure.To be expression be seated in schematic diagram on the support plate with packaging body with the chip of different size and function to Figure 14.As shown in figure 14, similarly, it is the packaging body 20 that on support plate 10, forms through hole earlier with a plurality of different aspect ratios, identical in this preceding method of stating of formation method of packaging body 20 of through hole with a plurality of different aspect ratios, no longer add to give unnecessary details at this, the size that is noted that the through hole in the packaging body 20 is corresponding to chip 30A, 30B, the 30C size that will be arranged on the support plate 10.Then, identical with prior statement, be that the wafer that will have difference in functionality cuts, to form a plurality of chip 30A, 30B, 30C, then up with the active surface of chip 30A, the 30B of each difference in functionality, 30C with different size and function; Then, use fetching device (not shown in the diagram) respectively chip 30A, 30B, the 30C of each difference in functionality and size to be picked up, and chip 30A, the 30B of each difference in functionality, the back side of 30C are seated on the partial front of the support plate 10 that has exposed by active surface; Because, all dispose a plurality of weld pad 302A, 302B, 302C on chip 30A, the 30B of each difference in functionality, the active surface of 30C, therefore, fetching device can Direct Recognition go out each weld pad 302A, the 302B on each chip 30A, 30B, its active surface of 30C, the position of 302C; When fetching device will be positioned over chip 30A, 30B, the 30C of each difference in functionality on the support plate 10, can be again by the position on the support plate 10, on chip 30A, the 30B of each difference in functionality, the front of having exposed to the open air that 30C accurately is positioned over support plate 10.Therefore, when a plurality of chip 30A, 30B, 30C with difference in functionality reconfigure on support plate 10, just chip 30A, 30B, the 30C of each difference in functionality can be positioned on the support plate 10 exactly; In addition, the chip 30 of a plurality of difference in functionalitys is put in the chip configuration district that is constituted by support plate 10 fronts of being exposed to the open air by a plurality of through holes on the packaging body 20 again, the accuracy in the time of can being improved chip by the relative position in the chip configuration district and reconfigure.
In addition, in the present embodiment, on the back side of chip 30A, the 30B of each difference in functionality, 30C, also comprise an adhesion layer 40, its objective is when chip 30A, 30B when each difference in functionality, 30C put to the front of the support plate 10 that has exposed to the open air, chip 30A, the 30B of each difference in functionality, the back side of 30C are fixed on the front of the support plate 10 that has exposed to the open air.In this embodiment, the material of adhesion layer 40 is the rubber-like adhesion material, and it can be silicon rubber (silicone rubber), silicones (silicone resin), elasticity PU, porous PU, acrylic rubber (acrylic rubber) or chip cutting glue.
Then, Figure 15 is that a plurality of first patterned protection layer of expression are formed on the schematic diagram on the packaging body.Its formation method comprises: earlier first protective layer (expression in the drawings) is formed on chip 30A, 30B, the 30C of packaging body 20 and each difference in functionality; Then, utilize semiconductor technology again, form a patterned light blockage layer (not expression in the drawings) on first protective layer; Next; be etched with and remove part first protective layer to form first patterned protection layer 502 on packaging body 20; and expose a plurality of weld pad 302A, 302B, 302C on the active surface of chip 30A, 30B, 30C of each difference in functionality, and expose a plurality of through holes 204.At this, the material of first protective layer can be tin cream (paste), two-stage thermosetting formula glue material (B-stage) or polyimide.
And then, after the position of a plurality of weld pad 302A that determine chip 30A, the 30B of each difference in functionality, 30C, 302B, 302C, can use the traditional operation that reroutes (Redistribution Layer; RDL) on a plurality of weld pad 302A that chip 30A, 30B, the 30C of each difference in functionality are exposed to the open air, 302B, 302C; form the metal wire sections 602 of the patterning of a plurality of fan-outs; wherein a plurality of weld pad 302A on the active surface of chip 30A, the 30B of an end of the metal wire sections 602 of each patterning and each difference in functionality, 30C, 302B, 302C electrically connect; and partly the other end of patterning metal line sections 602 is to be formed on the first patterned protection layer 502 in the fan-out mode, and fill up a plurality of through holes 204 simultaneously to form a plurality of conductive poles 610.At this, the formation step of the metal wire sections 602 of a plurality of patternings comprises: form a metal level 60 earlier on first patterned protection layer 60, and cover the weld pad 302 that is exposed to the open air and fill up a plurality of through holes 204, to form a plurality of conductive poles 610, as shown in figure 16; Then, carry out semiconductor technology, form another patterned light blockage layer (not expression in the drawings) on metal level 60; Be etched with and remove partly metal level 60; metal wire sections 602 with the patterning that forms a plurality of fan-outs; wherein partly an end of the metal wire sections 602 of patterning electrically connects a plurality of weld pad 302A, 302B, the 302C of active surface of chip 30A, 30B, the 30C of each difference in functionality; partly the other end of the metal wire sections 602 of a plurality of patternings is in the fan-out mode; be formed on the first patterned protection layer 502, as shown in figure 17.
Then, be to utilize semiconductor technology, on the metal wire sections 602 of the patterning of a plurality of fan-outs, form second protective layer 70, with the metal wire sections 602 of the patterning of the active surface of the chip 30A, the 30B that cover each difference in functionality, 30C and each fan-out, as shown in figure 18; Then, utilize semiconductor technology equally,, form a plurality of openings on second protective layer 70 and on the surface of extending corresponding to the active surface outside of chip 30A, the 30B to each difference in functionality of the metal wire sections 602 of each patterning, 30C; Wherein, forming a plurality of openings on a plurality of second patterned protection layer 702 comprises with the step on the surface of the metal wire sections 602 of the patterning that exposes each fan-out: utilize semiconductor technology, form a patterned light blockage layer (expression in the drawings) earlier above second protective layer 70; Then, be etched with and remove partly second protective layer 70,, form the surface of a plurality of openings, as shown in figure 19 with the other end of the metal wire sections 602 of the patterning that exposes each fan-out to form a second patterned protection layer 702.At this, the material of second protective layer can be tin cream (paste), two-stage thermosetting cement material (B-stage) or polyimide.
Then, Figure 20 is to be illustrated in the schematic diagram that forms the UBM layer of a plurality of patternings on the surface of the other end of metal wire sections of patterning of each fan-out that exposes.As shown in figure 20, be on the surface of the other end of the metal wire sections 602 of the patterning of each fan-out that exposes, form a UBM layer (expression in the drawings) in the mode of sputter (sputtering); Then, utilize semiconductor technology, on the UBM layer, form a patterned light blockage layer (not expression in the drawings), then, utilization is etched with and removes partly UBM layer,, on the surface of the metal wire sections 602 of the patterning of each fan-out that exposes, and electrically connect with the UBM layer 802 that forms the multiple bar chart caseization with the metal wire sections 602 of a plurality of patternings; The material of UBM layer 802 in the present embodiment can be Ti/Ni or Ti/W.
At last, on the UBM of each patterning layer 802, form a plurality of conductive components 90 again, so that as chip 30A, the 30B of each difference in functionality, the contact that 30C externally electrically connects; Wherein, this conductive component 90 can be metal coupling (metal bump) or tin ball (solder ball); And can form electric connection by the UBM layer 802 of a plurality of patternings and the metal wire sections 602 of a plurality of patternings.At last, support plate 10 is removed, promptly can finish the encapsulating structure of multicore sheet, as shown in figure 21.
Though the present invention discloses as above with aforesaid preferred embodiment; yet it is not in order to limit the present invention; any those of ordinary skill of being familiar with present technique; without departing from the spirit and scope of the present invention; when can making all changes that is equal to or replacement, therefore scope of patent protection of the present invention must be looked being as the criterion that the appended the application's claim scope of this specification defined.

Claims (4)

1. the method for packing of a chip comprises:
One support plate is provided, has a positive and back side;
One die device is provided, disposes the protrusion rib of a plurality of each intervals in this die device;
Form a packaging body on this front of this support plate, and have a plurality of through holes in this packaging body exposing the part front of this support plate, and these through holes protrude ribs by these and are formed;
Attaching a chip on this support plate, is with an active surface of this chip up, and a back side of this chip is attached on this front of having exposed to the open air of this support plate by an adhesion layer, and is formed with a plurality of weld pads on this active surface of this chip;
Form a first patterned protection layer on this packaging body and part active surface, and expose these weld pads on this active surface of this chip and expose these through holes at this chip;
Form a metal level and cover on this first patterned protection layer of part and fill up these through holes, and form and electrically connect with these weld pads on this active surface of this chip;
Form a second patterned protection layer on this first patterned protection layer and this metal level of cover part to expose the part surface of this metal level;
The UBM layer that forms a plurality of patternings and forms with this metal level and to electrically connect on this part surface of this metal level that has exposed to the open air;
Forming a plurality of conductive components, is that UBM layer and this metal level formation of these conductive components by these patternings is electrically connected; And
Remove this support plate, to form a chip-packaging structure.
2. method for packing according to claim 1 is characterized in that the method that forms these through holes comprises:
Form a polymer material layer on this front of this support plate;
Covering this die device to this polymer material layer, is downward and this polymer material layer pressing of these protrusion ribs by this die device; And
Break away from this die device, forming this packaging body, and in this packaging body, form these through holes and expose the part front of this support plate.
3. the method for packing of a multicore sheet comprises:
One support plate is provided, has a positive and back side;
One die device is provided, disposes the protrusion rib of a plurality of each intervals in this die device;
Form a packaging body on this front of this support plate, and have a plurality of through holes in this packaging body exposing the part front of this support plate, and these through holes protrude ribs by these and are formed;
Attaching a plurality of chips on this support plate, is with an active surface of each this chip up, and a back side of each this chip is attached on this front of having exposed to the open air of this support plate by an adhesion layer, and is formed with a plurality of weld pads on this active surface of this chip;
Form a first patterned protection layer on this packaging body and this active surface of part, and expose these weld pads on this active surfaces of these chips and expose these through holes at these chips;
Forming a metal level covers this first protective layer of this patterning of part and fills up these through holes to form a plurality of conductive poles, and form and electrically connect with these weld pads on this active surface of this chip, an end that wherein runs through these conductive poles of this packaging body forms a conduction end points;
Form a second patterned protection layer on this first patterned protection layer and this metal level of cover part to expose the part surface of this metal level;
The UBM layer that forms a plurality of patternings and electrically connects with this metal level on this part surface of this metal level that has exposed to the open air;
Forming a plurality of conductive components, is that UBM layer and this metal level formation of these conductive components by these patternings is electrically connected; And
Remove this support plate, to form a chip-packaging structure.
4. method for packing according to claim 3 is characterized in that the method that forms these through holes comprises:
Form a polymer material layer on this front of this support plate;
Covering this die device to this polymer material layer, is downward and this polymer material layer pressing of these protrusion ribs by this die device; And
Break away from this die device, forming this packaging body, and in this packaging body, form these through holes and expose the part front of this support plate.
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