CN101621043B - 标准芯片尺寸封装 - Google Patents
标准芯片尺寸封装 Download PDFInfo
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- CN101621043B CN101621043B CN2009101460730A CN200910146073A CN101621043B CN 101621043 B CN101621043 B CN 101621043B CN 2009101460730 A CN2009101460730 A CN 2009101460730A CN 200910146073 A CN200910146073 A CN 200910146073A CN 101621043 B CN101621043 B CN 101621043B
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- 229910000679 solder Inorganic materials 0.000 claims description 60
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 230000003044 adaptive effect Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000009434 installation Methods 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 239000004744 fabric Substances 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 18
- 235000012431 wafers Nutrition 0.000 description 68
- 238000005538 encapsulation Methods 0.000 description 58
- 238000010586 diagram Methods 0.000 description 27
- 239000004065 semiconductor Substances 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000010936 titanium Substances 0.000 description 7
- 238000002161 passivation Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- RPPNJBZNXQNKNM-UHFFFAOYSA-N 1,2,4-trichloro-3-(2,4,6-trichlorophenyl)benzene Chemical compound ClC1=CC(Cl)=CC(Cl)=C1C1=C(Cl)C=CC(Cl)=C1Cl RPPNJBZNXQNKNM-UHFFFAOYSA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229920006335 epoxy glue Polymers 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L23/495—Lead-frames or other flat leads
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2924/1304—Transistor
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- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201210414976.4A CN102938383B (zh) | 2008-06-30 | 2009-06-05 | 标准芯片尺寸封装 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US12/217,136 US8053891B2 (en) | 2008-06-30 | 2008-06-30 | Standing chip scale package |
US12/217,136 | 2008-06-30 |
Related Child Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201010528045.8A Division CN102034802B (zh) | 2008-06-30 | 2009-06-05 | 标准芯片尺寸封装的结构和方法 |
CN201210413924.5A Division CN102945811B (zh) | 2008-06-30 | 2009-06-05 | 标准芯片尺寸封装 |
CN201210414976.4A Division CN102938383B (zh) | 2008-06-30 | 2009-06-05 | 标准芯片尺寸封装 |
Publications (2)
Publication Number | Publication Date |
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CN101621043A CN101621043A (zh) | 2010-01-06 |
CN101621043B true CN101621043B (zh) | 2013-08-07 |
Family
ID=41446400
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
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CN201210413924.5A Active CN102945811B (zh) | 2008-06-30 | 2009-06-05 | 标准芯片尺寸封装 |
CN2009101460730A Active CN101621043B (zh) | 2008-06-30 | 2009-06-05 | 标准芯片尺寸封装 |
CN201210414976.4A Expired - Fee Related CN102938383B (zh) | 2008-06-30 | 2009-06-05 | 标准芯片尺寸封装 |
CN201010528045.8A Active CN102034802B (zh) | 2008-06-30 | 2009-06-05 | 标准芯片尺寸封装的结构和方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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CN201210413924.5A Active CN102945811B (zh) | 2008-06-30 | 2009-06-05 | 标准芯片尺寸封装 |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
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CN201210414976.4A Expired - Fee Related CN102938383B (zh) | 2008-06-30 | 2009-06-05 | 标准芯片尺寸封装 |
CN201010528045.8A Active CN102034802B (zh) | 2008-06-30 | 2009-06-05 | 标准芯片尺寸封装的结构和方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8053891B2 (zh) |
CN (4) | CN102945811B (zh) |
TW (1) | TWI392038B (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
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US8703543B2 (en) * | 2009-07-14 | 2014-04-22 | Honeywell International Inc. | Vertical sensor assembly method |
CN102315203A (zh) * | 2010-07-08 | 2012-01-11 | 环鸿科技股份有限公司 | 芯片与基材的组装结构 |
US20120119345A1 (en) * | 2010-11-15 | 2012-05-17 | Cho Sungwon | Integrated circuit packaging system with device mount and method of manufacture thereof |
CN102849674B (zh) * | 2011-11-02 | 2015-04-29 | 杭州士兰集成电路有限公司 | 一种垂直传感器的封装方法 |
ITTO20120174A1 (it) * | 2012-02-27 | 2013-08-28 | St Microelectronics Srl | Dispositivo elettronico incapsulato comprendente circuiti elettronici integrati dotati di antenne di ricetrasmissione |
CN102623415A (zh) * | 2012-04-19 | 2012-08-01 | 日月光半导体制造股份有限公司 | 半导体封装结构及其制造方法 |
US8816513B2 (en) * | 2012-08-22 | 2014-08-26 | Texas Instruments Incorporated | Electronic assembly with three dimensional inkjet printed traces |
JP6054115B2 (ja) | 2012-09-21 | 2016-12-27 | オリンパス株式会社 | マルチチップ半導体装置 |
US9355444B2 (en) * | 2012-09-28 | 2016-05-31 | Skyworks Solutions, Inc. | Systems and methods for processing packaged radio-frequency modules identified as being potentially defective |
TWI488268B (zh) * | 2013-03-28 | 2015-06-11 | Ind Tech Res Inst | 半導體元件 |
JP2015005664A (ja) * | 2013-06-21 | 2015-01-08 | 株式会社東芝 | 電子部品およびその製造方法 |
CN104576416A (zh) * | 2013-10-24 | 2015-04-29 | 扬州倍英斯微电子有限公司 | 一种双层凸点二极管芯片制备方法 |
CN103943573B (zh) * | 2013-12-31 | 2016-10-05 | 西安汐特电子科技有限公司 | 一种集成电路内部封装方法 |
US9281258B1 (en) * | 2014-10-30 | 2016-03-08 | Semiconductor Components Industries, Llc | Chip scale packages and related methods |
DE102015108909B4 (de) * | 2015-06-05 | 2021-02-18 | Infineon Technologies Ag | Anordnung mehrerer Leistungshalbleiterchips und Verfahren zur Herstellung derselben |
JP6261709B2 (ja) * | 2016-11-30 | 2018-01-17 | オリンパス株式会社 | マルチチップ半導体装置 |
CN108133924B (zh) * | 2017-12-20 | 2019-12-31 | 江苏冠达通电子科技有限公司 | 半导体芯片封装结构及其方法 |
US10847478B2 (en) * | 2018-02-27 | 2020-11-24 | Amkor Technology Singapore Holding Pte. Ltd. | Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures |
Family Cites Families (16)
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US4426689A (en) * | 1979-03-12 | 1984-01-17 | International Business Machines Corporation | Vertical semiconductor integrated circuit chip packaging |
JP3937265B2 (ja) * | 1997-09-29 | 2007-06-27 | エルピーダメモリ株式会社 | 半導体装置 |
TW408411B (en) | 1999-03-31 | 2000-10-11 | Huang Jr Gung | Semiconductor chip scale package |
JP2001007280A (ja) * | 1999-06-24 | 2001-01-12 | Mitsubishi Electric Corp | 半導体装置およびその実装構造 |
JP4646284B2 (ja) | 2000-02-10 | 2011-03-09 | インターナショナル レクティフィアー コーポレイション | 単一表面上のバンプコンタクトを有する垂直伝導フリップチップ半導体デバイス |
US6624522B2 (en) | 2000-04-04 | 2003-09-23 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
US6798044B2 (en) * | 2000-12-04 | 2004-09-28 | Fairchild Semiconductor Corporation | Flip chip in leaded molded package with two dies |
US6646329B2 (en) | 2001-05-15 | 2003-11-11 | Fairchild Semiconductor, Inc. | Power chip scale package |
TW511262B (en) * | 2001-12-26 | 2002-11-21 | Gen Semiconductor Of Taiwan Lt | Chip scale package for power semiconductor device |
US6830959B2 (en) * | 2002-01-22 | 2004-12-14 | Fairchild Semiconductor Corporation | Semiconductor die package with semiconductor die having side electrical connection |
KR100452818B1 (ko) | 2002-03-18 | 2004-10-15 | 삼성전기주식회사 | 칩 패키지 및 그 제조방법 |
TW583763B (en) * | 2003-01-17 | 2004-04-11 | Comchip Technology Co Ltd | Discrete circuit component having an up-right circuit die with lateral electrical connections |
US6870261B2 (en) * | 2003-02-26 | 2005-03-22 | Comchip Technology Co., Ltd. | Discrete circuit component having an up-right circuit die with lateral electrical connections |
US7095226B2 (en) * | 2003-12-04 | 2006-08-22 | Honeywell International, Inc. | Vertical die chip-on-board |
JP4377269B2 (ja) * | 2004-03-19 | 2009-12-02 | Necエレクトロニクス株式会社 | 半導体装置 |
CN101276762B (zh) * | 2007-03-26 | 2010-07-21 | 矽品精密工业股份有限公司 | 多芯片堆叠结构及其制法 |
-
2008
- 2008-06-30 US US12/217,136 patent/US8053891B2/en active Active
-
2009
- 2009-06-05 CN CN201210413924.5A patent/CN102945811B/zh active Active
- 2009-06-05 CN CN2009101460730A patent/CN101621043B/zh active Active
- 2009-06-05 CN CN201210414976.4A patent/CN102938383B/zh not_active Expired - Fee Related
- 2009-06-05 CN CN201010528045.8A patent/CN102034802B/zh active Active
- 2009-06-06 TW TW098118886A patent/TWI392038B/zh active
-
2010
- 2010-08-09 US US12/852,717 patent/US8058727B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN102938383B (zh) | 2015-12-16 |
US20090321929A1 (en) | 2009-12-31 |
TW201001579A (en) | 2010-01-01 |
CN102945811A (zh) | 2013-02-27 |
US20100320531A1 (en) | 2010-12-23 |
US8058727B2 (en) | 2011-11-15 |
CN102945811B (zh) | 2015-04-15 |
CN102034802A (zh) | 2011-04-27 |
TWI392038B (zh) | 2013-04-01 |
CN101621043A (zh) | 2010-01-06 |
CN102938383A (zh) | 2013-02-20 |
US8053891B2 (en) | 2011-11-08 |
CN102034802B (zh) | 2014-05-14 |
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Denomination of invention: Standing chip scale package Effective date of registration: 20191210 Granted publication date: 20130807 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |
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