CN101661917B - Chip packaging structure of resin core column - Google Patents
Chip packaging structure of resin core column Download PDFInfo
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- CN101661917B CN101661917B CN2009100274513A CN200910027451A CN101661917B CN 101661917 B CN101661917 B CN 101661917B CN 2009100274513 A CN2009100274513 A CN 2009100274513A CN 200910027451 A CN200910027451 A CN 200910027451A CN 101661917 B CN101661917 B CN 101661917B
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- chip
- resin core
- layer
- wiring metal
- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The invention relates to a chip packaging structure of a resin core column, belonging to the technical field of chip packaging. The chip packaging structure of the resin core column comprises a chip body (101), a chip electrode (102), a chip surface passivation layer (103), a first rewiring metal layer (104), a resin core (105), a second rewiring metal layer (106), a rewiring metal surface protection layer (107) and a solder ball protruding point (108). The chip electrode (102) is arranged on the chip body; the chip surface passivation layer (103) is compounded on the surface of the chip body as well as an outer edge and a surface periphery of the chip electrode; the first rewiring metal layer (104) covers the chip surface passivation layer (103) to expose the middle part of the surface of the chip electrode (102) of the chip surface passivation layer (103); the resin core (105) is arranged on the first rewiring metal layer (104); the second rewiring metal layer (106) covers the periphery of the resin core (105); and the solder ball protruding point (108) is arranged on a metal layer (106A) below the protruding point in a protruding way. The chip packaging structure can solve the problem of low stress of the solder ball protruding point.
Description
(1) technical field
The present invention relates to a kind of chip packaging structure of resin core column.Belong to the chip encapsulation technology field.
(2) background technology
Traditionally, IC chip and outside being electrically connected are in the mode of bonding the I/O on the chip to be connected to package carrier and to realize through packaging pin with metal lead wire.Along with the expansion with integrated scale dwindled of IC chip features size, the spacing of I/O constantly reduces, quantity is on the increase.When the I/O spacing narrows down to 70um when following, Wire Bonding Technology is just no longer suitable, must seek new technological approaches.Wafer-Level Packaging Technology is utilized the film technology that distributes again, I/O can be distributed on the whole surface of IC chip and no longer only be confined to the neighboring area of narrow IC chip, thereby solved the problem that is electrically connected of highly dense plating, thin space I/O chip.
Wafer level packaging is a kind of CSP through improving and improving based on the BGA technology, has demonstrated fully the technical advantage of BGA, CSP.It has the advantage of many uniquenesses: 1. encapsulation process efficient height, and it is made with the mass production processes of disk form; 2. the advantage that has Flip-Chip Using is promptly light, thin, short, little; 3. wafer level packaging production facility expense is low, can make full use of the manufacturing equipment of disk, need not invest and build packing producing line in addition; 4. the chip design of wafer level packaging and package design can be unified to consider, carry out simultaneously that this will improve design efficiency, reduce design cost; 5. wafer level packaging from chip manufacturing, be encapsulated into the whole process that product mails to the user, intermediate link significantly reduces, the cycle shortens a lot, this will cause the reduction of cost; 6. the number of chips on the cost of wafer level packaging and each disk is closely related, and the chip-count on the disk is many more, and the cost film of wafer level packaging distribution circle sheet level chip scale package again is one of wafer level packaging technology.Because its cost is lower, and satisfy the requirement of portable product plate level application reliability standard, its range of application is more and more wider.
Current most typical film Wiring technique again is, adopt PI or BCB as the dielectric layer that distributes again, Cu or Ni adopt sputtering method deposit salient point bottom metal layers (UBM) as the line metal that distributes again, with planting ball or silk screen print method deposit soldering paste and refluxing, form the soldered ball solder bumps.Solder bumps is a chip stress bearing position in use, increases at chip I/O number, and under the trend that chip size increases, the stress distribution of solder bumps directly influences the reliability of welding spot structure and to the influence of the electrical property of wiring underlayer.Though present wire structures again part has satisfied die stress buffer problem under the salient point, has two defectives: 1) when chip electrode did not need to connect up transfer again, the stress buffer ability of current wire structures again can't embody; 2) intensity of thin film dielectrics layer own is limited under the salient point, is difficult to satisfy the product structure reliability requirement under the big condition of stress.Therefore, the solder bumps technology of seeking the low stress high-strength structure is the target that industry is constantly pursued always.
(3) summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, provide a kind of and can increase, improve the chip packaging structure of resin core column of the integrally-built unfailing performance of chip dielectric strength under the stress buffer of solder bumps and the salient point.
The object of the present invention is achieved like this: a kind of chip packaging structure of resin core column; it is characterized in that described chip-packaging structure comprises the chip body; chip electrode; the chip surface passivation layer; ground floor is the wiring metal layer again; resin core; the second layer is the wiring metal layer again; wiring metal sealer and solder bumps again; described chip electrode is arranged on the chip body; the chip surface passivation layer is compounded in chip body surface and chip electrode outer rim and surperficial neighboring; and the mid portion exposed chip surface passivation layer on chip electrode surface; described ground floor wiring metal layer again covers the chip electrode surface mid portion of chip surface passivation layer and exposed chip surface passivation layer; described resin core is arranged on ground floor again on the wiring metal layer; described second layer wiring metal layer again is coated on the periphery of resin core; described ground floor is the wiring metal layer again; the resin core and the second layer wiring metal layer again constitute resin core column; the described sealer of wiring metal again covers the chip surface passivation layer; ground floor is wiring metal layer and the second layer surface of wiring metal layer more again; and expose the ubm layer at resin core top, described solder bumps is protruded and is arranged on the described ubm layer.
Ground floor wiring metal layer again has only the function that connects up again, and the second layer is the existing function that connects up again of wiring metal layer again, has the function of metal under the salient point again, with soldered ball wetting formation takes place and reliably be connected.
Beneficial effect of the present invention is:
By making resin core metal column structure, make the resin core metal column also have the ability of stress buffer, thereby increased dielectric strength under the stress buffer of solder bumps and the salient point, improved integrally-built unfailing performance, utilize the characteristics of this structural manufacturing process simultaneously, realize the wiring function again of chip electrode.
(4) description of drawings
Fig. 1 is the vertical view of chip packaging structure of resin core column of the present invention.
Fig. 2 is the a-a cut-away view one of Fig. 1.
Fig. 3 is the a-a cut-away view two of Fig. 1.
Fig. 4 is the a-a cut-away view three of Fig. 1.
Fig. 5 is the b-b cut-away view of Fig. 1.
Among the figure: chip body 101, chip electrode 102, chip surface passivation layer 103, ground floor be wiring metal layer 104, resin core 105, second layer wiring metal layer 106, ubm layer 106A, wiring metal sealer 107, solder bumps 108 more again.
(5) embodiment
Chip packaging structure of resin core column of the present invention, mainly by chip body 101, chip electrode 102, chip surface passivation layer 103, ground floor again wiring metal layer 104, resin core 105, the second layer again wiring metal layer 106, wiring metal sealer 107 and solder bumps 108 are formed again.Described chip electrode 102 is arranged on the chip body 101, chip surface passivation layer 103 is compounded in chip body 101 surfaces and chip electrode 102 outer rims and surperficial neighboring, and the mid portion exposed chip surface passivation layer 103 on chip electrode 102 surfaces, described ground floor wiring metal layer 104 again covers the chip electrode 102 surperficial mid portions of chip surface passivation layer 103 and exposed chip surface passivation layer 103, described resin core 105 is arranged on ground floor again on the wiring metal layer 104, described second layer wiring metal layer 106 again is coated on the periphery of resin core 105, and described ground floor is wiring metal layer 104 again, the resin core 105 and the second layer wiring metal layer 106 again constitute resin core column.There are two kinds of versions the position of described resin core column: a kind of chip electrode 102 tops that are positioned at, as shown in Figure 2, another kind is positioned on the chip surface passivation layer 103 on chip electrode 102 next doors.
The described sealer of wiring metal again 107 covers chip surface passivation layer 103, ground floor wiring metal layer 104 and the second layer surface of wiring metal layer 106 more again; and expose the ubm layer 106A at resin core 105 tops, described solder bumps 108 is protruded and is arranged on the described ubm layer 106A.
Its implementation procedure is:
1) comprises that by sputter or plating the mode of chemical plating forms ground floor wiring metal layer 104 again on the chip electrode 102 surperficial mid portions and chip surface passivation layer 103 surfaces of exposed chip surface passivation layer 103.
2) mode of utilization printing or photoetching forms resin core 105 on the wiring metal layer 104 again at ground floor.
3) comprise that by sputter or plating the mode of chemical plating forms second layer wiring metal layer 106 again in the periphery of resin core 105,
4) to chip surface passivation layer 103, ground floor again wiring metal layer 104 and the second layer carry out surface coverage or the entire chip surface covered with wiring metal sealer 107 again in the surface of wiring metal layer 106 again, and expose the ubm layer 106A at resin core 105 tops.
5) plant ball or printing soldering paste at described ubm layer 106A place, and the formation solder bumps 108 that refluxes.
Described resin core 105 is an insulating polymeric material, as polyimides, epoxy resin etc.
Described ground floor again wiring metal layer 104 and the second layer again wiring metal layer 106 be the single or multiple lift metal material.
The described sealer of wiring metal again 107 is an insulating polymeric material, as polyimides, epoxy resin etc.
Claims (8)
1. chip packaging structure of resin core column; it is characterized in that described chip-packaging structure comprises chip body (101); chip electrode (102); chip surface passivation layer (103); ground floor is wiring metal layer (104) again; resin core (105); the second layer is wiring metal layer (106) again; wiring metal sealer (107) and solder bumps (108) again; described chip electrode (102) is arranged on the chip body (101); chip surface passivation layer (103) is compounded in chip body (101) surface and chip electrode (102) outer rim and surperficial neighboring; and the mid portion exposed chip surface passivation layer (103) on chip electrode (102) surface; described ground floor wiring metal layer (104) again covers the surperficial mid portion of chip electrode (102) of chip surface passivation layer (103) and exposed chip surface passivation layer (103); described resin core (105) is arranged on ground floor again on the wiring metal layer (104); described second layer wiring metal layer (106) again is coated on the periphery of resin core (105); described ground floor is wiring metal layer (104) again; the resin core (105) and the second layer wiring metal layer (106) again constitute resin core column; the described sealer of wiring metal again (107) covers chip surface passivation layer (103); ground floor is wiring metal layer (104) and the second layer surface of wiring metal layer (106) more again; and expose the ubm layer (106A) at resin core (105) top, described solder bumps (108) is protruded and is arranged on the described ubm layer (106A).
2. a kind of chip packaging structure of resin core column according to claim 1 is characterized in that the position of described resin core column is positioned at chip electrode (102) top.
3. a kind of chip packaging structure of resin core column according to claim 1 is characterized in that the position of described resin core column is positioned on the chip surface passivation layer (103) on chip electrode (102) next door.
4. according to claim 1,2 or 3 described a kind of chip packaging structure of resin core column, it is characterized in that described resin core (105) is an insulating polymeric material.
5. a kind of chip packaging structure of resin core column according to claim 4 is characterized in that described insulating polymeric material is polyimides or epoxy resin.
6. according to claim 1,2 or 3 described a kind of chip packaging structure of resin core column, it is characterized in that the described sealer of wiring metal again (107) is an insulating polymeric material.
7. a kind of chip packaging structure of resin core column according to claim 6 is characterized in that described insulating polymeric material is polyimides or epoxy resin.
8. according to claim 1,2 or 3 described a kind of chip packaging structure of resin core column, it is characterized in that described ground floor again wiring metal layer (104) and the second layer again wiring metal layer (106) be the single or multiple lift metal material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100274513A CN101661917B (en) | 2009-05-11 | 2009-05-11 | Chip packaging structure of resin core column |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100274513A CN101661917B (en) | 2009-05-11 | 2009-05-11 | Chip packaging structure of resin core column |
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| Publication Number | Publication Date |
|---|---|
| CN101661917A CN101661917A (en) | 2010-03-03 |
| CN101661917B true CN101661917B (en) | 2011-06-22 |
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| CN2009100274513A Active CN101661917B (en) | 2009-05-11 | 2009-05-11 | Chip packaging structure of resin core column |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102244061A (en) * | 2011-07-18 | 2011-11-16 | 江阴长电先进封装有限公司 | Low-k chip package structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6277669B1 (en) * | 1999-09-15 | 2001-08-21 | Industrial Technology Research Institute | Wafer level packaging method and packages formed |
| CN201402804Y (en) * | 2009-05-11 | 2010-02-10 | 江阴长电先进封装有限公司 | Novel resin core column chip packaging structure |
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2009
- 2009-05-11 CN CN2009100274513A patent/CN101661917B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6277669B1 (en) * | 1999-09-15 | 2001-08-21 | Industrial Technology Research Institute | Wafer level packaging method and packages formed |
| CN201402804Y (en) * | 2009-05-11 | 2010-02-10 | 江阴长电先进封装有限公司 | Novel resin core column chip packaging structure |
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| CN101661917A (en) | 2010-03-03 |
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