CN101681812A - 使用自组装材料的间距倍增 - Google Patents

使用自组装材料的间距倍增 Download PDF

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CN101681812A
CN101681812A CN200880018731A CN200880018731A CN101681812A CN 101681812 A CN101681812 A CN 101681812A CN 200880018731 A CN200880018731 A CN 200880018731A CN 200880018731 A CN200880018731 A CN 200880018731A CN 101681812 A CN101681812 A CN 101681812A
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block copolymer
self
block
substrate
layer
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CN101681812B (zh
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古尔特杰·桑胡
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Micron Technology Inc
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Abstract

使用自组装材料(例如，嵌段共聚物)作为用于实现间距倍增的心轴(162)。在衬底(110)上方沉积所述共聚物并引导其自组装成所需图案。选择性地移除形成所述嵌段共聚物的嵌段(164)中的一者。将剩余嵌段用作用于实现间距倍增的心轴(162)。在嵌段(162)上方覆盖沉积间隔件材料。所述间隔件材料经受间隔件蚀刻以在所述心轴(162)的侧壁上形成间隔件。选择性地移除所述心轴(162)以留下独立的间隔件。所述间隔件可用作间距倍增的掩模特征以在下伏衬底(110)中界定图案。

Description

使用自组装材料的间距倍增
相关申请案交叉参考
本申请案与以下申请案有关：2006年3月23日提出申请、名称为形貌引导的图案化的格泰吉桑达胡(Gurtej Sandhu)的第11/389,581号美国专利申请案(代理人档案号MICRON.342A)及2006年6月2日提出申请、名称为基于形貌的图案化的格泰吉桑达胡(Gurtej Sandhu)的第11/445,907号美国专利申请案(代理人档案号MICRON.349A)。这些参考资料的每一者的全部揭示内容均以引用的方式并入本文中。
技术领域
本发明涉及掩模形成，包含用于制造集成电路的印刷技术。
背景技术
由于许多因素(其中包含对增加的便携性、计算能力、存储器容量及能量效率的需求)，集成电路的大小不断减小。形成集成电路的组成特征(例如，电装置及互连线)的大小也持续降低以促进此大小减小。
例如，在存储器电路或装置(例如：动态随机存取存储器(DRAM)、快闪存储器、静态随机存取存储器(SRAM)、铁电(FE)存储器等)中，降低特征大小的趋势是明显的。举一个实例来说，DRAM通常包含数百万个相同的电路元件，称作存储器单元。存储器单元通常由两个电装置组成：存储电容器及存取场效应晶体管。每一存储器单元都是可存储一个数据位(二进制数字)的可寻址位置。可通过晶体管将位写入到单元且可通过感测电容器中的电荷读取所述位。某些存储器技术采用可充当存储装置及开关两者的元件(例如，采用掺杂银的硫系玻璃的枝状存储器)，且某些非易失性存储器不需要为每一单元均使用开关(例如，磁阻RAM)，也不需要将开关并入到存储器元件中(例如，快闪存储器的EEPROM)。
在另一实例中，快闪存储器通常包含数百万个快闪存储器单元，其含有可保持电荷的浮动栅极场效应晶体管。浮动栅极中存在电荷还是不存在电荷确定存储器单元的逻辑状态。可通过将电荷注入到单元或从单元中移除电荷来将位写入到所述单元。快闪存储器单元可以不同架构配置连接，每一架构配置具有用于读取位的不同方案。在“NOR”架构配置中，每一存储器单元均耦合到位线且可个别地进行读取。在“NAND”架构配置中，存储器单元对准成单元“串”，且激活整个位线来存取单元串的一者中的数据。
一般而言，通过降低构成存储器单元的电装置的大小及存取存储器单元的导线的大小，可使存储器装置更小。另外，可通过将更多的存储器单元装配于存储器装置的给定区域上来增加存储容量。然而，减小特征大小的需要可更普遍地适用于集成电路，其中包含通用及专用处理器。
不断减小特征大小对用于形成所述特征的技术提出越来越高的要求。例如，一般使用光刻来图案化这些特征。通常，光刻涉及使光透过光罩并将所述光会聚到光化学活性光致抗蚀剂材料上。正如幻灯片具有可被投射到屏幕上的图像，所述光罩通常具有可被转移到衬底的图案。通过引导光或辐射透过光罩，可将光罩中的图案会聚在光致抗蚀剂上。所述光或辐射导致光致抗蚀剂的被照明部分中发生化学变化，从而允许这些部分相对于处于阴影中的部分选择性地被保留或被移除(此取决于使用了正性光致抗蚀剂还是负性光致抗蚀剂)。因此，经暴露部分与未暴露部分在光致抗蚀剂中形成图案。
因为平版印刷通常通过将光或辐射投射到表面上来实现，所以特定平版印刷技术的最终分辨率取决于诸如光学器件及光或辐射波长的因素。例如，将良好界定的图案会聚到抗蚀剂上的能力取决于特征的大小及投射穿过光罩的辐射的波长。应了解，由于衍射以及其它原因，分辨率随着波长的增加而减小。因此，随着特征大小减小，形成具有良好分辨率的特征通常需要较短波长辐射。
连同具有特定波长的辐射，光刻利用与所述辐射相适宜的光致抗蚀剂。在经过显影之后，光致抗蚀剂充当掩模以将图案转移到下伏材料。所述光致抗蚀剂足够坚固以在不发生变形的情况下经受住显影步骤且还足够坚固以经受住用于将掩模图案转移到下伏材料的蚀刻。然而，随着特征大小减小，光致抗蚀剂掩模特征的宽度也减小，但通常这些掩模特征的高度不发生对应减小。由于这些掩模特征的高纵横比，因此可难以在显影及图案转移步骤期间维持这些细掩模特征的结构整体性。因此，随着这些特征的大小继续减小，使用足够坚固的光致抗蚀剂材料可限制光刻印刷特征的能力。
因此，继续需要用于图案化特征的高分辨率方法。
附图说明
图1是根据本发明的一些实施例，具有上覆掩蔽层的衬底的示意性横截面侧视图。
图2是根据本发明的一些实施例图1的结构在进行图案化可选择性地界定的层之后的示意性横截面侧视图。
图3是根据本发明的实施例图2的结构在进行蚀刻穿透硬掩模层之后的示意性横截面侧视图。
图4是根据本发明的一些实施例图3的结构在进行移除可选择性地界定的层之后的示意性横截面侧视图。
图5是根据本发明的一些实施例图4的结构在加宽硬掩模层中的特征之间的间隔之后的示意性横截面侧视图。
图6是根据本发明的一些实施例图5的结构在沉积一层自组织材料的溶液之后的示意性横截面侧视图。
图7是根据本发明的一些实施例图6的结构在自组织材料的自组装之后的示意性横截面侧视图。
图8是根据本发明的一些实施例显示由自组织材料的自组装产生的材料区域布置的图7的结构的示意性俯视图。
图9是根据本发明的一些实施例图7的结构在进行选择性的移除自组织材料的一些区域以形成心轴之后的示意性横截面侧视图。
图10是根据本发明的一些实施例图9的结构在进行沉积一层间隔件材料之后的示意性横截面侧视图。
图11是根据本发明的一些实施例图10的结构在进行间隔件蚀刻之后的示意性横截面侧视图。
图12是根据本发明的一些实施例图11的结构在进行移除心轴以留下自立间隔件图案的示意性横截面侧视图。
图13是根据本发明的一些实施例图12的结构在进行转移由独立的间隔件形成的图案之后的示意性横截面侧视图。
图14是根据本发明的一些实施例图12的结构在于间隔件上方沉积平坦化层之后的示意性横截面侧视图。
图15是根据本发明的一些实施例图14的结构在进行图案化平坦化层之后的示意性横截面侧视图。
具体实施方式
可使用嵌段共聚物的自组织能力来形成掩模图案。嵌段共聚物由两种或两种以上化学上不同的嵌段形成。例如，每一嵌段均可由不同的单体形成。所述嵌段是不混溶或热力学不相容的，例如，一个嵌段可以是极性的，而另一嵌段可以是非极性的。由于热力学效应，共聚物将在溶液中自组织以使系统的能量整体地最小化，此通常导致共聚物相对于彼此而移动，因而(例如)相同的嵌段聚集在一起，借此形成含有每一嵌段类型或物质的交替区域。例如，如果共聚物是由极性及非极性嵌段形成，那么所述嵌段将分离，从而非极性嵌段与其它非极性嵌段聚集且极性嵌段与其它极性嵌段聚集。应了解，可将嵌段共聚物描述为自组织材料，因为嵌段可在不主动施加引导特定个别分子运动的外力的情况下移动以形成图案，但也可施加热以增大分子群组整体的移动速率。
除嵌段物质之间的相互作用之外，嵌段共聚物的自组织可受形貌特征影响，例如嵌段共聚物所沉积到的表面上的阶梯。例如，由两个不同嵌段物质形成的共聚物-二嵌段共聚物可形成交替的域或区域，其中的每一者均由大致不同的嵌段物质形成。当在阶梯的壁之间的区域中发生嵌段物质自组织时，阶梯可与嵌段相互作用，从而(例如)使由嵌段形成的交替区域中的每一者形成具有平行于壁定向的特征的有规律图案。另外，可通过用光刻技术修改表面而不是在表面上形成阶梯来导引嵌段共聚物的自组织，如以下书刊中所揭示：斯托卡可斯(Stoykovich)等人的《科学》308，1442(2005)；科姆(Kim)等人的《自然》424，411(2003)；及爱德华兹(Edwards)等人的《先进材料》16，1315(2004)。这些参考资料的每一者的全部揭示内容均以引用的方式并入本文中。
此自组织可用于形成用于在半导体制造过程期间图案化特征的掩模。例如，可移除交替域中的一者，借此留下形成另一区域的材料用作掩模。所述掩模可用于图案化例如下伏半导体衬底中的电装置的特征。形成共聚物掩模的方法揭示于以下申请案中：2006年3月23日提出申请、名称为形貌引导的图案化的，格泰吉桑达胡(GurtejSandhu)的第11/389,581号美国专利申请案(代理人档案号MICRON.342A(Micron Ref.No.：2005-0865))及2006年6月2日提出申请、名称为基于形貌的图案化的格泰吉桑达胡(Gurtej Sandhu)的第11/445,907号美国专利申请案(代理人档案号MICRON.349A(Micron Ref.No.：05-0865))，这两个申请案的每一者的全部揭示内容以引用的方式并入本文中。尽管自组织材料可用于形成相对小的掩模特征，但由于集成电路的持续小型化，需要掩模特征大小的进一步减小。
此外，嵌段共聚物的长度可以对由那些嵌段共聚物的嵌段形成的域的大小有固有限制。举例来说，共聚物可经选取而具有促进自组装成所需域图案的长度，而较短共聚物并不可根据需要来进行自组装。
本发明的实施例允许形成比那些可单独由嵌段聚合物形成的特征小的特征。在本发明的实施例中，允许组织由不同化学物质形成的自组织材料以形成由相同化学物质组成的域。选择性地移除那些域中的一些域以形成心轴或临时占位件。然后，使用由自组织材料形成的心轴执行间距倍增过程。从心轴获得具有小于所述心轴的间距的间距的特征。在一些实施例中，在心轴的侧壁上形成间隔件且选择性地移除心轴。间隔件或从间隔件获得的其它掩模特征用作掩模的一部分以在(例如制造集成电路期间)图案化下伏材料。
本发明的实施例可不借助使用较新的相对复杂且昂贵的平版印刷技术形成掩模特征且可减少光致抗蚀剂的坚固性的负担。举例来说，代替在掩模中使用相对软且专门结构的光致抗蚀剂，可使用间隔件或从间隔件获得的掩模特征作为掩模。使用间隔件允许选择各种材料用于间隔件，且可针对坚固性及与流程中所使用的下伏材料的相容性来选择材料。此外，由于不使用共聚物材料用作用于图案化下伏层的掩模，因此可不考虑(例如)其坚固性及供形成掩蔽层的适合性来选择共聚物材料。而是，可基于共聚物材料的自组织行为及供在心轴中使用的适合性来选择所述共聚物材料，借此增加过程的宽泛性。此外，材料(嵌段共聚物)的自组织行为允许可靠地形成极小的特征，借此促进形成具有极小特征大小的掩模。举例来说，可形成具有在以下范围中的临界尺寸的特征：约1nm到约100nm、约3nm到约50nm或约5nm到约30nm。
现在将参照图，其中各图中相同的编号指代相同的零件。应了解，所述图未必按比例绘制。
在根据本发明的一些实施例的方法的第一阶段中，由自组织材料(例如，嵌段共聚物)形成多个心轴。图1到8图解说明用于使用导引件或阶梯特征导引自组装来将自组织材料自组装成所需图案的方法。在其它实施例中，将了解，可通过此项技术中已知的任何方法来引导自组织材料的自组装。
参照图1，图中图解说明经部分形成的集成电路100的横截面侧视图。可在衬底110上提供掩蔽层120、130以形成用于共聚物自组装的导引件。基于对所述层与将要使用的嵌段共聚物材料的相互作用以及对本文中论述的各种图案形成及图案转移步骤的化学工艺及过程条件的考虑选取用于上覆衬底110的层120、130的材料。举例来说，由于将上部层中的图案转移到下部层，因此下部掩蔽层130经选取以使得其相对于其它经暴露材料中的至少一些材料可选择性地被蚀刻。将了解，当一种材料的蚀刻速率比周围材料的蚀刻速率至少大约2到3倍或至少大约10倍或至少大约20倍或至少大约50倍时，那么认为选择性地或优先地蚀刻所述材料。
应了解，图案所转移到的“衬底”可包含单个材料层、多个不同材料层、其中具有不同材料或不同结构的区域的层等。这些材料可包含半导体、绝缘体、导体或其组合。例如，所述衬底可包括经掺杂多晶硅、单晶电装置有源区域、硅化物或金属层，例如钨、铝或铜层或其组合。在一些实施例中，下文论述的掩模特征可直接对应于传导性特征(例如，互连件)在衬底中的期望布置。在其它实施例中，所述衬底可以是绝缘体，且掩模特征的位置可对应于传导性特征之间的绝缘体的期望位置，例如，在大马士革金属化(damascene metallization)中。掩模特征可用作硬掩模以直接蚀刻衬底，或可用于将图案转移到另一下伏层(例如，碳层(例如，透明碳层))，然后所述下伏层用于将所述图案转移到一个或一个以上下伏层(例如，衬底)。
继续参照图1，可选择性地界定的层120上覆硬掩模或蚀刻停止层130，所述掩模或蚀刻停止层又上覆衬底110。所述可选择性地界定的层120可以是光可界定的(例如，由光致抗蚀剂形成)，包含此项技术中已知的任何光致抗蚀剂。举例来说，光致抗蚀剂可以是与极远端紫外系统(例如，13.4nm波长系统)、157nm、193nm、248nm或365nm波长系统或193nm波长浸没系统相容的任何光致抗蚀剂。光致抗蚀剂材料的实例包含对氟化氩(ArF)敏感的光致抗蚀剂(即适合与ArF光源一起使用的光致抗蚀剂)，和对氟化氪(KrF)敏感的光致抗蚀剂(即适合与KrF光源一起使用的光致抗蚀剂)。ArF光致抗蚀剂与利用相对短波长光(例如，193nm)之光刻系统一起使用。KrF光致抗蚀剂与较长波长光刻系统(例如，248nm系统)一起使用。另外，虽然在本发明的实施例中使用自组织材料及间距倍增可规避用昂贵、相对新颖的直接形成技术(例如，极远端紫外系统(其中包含13.4nm波长系统)，或电子束平版印刷系统)界定极小特征的需要，但如果需要也可使用此类系统。另外，无掩模平版印刷或无掩模光刻可用以界定可选择性地界定的层120。在其它实施例中，层120及任何后续抗蚀剂层可由可通过纳米压印平版印刷图案化的抗蚀剂形成，例如通过使用模型或机械力来在所述抗蚀剂中形成图案。
用于硬掩模层130的材料可包括不是聚合物的无机材料。实例性材料包含氧化硅(SiO2)、氮化硅、硅或介电抗反射涂层(DARC)，例如富含硅的氧氮化硅。在所图解说明的实施例中，硬掩模层130包括氮化硅。硬掩模层130的材料经选择以与随后沉积的自组织材料相互作用以引导自组织材料自组装成所需图案。
参照图2，光可界定的层120暴露于透过光罩的辐射，且然后经显影以留下包括由光可界定材料形成的特征122的图案。将了解，所得特征122(例如，线)的间距等于线122的宽度与相邻间隔124的宽度的和。在一些实施例中，特征122的间距可以是(例如)约400nm或更小、约300nm或更小、约200nm或更小或约100或更小。在实例性实施例中，特征122可具有约140nm的临界尺寸及约280nm的间距。
参照图3，将光可界定层120中的图案转移到硬掩模层130，借此在硬掩模层130中形成硬掩模特征132。所述图案转移可使用各向异性蚀刻来实现，例如使用碳氟化合物等离子体的蚀刻，但在硬掩模层130足够薄的情况下，湿法(各向同性)蚀刻也可以是适合的。实例性碳氟化合物等离子体化学蚀刻工艺包含CFH3、CF2H2、CF3H及CF4/HBr。参照图4，也可移除形成光可界定层120的抗蚀剂，例如，通过等离子体灰化。
参照图5，修整硬掩模特征132(图4)以形成用于共聚物自组装的导引件134。可使用湿法蚀刻或干法蚀刻来修整硬掩模特征132，所述蚀刻相对于其它暴露材料选择性地蚀刻硬掩模材料。可使用(例如)SO2/O2/Ar等离子体来执行修整蚀刻。所述修整允许形成具有比可使用常规光刻容易地形成的特征小的临界尺寸的特征。举例来说，可修整具有约140nm的临界尺寸及约280nm的间距的硬掩模特征132以形成具有约35nm的临界尺寸及约280nm的相同间距的共聚物自组装导引件134。在其它实施例中，除了或代替硬掩模特征132，可修整光致抗蚀剂特征122(图2)，借此允许在不需要修整硬掩模特征132的情形下形成具有所需大小的导引件134。
接下来，在衬底110上施加自组织材料(例如，嵌段共聚物)且使其自组装以在其上形成掩模图案。形成自组织的嵌段共聚物图案的方法揭示于以下文献中：2004年9月第三期的嵌段，IEE纳米技术学报，第3卷(Block，IEE Transactions inNanotechnology，Vol.3，No.3，September 2004)及第11/389,581及11/445,907号美国专利申请案，其中的每一者的全部揭示内容以引用的方式并入本文中。
参照图6，在导引件134之间及其上方沉积嵌段共聚物材料膜160。共聚物包括聚合物材料嵌段，其可以是相对于彼此选择性地被蚀刻且其可以所需及可预测的方式自组织，例如嵌段不混溶且将在适当条件下分离以形成主要含有单一嵌段物质的域。在所图解说明的实例性实施例中，共聚物是二嵌段共聚物，其包括(例如)聚苯乙烯(PS)及聚甲基丙烯酸甲酯(PMMA)。所述二嵌段共聚物可被溶解在溶剂(例如，甲苯)中来提供。应了解，每一二嵌段共聚物的总大小及组成嵌段与单体的比可经选取以促进自组织且形成具有所需尺寸的经组织嵌段域。举例来说，应了解，嵌段共聚物具有固有的聚合物长度标度，即膜中共聚物的平均端到端长度，其中包含任何卷绕或纽结，所述长度控制嵌段域的大小。可使用具有较长共聚物的共聚物溶液形成较大的域且可使用具有较短的共聚物的共聚物溶液形成较小的域。在一些实施例中，共聚物经选择以提供在间隔件175之间提供一致间隔的心轴(图12)。在其它实施例中，嵌段共聚物经选择以促进自组装成所需图案，(例如)通过湿法蚀刻或干法蚀刻修整心轴以在心轴之间提供所需间隔。可通过各种方法来沉积嵌段共聚物，包含(例如)旋转涂布、旋转浇铸、刷涂或气相沉积。
可基于将由共聚物形成的所需图案来选取共聚物膜160的厚度。应了解，当达到与聚合物长度标度及其中设置聚合物的环境相关的特定厚度(例如，导引件134之间的距离及导引件134的高度)时，共聚物将通常定向以形成交替的大致薄片状的域，所述域形成平行线，在俯视图(图8)中可观察到。此类薄片可用于图案化(例如)互连件，或者可限制所述薄片的衡向延伸以形成隔离的特征，例如晶体管栅极。在一些条件下，当达到与聚合物长度标度及其中设置聚合物的环境相关的膜160厚度时，共聚物可定向以形成垂直延伸的柱(例如，圆柱体)或球体。
为形成薄片，共聚物膜厚度可约小于形成所述膜的共聚物的长度标度。举例来说，在共聚物长度标度是约35nm的情形下，膜厚度约为35nm或更小、约30nm或更小或约25nm或更小。
应了解，膜160厚度可以大于、等于或小于导引件134的高度。如下文进一步所图解说明及论述，可使用大于导引件134的高度的厚度来提供共聚物蓄存器。在其它实施例中，可使用等于或小于导引件134的高度的厚度来在导引件134之间形成隔离的共聚物岛，借此防止共聚物在所述岛之间交叉扩散。
虽然本发明不受理论限制，但应了解，出于在类似于材料的相分离的过程中的热力学考虑，应理解不同的嵌段物质可自聚集。自组织是由导引件134来导引，此因界面相互作用而促使嵌段共聚物的构成嵌段沿导引件134的长度自我定向。应了解，自组织可导致共聚物物质的更有效堆积。因此，在一些情况下，如果共聚物膜160延伸过大的范围时，可用于自组织的共聚物可被耗尽，从而导致所述范围中间的区域经形成而没有经组织的共聚物或具有较差组织的共聚物。因此，在一些实施例中，共聚物膜160应足够厚以延伸到高于导引件134从而提供用于发生于导引件134之间的自组织的共聚物蓄存器。另外，导引件134之间的距离可经选取以足够小从而最小化可发生在大范围中的耗尽效应。
参照图7，允许共聚物膜160中的嵌段共聚物自组织。可通过对已部分制成的集成电路100进行退火来促进及加速自组织。所述退火的温度可经选取以足够低从而防止对嵌段共聚物或已部分制成的集成电路100产生负面影响。在一些实施例中，可以小于约250℃、小于约200℃或约180℃的温度执行退火。退火还可用于导致共聚物的交联，借此稳定共聚物以用于随后蚀刻及图案转移步骤。
图7显示退火之后所得的薄片的图案。一种嵌段物质(例如，PS)的域162及另一嵌段物质(例如，PMMA)的域164在导引件134之间交替。应了解，嵌段域的大小是由形成其的嵌段物质的大小所决定。
参照图8，图中显示图7的已部分制成的集成电路的俯视图。可看到PS域162与PMMA域164交替。域162及164两者沿导引件134的长度延伸。
参照图9，选择性地移除域164，从而留下域162及导引件134(未显示)，所述域162可用作间距倍增的心轴。应了解，可在单个步骤中使用单个化学蚀刻工艺或可使用具有不同化学蚀刻工艺的多次蚀刻移除域164。举例来说，在域164是由PMMA形成且域162是由PS形成的情形下，域164可通过(例如)使用醋酸作为蚀刻剂执行选择性湿法蚀刻来移除。在其它实施例中，当所述域中的一者可以比另一者快的速率被蚀刻时，干法蚀刻或各向异性蚀刻可是适当的。应了解，所得特征的尺寸可不同，这取决于所使用的共聚物的大小及过程条件。在一些实施例中，所得图案可包括具有约50nm到约2nm、约35nm或更小到约3nm的临界尺寸的PS域，其中间距为约100nm到约4nm或约70nm到约6nm。应了解，在其它实施例中，可替代地移除域162及/或导引件134，借此留下域164，可具有或不具有导引件134。
接下来，参照图10，将间隔件材料层170保形地覆盖沉积在所暴露的表面上方，包含衬底110。所述间隔件材料可以是可充当用于将图案转移到下伏材料的掩模的任何材料。所述间隔件材料：1)可经沉积具有良好阶梯覆盖；2)可以与心轴162相容的温度沉积；及3)可相对于心轴162及导引件134(如果存在)以及下伏衬底110选择性地被蚀刻。无限制地，所述间隔件材料可以是无机材料(例如，含硅材料)或有机材料(例如，聚合物)。无限制地，所述含硅间隔件材料可以是硅、氧化硅及氮化硅。在所图解说明的实施例中，所述间隔件材料是氧化硅。
用于间隔件材料沉积的方法包含原子层沉积，例如使用具有硅前驱物的自限制沉积且随后暴露于氧或氮前驱物以分别形成氧化物及氮化物。可在相对低的温度下(例如，在约200℃下或在约100℃下)执行ALD，从而可放置对下伏热敏感材料造成热损害。举例来说，可使用ALD来预防对形成嵌段域162的聚合物材料的损害。在其它实施例中，使用化学气相沉积来沉积间隔件材料。
层170的厚度是基于间隔件175的所需宽度(图12)来确定。举例来说，在一些实施例中，将层170沉积到约10到80nm或约20到50nm的厚度以形成大致类似宽度的间隔件。阶梯覆盖约为80％或更大及/或约为90％或更大。
参照图11，氧化硅间隔件层170然后经受各向异性蚀刻以从经部分形成的集成电路100的水平表面180移除间隔件材料。此类蚀刻(也称作间隔件蚀刻)可使用碳氟化合物等离子体来执行，例如含等离子体的CF4、CHF3及/或NF3。
参照图12，移除嵌段域162及任何剩余导引件134以留下独立的间隔件175。可使用相对于间隔件175选择性地移除嵌段域162及导引件134的湿法蚀刻或干法蚀刻来移除那些特征。所述蚀刻还可相对于下伏衬底110选择性地移除嵌段域162及导引件134。取决于形成嵌段域162及导引件134的材料，可应用相同或不同的化学蚀刻工艺。无限制地，化学蚀刻工艺包含用以移除PS嵌段域162的基于O2的碳剥离蚀刻及用以移除氮化硅导引件134的基域磷酸的湿法蚀刻。
因此，形成间距倍增掩模特征。在所图解说明的实施例中，间隔件175的间距大致为由嵌段共聚物形成的嵌段域162(图9)的间距的一半。举例来说，在嵌段域162具有约200nm的间距的情形下，可形成具有约100nm或更小的间距的间隔件175且在嵌段域162具有约60nm或更小的间距的情形下，可形成具有约30nm或更小的间距的间隔件175。应了解，因为间隔件175形成在嵌段域162的侧壁上，所以间隔件175通常跟随嵌段域162的轮廓且因此，通常形成闭环。间隔件175形成第一图案177。应了解，在一些实施例中，可通过使用间隔件175作为用以形成其它间隔件或掩模特征的心轴来实现较高数量级的间距倍增。
参照图13，将图案177转移到衬底110。可使用适于相对于间隔件175选择性地蚀刻衬底110的一种或多种材料的化学蚀刻工艺来实现图案转移。所属领域的技术人员可易于确定用于衬底材料的适合化学蚀刻工艺。应了解，在衬底110包括不同材料的层的情形下，如果单个化学工艺不足以蚀刻所有所述不同材料，那么可使用一系列不同的化学工艺(例如，干法蚀刻化学工艺)来连续地蚀刻穿透这些不同层。还应了解，取决于所使用的一个或多个化学工艺，可蚀刻间隔件175。在所图解说明的实施例中，间隔件175足够高以在不完全磨损衬底110的前提下完成对其的蚀刻。
参照图14，剥离上覆衬底110的掩模(包含域162及导引件134)，从而留下经图案化的衬底110。在图案转移之后，已部分制成的集成电路100经受后续处理步骤(包含形成辅助电装置及电互连件)以形成完成的集成电路，例如，存储器芯片。
将了解，可对所图解说明的实施例做出各种修改。例如，虽然为便于图解说明及论述已在二嵌段共聚物的背景下作出论述，但共聚物可由两种或两种以上嵌段物质形成。此外，虽然所图解说明的实施例的嵌段物质各自由不同单体形成，但嵌段物质可共享单体。例如，嵌段物质可由不同组单体形成，其中的某一些是相同的，或者可由相同单体形成，但在每一嵌段中呈不同的分布。所述不同组单体形成具有不同特性的嵌段，从而可促进共聚物的自组装。
在一些实施例中，可在嵌段域162及164和导引件134的上方沉积自组织材料的补充层180以垂直延伸由那些嵌段域及导引件134界定的图案。形成补充层180的自组织材料可以是共聚物，例如嵌段共聚物。形成补充层180的材料经选取以与嵌段域162及164和导引件134相互作用以使得域162、164和导引件134能够引导自组织材料的组织。举例来说，在嵌段域162及164和导引件134包含极性及非极性嵌段物质时，层180也可具有极性及非极性嵌段物质。在一些实施例中，形成层180的补充嵌段共聚物与膜160的嵌段共聚物相同。用于垂直延伸由自组织材料形成的图案的方法揭示于2006年6月2日提出申请的、名称为基于形貌的图案化的格泰吉桑达胡(Gurtej Sandhu)的第11/445,907号美国专利申请案(代理人档案号MICRON.349A)中，所述申请案的全部揭示内容以引用的方式并入本文中。
应了解，在将掩模图案177转移到衬底110之前或之后，可用额外的掩模图案上覆掩模图案177(图11)。举例来说，可在间隔件175之间及其上方沉积平坦化材料且可图案化所述平坦化材料以形成额外的图案。可将与掩模图案177形成组合图案的额外图案转移到下伏衬底110。参照图15，平坦化材料可以是光致抗蚀剂，例如负性或正性光致抗蚀剂。参照图16，可通过曝光到辐射来图案化所述光致抗蚀剂以形成额外的图案。在掩模图案177的特征间隔极接近(例如，具有约40nm或更小的间距)的实施例中，可使用负性光致抗蚀剂。已发现，在具有这样小的间距的间隔件之间可难于移除正性光致抗蚀剂，是因为难于使光致抗蚀剂完全暴露于光造成。另一方面，增加光强度可不期望地致使光致抗蚀剂聚合，是由于一些透明间隔件材料(例如，氧化硅)引起的光放大造成。负性光致抗蚀剂不需要暴露于光而进行移除，借此促进移除间隔件之间的光致抗蚀剂及与掩模图案177形成对齐的图案。
在一些实施例中，可省略上覆衬底的硬掩模层130。举例来说，光可界定材料可以由与用于共聚物自组织的温度及其它条件相容的材料形成或替代，且/或可将间隔件175用作蚀刻衬底110的掩模(其中，可使用对衬底110具有足够选择性的蚀刻剂)。
在一些其它实施例中，可在衬底110上方提供额外的掩蔽层级。举例来说，可在间隔件175与衬底110之间提供额外的硬掩模层。可在将图案177转移到衬底110之前将其转移到一个或一个以上额外的硬掩模层。所述额外的硬掩模层可经选择以提供对用于蚀刻衬底的蚀刻剂较高的抵抗性。举例来说，可在将图案177转移到衬底110之前将其转移到无定形碳层。已发现无定形碳适合作为用于蚀刻各种含硅材料的硬掩模。
另外，虽然通过一个掩模层的“处理”可囊括蚀刻下伏层，但通过多个掩模层的处理可涉及使下伏在掩模层下的层经受任何半导体制造工艺。举例来说，处理可涉及经由掩模层而进入到下伏层上的离子植入、扩散掺杂、沉积、氧化(特别是在聚合物掩模下使用硬掩模的情况下)、氮化等。另外，掩模层可用作化学机械抛光(CMP)的停止层或阻挡层，或者可对所述层中的任一者执行CMP以允许对下伏层进行平坦化及蚀刻两者，如在2005年8月31日提出申请的美国专利申请案第11/216,477号中所论述，所述专利申请案的全部揭示内容以引用的方式并入本文中。
另外，尽管所图解说明的实施例可应用于制造集成电路，但本发明的实施例可应用于其中需要形成具有极小特征的图案的各种其它应用中。举例来说，本发明实施例可用于形成光栅、磁盘驱动器、存储媒体或用于其它平版印刷技术的模板或掩模，包含X射线或压印平版印刷。举例来说，可通过图案化以下衬底来形成相移光罩，所述衬底具有一膜堆叠，所述膜堆叠具有相移材料涂层。
因此，从本文中的说明应了解，本发明包含各种实施例。举例来说，根据本发明的一些实施例，提供图案化半导体衬底的方法。所述方法包括提供包括嵌段共聚物的层。选择性地移除嵌段共聚物中的一个嵌段以留下横向分开的心轴所述心轴包括所述嵌段共聚物中的另一个嵌段。将间隔件材料覆盖沉积在心轴上。蚀刻间隔件材料以在心轴的侧壁上形成间隔件。将由间隔件界定的图案转移到衬底。
根据本发明的其它实施例，提供形成用于图案化衬底的掩模的方法。所述方法包括提供自组织材料层。自组织材料的相同化学物质聚集以形成具有由化学物质界定的域的重复图案。优先地移除化学物质中的一者以形成间隔开的心轴。在心轴的侧壁上形成间隔件。
根据本发明的又一实施例，提供制造集成电路的方法。所述方法包括将嵌段共聚物层暴露于湿法蚀刻剂以在嵌段共聚物层中界定独立的有规律间隔的间隔开占位件。在占位件的侧壁上形成间隔件。将从间隔件获得的图案转移到下伏衬底。
除以上揭示内容外，所属领域的技术人员还将了解，可在不背离本发明的范围的前提下对上文所描述的方法及结构作出各种省略、添加及修改。打算将所有此类修改及改变均归属在以上权利要求书所界定的本发明的范围内。

Claims (35)

1、一种图案化半导体衬底的方法，其包括：
提供包括嵌段共聚物的层；
选择性地移除所述嵌段共聚物中的一个嵌段以留下包括所述嵌段共聚物的另一嵌段的横向分开的心轴；
在所述心轴上覆盖沉积间隔件材料；
蚀刻所述间隔件材料以在所述心轴的侧壁上形成间隔件；及
将由所述间隔件界定的图案转移到所述衬底。
2、如权利要求1所述的方法，其中提供由嵌段共聚物形成的所述层包括：
在所述衬底上方沉积嵌段共聚物溶液；及
分离构成所述嵌段共聚物的嵌段以在所述衬底上方形成由所述共聚物的嵌段界定的重复图案。
3、如权利要求2所述的方法，其中提供由嵌段共聚物形成的所述层进一步包括在所述衬底上方提供横向间隔开的共聚物自组装导引件，其中沉积所述嵌段共聚物溶液包括在所述共聚物分离导引件之间沉积所述嵌段共聚物溶液。
4、如权利要求3所述的方法，其中所述导引件是由吸引或排斥形成所述嵌段共聚物的嵌段的材料形成。
5、如权利要求3所述的方法，其中所述导引件是由选自由以下构成的群组的材料形成：氧化硅、硅及介电抗反射涂层。
6、如权利要求1所述的方法，其进一步包括在将由所述间隔件界定的所述图案转移到所述衬底之前移除所述心轴。
7、如权利要求6所述的方法，其进一步包括在将由所述间隔件界定的所述图案转移到所述衬底之前将由所述间隔件界定的所述图案转移到下伏硬掩模层。
8、如权利要求7所述的方法，其中所述硬掩模层包括无定形碳。
9、如权利要求1所述的方法，其进一步包括：
在所述间隔件上方沉积可选择性地界定的材料；及
在所述可选择性地界定的材料中界定另一图案，
其中将由所述间隔件界定的所述图案转移到所述衬底包括将由所述图案及所述另一图案形成的组合图案转移到所述衬底。
10、如权利要求9所述的方法，其中所述可选择性地界定的层是沉积在所述间隔件上及其之间。
11、如权利要求10所述的方法，其中所述可选择性地界定的层是光致抗蚀剂。
12、如权利要求11所述的方法，其中所述光致抗蚀剂是负性光致抗蚀剂。
13、如权利要求9所述的方法，其进一步包括在将由所述图案及所述另一图案形成的所述组合图案转移到所述衬底之前将所述组合图案转移到下伏硬掩模层。
14、如权利要求9所述的方法，其中将所述组合图案转移到所述衬底是将由所述间隔件界定的所述图案转移到已部分制成的集成电路的阵列区域及将所述另一图案转移到所述已部分制成的集成电路的外围区域。
15、如权利要求1所述的方法，其中将由所述间隔件界定的所述图案转移到所述衬底在所述衬底中界定互连件。
16、一种形成用于图案化衬底的掩模的方法，其包括：
提供自组织材料层；
聚集所述自组织材料的相同化学物质以形成具有由所述化学物质界定的域的重复图案；
优先地移除所述化学物质中的一者以形成间隔开的心轴；及
在所述心轴的侧壁上形成间隔件。
17、如权利要求16所述的方法，其中所述自组织材料包括嵌段共聚物。
18、如权利要求17所述的方法，其中所述嵌段共聚物是二嵌段共聚物。
19、如权利要求18所述的方法，其中所述二嵌段共聚物包括聚苯乙烯。
20、如权利要求19所述的方法，其中所述二嵌段共聚物进一步包括聚甲基丙烯酸甲酯。
21、如权利要求16所述的方法，其进一步包括延伸由所述化学物质界定的所述重复图案的高度。
22、如权利要求21所述的方法，其中延伸由所述化学物质界定的所述重复图案的所述高度包括：
在由所述化学物质界定的所述重复图案上方沉积额外的自组织材料；及
使所述额外自组织材料的相同化学部分与由所述化学物质界定的所述域对准。
23、如权利要求22所述的方法，其中所述自组织材料及所述额外自组织材料为嵌段共聚物。
24、如权利要求23所述的方法，其中所述自组织材料及所述额外自组织材料为相同的嵌段共聚物。
25、如权利要求22所述的方法，其中优先地移除所述化学物质中的一者包括蚀刻所述额外自组织材料的相同化学部分及蚀刻所述化学物质中的一者。
26、一种制造集成电路的方法，所述方法包括：
使嵌段共聚物层暴露于湿法蚀刻剂以在所述嵌段共聚物层中界定独立的有规律间隔的间隔开的占位件；
在所述占位件的侧壁上形成间隔件；及
将从所述间隔件获得的图案转移到下伏衬底。
27、如权利要求26所述的方法，其中所述湿法蚀刻剂包括醋酸。
28、如权利要求27所述的方法，其中所述嵌段共聚物包括聚苯乙烯嵌段及聚甲基丙烯酸甲酯嵌段。
29、如权利要求26所述的方法，其中所述占位件具有约100nm或更小的间距。
30、如权利要求29所述的方法，其中所述占位件具有约50nm或更小的间距。
31、如权利要求26所述的方法，其中所述独立的间隔开的占位件包括垂直薄片。
32、如权利要求26所述的方法，其中所述独立的间隔开的占位件包括垂直延伸的隔离柱。
33、如权利要求26所述的方法，其中所述转移所述图案包括在已部分制成的集成电路的阵列区域中界定有规律间隔的特征。
34、如权利要求26所述的方法，其中形成间隔件包括：
在所述占位件上方覆盖沉积间隔件材料层；及
各向异性地蚀刻所述间隔件材料层。
35、如权利要求26所述的方法，其进一步包括在使所述嵌段共聚物层暴露于所述湿法蚀刻剂之前：
在所述衬底上方沉积嵌段共聚物溶液；及
对所述嵌段共聚物溶液进行退火以致使所述嵌段共聚物自组装成有规律间隔的嵌段域。
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