CN101706731B - Method and system for loading program - Google Patents
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- CN101706731B CN101706731B CN 200910250402 CN200910250402A CN101706731B CN 101706731 B CN101706731 B CN 101706731B CN 200910250402 CN200910250402 CN 200910250402 CN 200910250402 A CN200910250402 A CN 200910250402A CN 101706731 B CN101706731 B CN 101706731B
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Abstract
The invention discloses a method and a system for loading a program, which are used for loading a program to be loaded into an EEPROM. The method comprises the following steps: loading an EEPROM program loading control function logic code into a programmable logic device; executing an EEPROM program loading operation command after the EEPROM program loading control function logic code in the programmable logic device runs, and loading the program to be loaded into the EEPROM when the logic code in the programmable logic device realizes the EEPROM program loading control function. With the loading method and the loading system, the high-efficiency on-line loading of the EEPROM program can be realized without extra hardware consumption.
Description
Technical field
The present invention relates to EEPROM (Electrically Erasable Programmable Read-OnlyMemory, Electrically Erasable Read Only Memory) chip technology field, relate in particular to a kind of loading method and system of program.
Background technology
Program loaded into the method for EEPROM mainly contain two large classes: a kind of is that eeprom chip is being independent of loading procedure on the external load equipment of application system first, and then chip is moved on to the load mode that uses in the application system; Another kind is on-line loaded, at present published have by the boundary scan controller in the system, utilize the controllable characteristics of device I/O pin in the boundary scan testing process, realize the loading method of the online programming of EEPROM device that boundary scanning device is connected.
First method need to be fixed on eeprom chip in every way on the special external load equipment and load, and the eeprom chip that will load again program is installed in the application system.The method needs extra loading equipemtn, the most frequently used fixed form be with chip lock on socket, shape, size, the chip that number of pins is different all need specific socket to match; And eeprom chip needs externally between the loading equipemtn and application system repeatedly switching position when utilizing the method to realize again loading, thus be only suitable for the fixing EEPROM device of socket mode, and be not suitable for the EEPROM device of surface mount mode.The method is early stage a kind of common practice, but greatly increase for present device density, expend the situation that the socket mode installing device of plate face area is abandoned gradually, utilize external load equipment to carry out method that the EEPROM program loads and no longer be suitable for new technology and use.
Second method is to utilize Boundary-scan test technology, the controllable characteristics of device I/O pin in the boundary scan testing process, by the boundary scan controller in the system, all scanning elements to boundary scanning device such as are shifted, refresh at the operation, change its I/O (Input/Output, I/O) pin state is realized the online programming loading to the EEPROM device that is connected with boundary scanning device.Although this loading method can be implemented in sequence of threads and load, there is the lower problem of loading efficiency in all scanning elements that it needs the scanning boundary scanning device.At present existing certain methods is used for improving boundary scan efficient, as reducing the scan shift total degree by the method that reduces the boundary scan cell sum, strengthen data-bus width, improving scan clock frequency etc., but these methods all are subject to the hardware specific (special) requirements such as high clock frequency requirement, and the slow-footed objective condition restriction of scan shift mode, be difficult to so that the method for utilizing boundary scanning test method to load the EEPROM program is brought into play good effect in actual applications.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of loading method and system of program, does not need extra hardware consumption, expeditiously on-line loaded EEPROM program.
In order to address the above problem, the invention provides a kind of loading method of program, be used for program to be loaded is loaded into Electrically Erasable Read Only Memory (EEPROM), described method comprises:
EEPROM program Loading Control function logic code is loaded into programmable logic device (PLD);
After the described EEPROM program Loading Control function logic code operation in the described programmable logic device (PLD), carry out EEPROM program load operation order, described logical code in the described programmable logic device (PLD) is realized EEPROM program Loading Control function, and described program to be loaded is loaded into described EEPROM.
Further, described method also comprises:
Described logical code is being loaded after described programmable logic device (PLD), and whether the described loading of verification is successful, if load successfully, then carries out EEPROM program load operation order; Otherwise, end operation, or after getting rid of unusually, re-execute described logical code load operation order.
Further, described method also comprises:
Program to be loaded is being loaded behind EEPROM, and whether the described loading of verification is successful, if load successfully, then described method finishes; Otherwise, after getting rid of unusually, re-execute described EEPROM program load operation order.
Further, the described EEPROM program Loading Control function logic code that loads in the described programmable logic device (PLD) is used for controlling the loading of one or more programs to be loaded.
Further, described method also comprises:
When needs increase EEPROM subregion and/or online upgrading function, by revising the described EEPROM program Loading Control function logic code that loads in the described programmable logic device (PLD), realize the variation of described EEPROM program value-added tax function.
The present invention also provides a kind of loading system of program, is applied to Circuits System, comprises main frame, loaded cable, loading interface, programmable logic device (PLD) and EEPROM, wherein,
Described programmable logic device (PLD) is used for, and loads and operation EEPROM program Loading Control function logic code;
Described main frame is used for, and by described loaded cable and described loading interface described EEPROM program Loading Control function logic code is loaded into described programmable logic device (PLD); And, after the described EEPROM program Loading Control function logic code operation in described programmable logic device (PLD), by described loaded cable, described loading interface and described EEPROM program Loading Control function, program to be loaded is loaded into EEPROM.
Further, described loading interface further comprises: be used for joint test behavior tissue (JTAG) interface that the programmable logic device (PLD) logical code loads, and be used for the EEPROM program loading interface that the EEPROM program loads;
Wherein, described jtag interface comprises model selection, clock input, data input, data output signal line; Described EEPROM program loading interface comprises the loading clock, loads zone bit, loads data/address signal line.
Further, describedly program to be loaded is loaded the information that transmits in the loading procedure of EEPROM comprise data, address information; When the bit wide of described data/address information is wider, sequentially send the mode of the address of different bits by continuous a plurality of clock period, realize the data of any bit wide/address information transmission.
Further, described programmable logic device (PLD) is programmable logic device (PLD) existing in the described Circuits System or that arrange separately.
Further, the described EEPROM program Loading Control function logic code that loads in the described programmable logic device (PLD) is used for controlling the loading of one or more programs to be loaded.
Compared with prior art, the present invention can realize (the In-System Programming to the ISP of one or more EEPROM devices, online programming), changed in the traditional mode of production flow process first chip has been carried out refilling after program loads mode on the circuit board, simple flow for first fixedly the EEPROM device to circuit board, again by the loading interface loading procedure, thus speed production efficient greatly.
In addition, with existing JTAG (the joint test behavior tissue that adopts fully, Joint Test ActionGroup) the interface mode of carrying out on-line loaded EEPROM program by the boundary scan mode is compared, the present invention has introduced programmable logic device (PLD) and has carried out EEPROM program Loading Control, the EEPROM program Loading Control function that major part is originally finished by boarder controller changes by programmable logic device (PLD) to be finished, greatly accelerate loading velocity, and need not extra hardware circuit, simple.Utilize the circuit that needs at present loading EEPROM program that the characteristics of programmable logic device (PLD) are generally arranged; EEPROM program Loading Control function logic code is put into programmable logic device (PLD); being used for controlling the EEPROM program loads; simultaneously; utilize the method can increase easily the expanded functions such as EEPROM subregion, write-protect, program on-line upgrading, improved the dirigibility of design.In process of production, the logical code of programmable logic device (PLD) loads and the program loading of EEPROM is almost finished simultaneously, can simplify working process Effective Raise production efficiency.
Description of drawings
Fig. 1 is the hardware connection diagram of the program charger of the embodiment of the invention;
Fig. 2 is the electrical connection diagram of the Circuits System of a plurality of EEPROM devices to be loaded of having of the embodiment of the invention;
Fig. 3 is the flow chart of steps of the program loading method of the embodiment of the invention.
Embodiment
Core concept of the present invention is: provide a kind of programmable logic device (PLD) of utilizing that program is loaded method into EEPROM, in the logical code of programmable logic device (PLD), comprise EEPROM program Loading Control function logic code, when actuating logic code loading command, EEPROM program Loading Control function logic code is loaded after programmable logic device (PLD), selection need to be loaded into the program file of EEPROM, carry out EEPROM program loading command, EEPROM program to be loaded is loaded into EEPROM.
Based on above-mentioned thought, the loading method of program provided by the invention mainly adopts following technical scheme:
One, in programmable logic device (PLD), load EEPROM program Loading Control function logic code;
Particularly, can in the following manner EEPROM program Loading Control function logic code be loaded into programmable logic device (PLD):
Steps A. design loading tool program and programmable logic device (PLD) logical code;
Step B. links to each other by loading interface main frame with programmable logic device (PLD);
Wherein there are electric connecting relation in programmable logic device (PLD) and EEPROM to be loaded.
Step C. is in main frame operation loading tool program;
Wherein, this program has the functions such as programmable logic device (PLD) logical code load operation order, EEPROM program load operation order.
Step D. need to select the logical code file of loading, carry out programmable logic device (PLD) logical code loading command, produce the JTAG sequential, logical code is loaded into programmable logic device (PLD), wherein, described logical code comprises EEPROM program Loading Control function logic code;
Two, after the EEPROM program Loading Control function logic code operation in the programmable logic device (PLD), carry out EEPROM program load operation order, the logical code in the programmable logic device (PLD) is realized EEPROM program Loading Control function, and program to be loaded is loaded into EEPROM.Detailed process comprises the steps:
Step e. selection need to be loaded into the program file of EEPROM, carry out EEPROM program loading command, produce the EEPROM program and load sequential, needs are loaded the loading tool software of program by moving on the main frame into EEPROM, loaded cable, loading interface, and the EEPROM program Loading Control function of programmable logic device (PLD) load EEPROM.
Preferably, can after step D and E, increase verifying function, in order to judge whether loading is successful.Then continue to carry out next step or end operation such as success, otherwise check whether electrical connection unusual, whether the implementing procedure operation unusual etc., get rid of and again carry out previous step until load and verification succeeds after unusual.
Preferably, in loading tool software, can add the functions such as cable connectivity detection, chip type detection.
Preferably, for the situation that a plurality of EEPROM devices need to load, the device that needs are loaded all is connected to programmable logic device (PLD), revises EEPROM program Loading Control partial logic code, loads successively in the same way.
In addition, when described program to be loaded changes, can directly again load, and need not to revise the described EEPROM program Loading Control function logic code that loads in the described programmable logic device (PLD).When needs increase other function as to functions such as EEPROM subregion, online upgradings the time, can by revising the described EEPROM program Loading Control function logic code that loads in the described programmable logic device (PLD), realize the flexible variation of EEPROM program value-added tax function.
Below in conjunction with the accompanying drawings and the specific embodiments the enforcement of technical solution of the present invention is further described.
As shown in Figure 1, the program charger that provides of the embodiment of the invention comprises:
EEPROM 105 to be loaded fixes or is welded on the system circuit board;
Programmable logic device (PLD) 104, be used for loading EEPROM program Loading Control function logic code, such as the existing programmable logic device (PLD) of system, the existing programmable logic device (PLD) of utilisation system, need not to increase separately device, as do not have, need to add a programmable logic device (PLD), this programmable logic device (PLD) has electric connecting relation with the EEPROM that is loaded;
Loading interface 103, being used for logical code loading and EEPROM program loads, loading interface comprises the jtag interface function that loads for the programmable logic device (PLD) logical code and is used for the interface function that the EEPROM program loads, and loading interface and programmable logic device (PLD) have electric connecting relation;
Loaded cable 102 is used for main frame is connected with described loading interface, and finishes the level conversion function;
Wherein, programmable logic device (PLD) 104 has electric connecting relation with EEPROM105 to be loaded; Loading interface 103 has electric connecting relation with programmable logic device (PLD) 104; Main frame 101 provides loaded cable 102 to be connected with loading interface 103.
Utilize the present invention to carry out program when loading, only need to the loading interface on the circuit board at main frame and the EEPROM place that needs loading procedure be connected by a loaded cable on the hardware, can realize the program loading of one or more EEPROM.
Be described in detail below with reference to the implementation of accompanying drawing to present embodiment, more clearly to understand reason, method, the feature and advantage of implementing.
As shown in Figure 1, program charger of the present invention has following features on hardware is realized:
Loaded cable 102 is used for main frame 101 and loading interface 103 are coupled together, because both signal levels are different, so need to comprise corresponding level shifting circuit in the loaded cable.Loaded cable one end is 25 needle sockets of coupled computer parallel communication interface, the other end is optional socket as required, only need cooperate with the loading socket on the circuit board to get final product, the pin count of socket need to satisfy for the jtag interface of programmable logic device (PLD) logical code loading and the requirement of EEPROM program loading interface.
Programmable logic device (PLD) 104 can directly be utilized the existing programmable logic device (PLD) of Circuits System during design circuit, need not independent a slice and finishes EEPROM program Loading Control function.Usually Circuits System all comprises programmable logic device (PLD), CPLD (CPLD such as the functions such as initially control that are used for powering on, Complex Programmable Logic Device), only needing to reserve EEPROM program Loading Control resource partly when the chip type selecting gets final product.The programmable logic device (PLD) logical code need to comprise EEPROM program Loading Control function, and after programmable logic device (PLD) 104 was loaded, this part function can come into force, and can carry out the program Loading Control to EEPROM.
Fig. 2 is the electrical connection diagram with upper part of devices of Circuits System (circuit board) of a plurality of (take 2 as example) EEPROM device to be loaded, below in conjunction with Fig. 2 loading interface on the circuit board 103, programmable logic device (PLD) 104, eeprom chip signal to be loaded is connected to do to specify.
Programmable logic device (PLD) 104, the corresponding connection of jtag interface signal of its JTAG mouth and loading interface 103, select arbitrarily the I/O interface of respective numbers and loading interface 103 the loading clock, load zone bit, load data/address signal and be connected.The EEPROM program Loading Control function logic code of programmable logic device (PLD) 104 is related with selected I/O pin.
Eeprom chip 1 and eeprom chip 2 are two chips of programmable logic device (PLD) 104 controlled loadings, electrical connection between eeprom chip and the programmable logic device (PLD) 104 comprises sheet choosing, reading and writing, data, address equisignal line, data line and the address wire of the eeprom chip that multi-disc is to be loaded connect together with bus mode, and each chip has the control signal wires such as independently sheet choosing, reading and writing.
As shown in Figure 3, the main flow process of the EEPROM program loading procedure of the embodiment of the invention comprises such as following step:
Step 1: main frame loading tool software produces by loading interface and loads the zone bit signal, gives programmable logic device (PLD).Whether the zone bit that the EEPROM program Loading Control function basis of programmable logic device (PLD) receives effectively carries out the step of back, when zone bit is effective, and execution in step 2; Zone bit is invalid, and then execution in step 8.
Step 2: send at main frame in the effective situation of loading zone bit of programmable logic device (PLD), main frame begins to send specific coding by data/address wire to programmable logic device (PLD), the EEPROM program Loading Control function of programmable logic device (PLD) with its with the encoding ratio of prior agreement, determine to read or write according to comparative result, will read accordingly to enable or write to enable to be set to effectively.The EEPROM program Loading Control function of programmable logic device (PLD) sends corresponding reading and writing enable signal and carries out reading and writing control to EEPROM.
Step 3: whether determining step 2 has produced effective reading and writing enable signal, whether the EEPROM program Loading Control function basis of programmable logic device (PLD) reads or writes EEPROM and moves to determine the sheet choosing, if so, then carry out step 4, if otherwise return step 1;
Step 4: as long as the corresponding read signal of EEPROM or write signal are effective, namely produce effective chip selection signal;
Step 5: main frame sends address information by the data/address wire [0:N] of loading interface to programmable logic device (PLD), and each clock period can be transmitted at most (N+1) bit; When programmable logic device (PLD) with
When the address bit wide of the address wire between EEPROM is wider, when for example bit wide is greater than (N+1) bit, can send in turn by continuous a plurality of clock period the mode of different address fields (being the address of different bits), realize the address information transmission of any bit wide.The EEPROM program Loading Control function of programmable logic device (PLD) with this address information as and eeprom chip between transmit data the address, this address is corresponding one by one with the routine data that sends eeprom chip to.
Step 6 and step 7 minute two lines are selected to carry out, and one is to write data routing step 6 (1) and step 7 (1), and one is read data path 6 (2) and 7 (2).
Step 6 (1): after the address information transmission finished, whether enable signal is write in judgement effective, if it is effective to write enable signal, then carries out next step data writing operation 7 (1), do not write data routing otherwise do not carry out.
Step 7 (1): 6 (1) judged results are write enable signal when effective, data 7 (1) operations are write in execution, main frame sends routine data by data/address wire to programmable logic device (PLD), and the EEPROM program Loading Control function of programmable logic device (PLD) cooperates the enable signal of writing of giving EEPROM to send routine data to eeprom chip again.
Step 6 (2): after the address information transmission finished, whether enable signal is read in judgement effective, if it is effective to read enable signal, then carries out next step read data operation 7 (2), otherwise do not carry out the read data path.
Step 7 (2): 6 (2) judged results are read enable signal when effective, carry out read data 7 (2) operations, main frame by data/address wire from the programmable logic device (PLD) receive data, the EEPROM program Loading Control function of programmable logic device (PLD) cooperate again give EEPROM read enable signal from the eeprom chip reading out data.
Step 8: if effectively do not load zone bit, then close read-write and enable process ends.
After the writing data or read data step (being that above-mentioned steps 1 is to step 7) and finish an of circulation, jump to next circulation, restart the cyclic process of " transfer data information that read/write is judged---transmitting address information---", until whole loading procedure finishes.
The above is preferred embodiment of the present invention only, is not for limiting protection scope of the present invention.The present invention also can have other various embodiments; in the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as and can be equal to accordingly change or replacement according to technical scheme of the present invention and design thereof, but these corresponding changes or replacement all should belong to the protection domain of claims of the present invention.
Claims (10)
1. the loading method of a program is characterized in that, is used for program to be loaded is loaded into Electrically Erasable Read Only Memory (EEPROM), and described method comprises:
EEPROM program Loading Control function logic code is loaded into programmable logic device (PLD);
After the described EEPROM program Loading Control function logic code operation in the described programmable logic device (PLD), carry out EEPROM program load operation order, described logical code in the described programmable logic device (PLD) is realized EEPROM program Loading Control function, and described program to be loaded is loaded into described EEPROM.
2. the method for claim 1 is characterized in that, described method also comprises:
Described logical code is being loaded after described programmable logic device (PLD), and whether the described loading of verification is successful, if load successfully, then carries out EEPROM program load operation order; Otherwise, end operation, or after getting rid of unusually, re-execute described logical code load operation order.
3. the method for claim 1 is characterized in that, described method also comprises:
Program to be loaded is being loaded behind EEPROM, and whether the described loading of verification is successful, if load successfully, then described method finishes; Otherwise, after getting rid of unusually, re-execute described EEPROM program load operation order.
4. the method for claim 1 is characterized in that,
The described EEPROM program Loading Control function logic code that loads in the described programmable logic device (PLD) is used for controlling the loading of one or more programs to be loaded.
5. such as claim 1 or 4 described methods, it is characterized in that described method also comprises:
When needs increase EEPROM subregion and/or online upgrading function, by revising the described EEPROM program Loading Control function logic code that loads in the described programmable logic device (PLD), realize the variation of described EEPROM program value-added tax function.
6. the loading system of a program is characterized in that, is applied to Circuits System, comprises main frame, loaded cable, loading interface, programmable logic device (PLD) and EEPROM, wherein,
Described programmable logic device (PLD) is used for, and loads and operation EEPROM program Loading Control function logic code;
Described main frame is used for, and by described loaded cable and described loading interface described EEPROM program Loading Control function logic code is loaded into described programmable logic device (PLD); And, after the described EEPROM program Loading Control function logic code operation in described programmable logic device (PLD), by described loaded cable, described loading interface and described EEPROM program Loading Control function logic code, program to be loaded is loaded into EEPROM.
7. system as claimed in claim 6 is characterized in that,
Described loading interface further comprises: be used for joint test behavior tissue (JTAG) interface of the EEPROM program Loading Control function logic code loading of programmable logic device (PLD), and be used for the EEPROM program loading interface that the EEPROM program loads;
Wherein, described jtag interface comprises model selection, clock input, data input, data output signal line; Described EEPROM program loading interface comprises the loading clock, loads zone bit, loads data/address signal line.
8. system as claimed in claim 6 is characterized in that,
Describedly program to be loaded is loaded the information that transmits in the loading procedure of EEPROM comprise data, address information; When the bit wide of described data/address information is wider, sequentially send the mode of the address of different bits by continuous a plurality of clock period, realize the data of any bit wide/address information transmission.
9. such as claim 6,7 or 8 described systems, it is characterized in that,
Described programmable logic device (PLD) is programmable logic device (PLD) existing in the described Circuits System or that arrange separately.
10. such as claim 6,7 or 8 described systems, it is characterized in that,
The described EEPROM program Loading Control function logic code that loads in the described programmable logic device (PLD) is used for controlling the loading of one or more programs to be loaded.
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| CN 200910250402 CN101706731B (en) | 2009-11-27 | 2009-11-27 | Method and system for loading program |
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| CN105263264A (en) * | 2015-10-08 | 2016-01-20 | 上海新跃仪表厂 | Complex wiring PCB (printed circuit board) with simple connection structure and preparation method thereof |
| CN106961792A (en) * | 2016-01-08 | 2017-07-18 | 上海和辉光电有限公司 | Wiring board, the method and system for improving wiring board utilization rate |
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| US6714041B1 (en) * | 2002-08-30 | 2004-03-30 | Xilinx, Inc. | Programming on-the-fly (OTF) |
| CN1564131A (en) * | 2004-03-29 | 2005-01-12 | 中兴通讯股份有限公司 | Method and device of realizing uppdating of single processor software |
| CN1845057A (en) * | 2005-09-30 | 2006-10-11 | 华为技术有限公司 | Flash memory loading method and system based on boundary scan |
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| CN1462979A (en) * | 2002-05-30 | 2003-12-24 | 华为技术有限公司 | Loading method of Flash chip and JTAG controller |
| US6714041B1 (en) * | 2002-08-30 | 2004-03-30 | Xilinx, Inc. | Programming on-the-fly (OTF) |
| CN1564131A (en) * | 2004-03-29 | 2005-01-12 | 中兴通讯股份有限公司 | Method and device of realizing uppdating of single processor software |
| CN1845057A (en) * | 2005-09-30 | 2006-10-11 | 华为技术有限公司 | Flash memory loading method and system based on boundary scan |
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