CN101707591B

CN101707591B - Processing method of SPI4 interface data packet

Info

Publication number: CN101707591B
Application number: CN200910093985A
Authority: CN
Inventors: 张磊; 刘兴奎; 窦晓光
Original assignee: Dawning Information Industry Beijing Co Ltd
Current assignee: Dawning Information Industry Beijing Co Ltd; Dawning Information Industry Co Ltd
Priority date: 2009-09-25
Filing date: 2009-09-25
Publication date: 2012-09-05
Anticipated expiration: 2029-09-25
Also published as: CN101707591A

Abstract

The invention provides a processing method of SPI4 interface data packet, which comprises the following steps of: acquiring midpoint data of a data valid window through carrying out delayed transaction on interface data; carrying out protocol conversion on the delayed interface data and removing control words in the conversed interface data; and carrying out alignment operation on the interface data after being removed the control words and receiving the interface data. By using the invention, a common interface of 10Gbps WAN, LAN, MAN and SAN can be realized, the design of an interface protocol is easier for engineering realization, pin number and power consumption are reduced and the completeness of a signal is enhanced.

Description

The processing method of SPI4 interface data bag

Technical field

The present invention relates to the communications field, and especially, relate to a kind of processing method of SPI4 interface data bag.

Background technology

SPI4.2 (system's packet switch interface, Level 4) is a new system-level interface standard, and the designer can be according to this standard for data and the communications service concentrated are developed flexibly, upgradeable system.The SPI4 interface is supported the high rate data transmission of a plurality of agreements to have nothing in common with each other, and these agreements comprise packets of information (POS frame), OC-192, Ethernet, Fast Ethernet, megabit Ethernet, 10 megabit Ethernets and the 10 megabit optical-fibre channel SAN etc. on the SONET/SDH.

At present, the SPI4 interface generally is to realize that through special ASIC or expensive IP core form receives bigger constraint, and cost is higher, and can not compatible 10Gbps WAN, procotols such as LAN, MAN and SAN.

Summary of the invention

Consider that SPI4 interface cost in the correlation technique is high, the problem of poor compatibility, the object of the present invention is to provide a kind of processing scheme of SPI4 interface data bag, with in addressing the above problem one of at least.

Processing method according to SPI4 interface data bag of the present invention comprises: postpone to handle the centre data acquisition that realizes data valid window through the docking port data; Interface data to after postponing carries out protocol conversion, and removes the control word in the conversion rear port data; Carry out alignment operation and reception to removing control word interface data afterwards.

Wherein, the delay carried out of docking port data is treated to: granularity is that the 4.8ns of 75ps postpones to handle.

And the processing of the interface data after postponing being carried out protocol conversion comprises: 16 SPI4 protocol conversions of the interface data after will postponing are 32 SPI4 agreements.

In addition, carry out alignment operation and specifically comprise removing interface data after the control word in the above-mentioned processing: will remove the high 16 or hang down 16 start bits of interface data after the control word as each frame.

In addition, the control word of removing in this method comprise following one of at least: IDLE control word, continuous control word.

By means of technical scheme of the present invention, can realize the common interface of 10Gbps WAN, LAN, MAN and SAN, make the interface protocol design be easier to Project Realization, reduce number of pin and power consumption, the enhancing signal integrality.

Description of drawings

Fig. 1 is the flow chart according to the processing method of the SPI4 interface data bag of the embodiment of the invention;

Fig. 2 is the sketch map according to the I/O interface model that processing method adopted of the SPI4 interface data bag of the embodiment of the invention;

Fig. 3 removes the state machine diagram of handling according to control word in the processing method of the SPI4 interface data bag of the embodiment of the invention;

Fig. 4 is the state machine diagram of handling according to alignment of data in the processing method of the SPI4 interface data bag of the embodiment of the invention.

Embodiment

Problem to SPI4 interface cost height, poor compatibility in the correlation technique; The present invention proposes to realize through FPGA the processing of SPI4 interface data; Make the SPI4 interface compatibility improve greatly through protocol conversion; Make that the SPI4 interface can be as the common interface of 10Gbps WAN, LAN, MAN and SAN, and can effectively reduce cost.

The present invention can be through multiple FPGA as carrier; With LX110T FPGA is example; The present invention can inner Ibufds (data buffering), IODELAY (postponing control) and the IDDR resources such as (converting single edge into along data or clock with two) of application device handle, and will combine accompanying drawing to describe embodiments of the invention in detail below.

Fig. 1 is the flow chart according to the processing method of the SPI4 interface data bag of the embodiment of the invention.As shown in Figure 1, comprise according to the processing method of the SPI4 interface data bag of the embodiment of the invention:

Step S102 postpones to handle the centre data acquisition that realizes data valid window through the docking port data, and it can granularity be 75ps totally 64 grades 4.8ns delay processing that this delay is handled, and is realized by the IODELAY technology;

Step S104 carries out protocol conversion to the interface data after postponing, and removes the control word in the conversion rear port data; Particularly, in this step, 16 SPI4 protocol conversions of the interface data after can application ID DR will postponing are 32 SPI4 agreements, and utilize Gap to remove part and remove control words such as IDLE control word, continuous control word, thereby reach the purpose that receives successive frame;

Step S106 carries out alignment operation and reception to removing control word interface data afterwards; Because 32 frames after step S104 handles also do not carry out alignment operation; That is, having height 16bit all is the situation that frame begins, and in step S106, can extract the part reception at frame and remove the continuous isl frame that part is uploaded from Gap; And use two data fifo and one control fifo and realize the situation that SOP/EOP interweaves; Thereby make low 16bit (or high 16bit iqvRct) is the start bit of frame.

Through above-mentioned processing, can realize the common interface of 10Gbps WAN, LAN, MAN and SAN, can be applied in the communication equipment such as line interface, switching backplane of router PHY to the descending connection of LINK.

Particularly, in step S102, can adopt IODELAY0 in the I/O interface model shown in Figure 2 ..., IODELAY17 postpones to handle.

Particularly; In step S 104; Can adopt IDDR0 in the I/O interface model shown in Figure 2 ..., IDDR16 postpones to handle; Because 16 SPI4 protocol conversions of the interface data after needing to postpone are position SPI4 agreement, so need resolve definition again to the control word in the agreement, concrete mode is following:

Band inner control word according to Rctl (2bit) and Rdat (32bit) produces proper data bag and synchronized generation frame start signal, and the possible situation of institute of 32bit SPI4 agreement has been shown in the table 1:

Table 1

Wherein, in the possible value of the Rctl of table 1 [1:0] ' 1 ' represent SOP or EOP possible situation.

It is 01 or 10 o'clock that possibly there are the following situation of intersecting: Rctl [1:0] value in above SOP and EOP; Control word possibly be independent SOP or EOP, also possibly promptly be that SOP is again EOP this moment; It is possible the situation of EOP or SOP that some bit territory this control word of decision has been shown in the table 2 in the control word, and all the other keep the perhaps impossible situation of situation for original agreement:

Table 2

In table 2, the Bit of possible cross section [15:12]: ' 1011 ', ' 1101 ', ' 1111 ', this control word possibly promptly be that EOP is again SOP in other words.

In step S104, can carry out control word with reference to state machine shown in Figure 3 and remove, in Fig. 3, state machine redirect condition abbreviation is represented the implication definition as follows:

Rdat representes the data channel of 32bit, and the variable that its inside can exist is following:

DD: the data channel of height 16bit all is valid data (data);

CI: high 16bit is the continue control word; Low 16bit is the Idle control word;

II: height 16bit is the Idle control word;

Definition such as other DC, CD, IC, ID, DI by that analogy.

Rctl representes the control channel of 2bit, and it is worth as follows:

11: on the expression Rdat all is control word, possibly be continue control word (C) or Idle control word (I);

10: it is control word that expression Rdat goes up high 16bit, and low 16bit is valid data;

Can know that in like manner it all is valid data that 00 expression Rdat goes up 32bit, and 01 and 10 is just in time opposite.

In addition, SOP:start of packet; EOP:end of packet; : the expression NOT operation; &: expression AND-operation; /: the expression OR operation; ‖: any conditional OR of expression above, for example,

Rdat：CD/DC

Rctl：10/01

‖(EOP&SOP)

Possible state has: Rdat=CD, and Rctl=10; Rdat=DC, and Rctl=01; EOP and SOP.

In addition, when carrying out the alignment of data processing, can be with reference to state machine shown in Figure 4.As shown in Figure 4, at first need be through training (Training) repeatedly, under the situation of Training result, stop to wait for for true (True), judge according to the value of Rctrl etc.

It should be noted that; Because the SPI4 agreement will reach 311Mhz; The inner highest frequency of FPGA can reach 550Mhz; So when the SPI4 agreement that redefines 32, requirement can only have the delay of one-level register, that is to say that will carry out a large amount of water operations makes agreement itself and FPGA compact internal structure combine the purpose that just can reach a high speed.

In sum, by means of technical scheme of the present invention, can realize the SPI4 interface, make interface protocol design be easier to Project Realization, reduce number of pin and power consumption, the enhancing signal integrality has realized the common interface of 10Gbps WAN, LAN, MAN and SAN; For needing the 10Gbps flow and based on the mega project of FPGA, can transplant through simple logic and be applied to the scene fast, and can be directed against different application, simple modification fifo interface and handshake can be used, and have good transplantability.

Obviously, it is apparent to those skilled in the art that above-mentioned each module of the present invention or each step can realize with the general calculation device; They can concentrate on the single calculation element; Perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element; Thereby; Can they be stored in the storage device and carry out, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize by calculation element.Like this, the present invention is not restricted to any specific hardware and software combination.

The above is merely the preferred embodiments of the present invention, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. the processing method of a SPI4 interface data bag is characterized in that, comprising:

Carry out the centre data acquisition that granularity is the 4.8ns delay processing realization data valid window of 75ps through the docking port data;

Said interface data to after postponing carries out protocol conversion, and removes the control word in the said interface data in conversion back;

Carry out alignment operation and reception to removing control word interface data afterwards,

Wherein, the processing of the said interface data after postponing being carried out protocol conversion comprises: 16 SPI4 protocol conversions of the said interface data after will postponing are 32 SPI4 agreements,

And wherein, carry out alignment operation and specifically comprise: will remove the high 16 or hang down 16 start bits of said interface data after the control word as each frame to removing interface data after the control word.

2. method according to claim 1 is characterized in that, the said control word of removal comprise following one of at least: IDLE control word, continuous control word.