CN101740454B

CN101740454B - Shallow slot isolation process for precisely controlling line width

Info

Publication number: CN101740454B
Application number: CN2008100439511A
Authority: CN
Inventors: 吕煜坤; 孙娟
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2008-11-20
Filing date: 2008-11-20
Publication date: 2011-08-24
Anticipated expiration: 2028-11-20
Also published as: CN101740454A

Abstract

The invention discloses a shallow slot isolation process for precisely controlling line width. The method comprises the following steps: one, coating photoresist on the surface of a silicon chip, exposing etching windows after exposure and development; two, measuring the line width between the etching windows; three, etching silicon nitride, monox and part of silicon on the etching windows; four, removing the photoresist by dry-method plasma; five, peeling off the photoresist through wet-method chemistry; and six, measuring the line width between shallow groove isolation structures. The shallow slot isolation process is characterized in that: the process adds one step between the step three and the step four, and adopts an isotropic etching process to etch the silicon nitride, the monox and the part of silicon on the etching windows. The process can precisely control the characteristic dimension of the shallow slot isolation process, reduces the precision requirement of etching CD, and removes the photoetching rework, thereby reducing production cost.

Description

The shallow grooved-isolation technique of precisely controlling line width

Technical field

The present invention relates to a kind of semiconductor integrated circuit manufacture method, particularly relate to a kind of shallow-trench isolation (STI) technology.

Background technology

Shallow grooved-isolation technique is the conventional process that semiconductor integrated circuit is made, and silicon chip surface also comprises the steps: to see also Fig. 1 after growing silicon oxide and deposit silicon nitride.

The 1st step, at the silicon chip surface resist coating, remove the photoresist of etching window behind the exposure imaging, keep all the other regional photoresists;

In the 2nd step, measure the live width between the etching window;

In the 3rd step, adopt anisotropic etch process to etch away silicon nitride, silica and part silicon in etching window;

In the 4th step, dry plasma is removed photoresist;

The 5th step, the wet chemistry stripping photoresist;

In the 6th step, measure the live width between the shallow groove isolation structure.

After the 3rd of said method went on foot and finishes, the generalized section of silicon chip saw also Fig. 2, etches away silicon nitride 12, silica 11 and part silicon 10 in etching window 14, has begun to take shape shallow groove isolation structure 15.Wherein a1 is the live width between the measured etching window 14 of the 2nd step, and a1 is commonly referred to photoetching CD (critical dimension, characteristic size).A2 is the live width between the shallow groove isolation structure 15 that the 6th step was about to measure, and a2 is commonly referred to final CD (Final CD).Δ a=a2-a1 is defined as etching live width loss amount (etch bias), and Δ a can be positive number or negative, ideally is zero.Under the situation shown in Figure 2, a2＜a1, so Δ a is a negative.

Along with dimensions of semiconductor devices diminishes gradually, also meticulous further to the live width control of shallow grooved-isolation technique.In process of production, suppose that the final CD of shallow grooved-isolation technique requires to be a3, Δ a fixes same equipment and material, therefore just requires a1=a3-Δ a.The situation that a1 exceeds the tolerable specification often takes place when the 2nd pacing amount a1, in order to make the a1 operation of doing over again usually up to specification, promptly repeats the 1st step photoetching process.This can increase the silicon chip defective, cause yield to reduce, also increased simultaneously photoetching equipment production pressure, cause the wasting of resources.

Summary of the invention

Technical problem to be solved by this invention provides a kind of shallow grooved-isolation technique, and this method can precisely controlling line width, and does not need to carry out photoetching and do over again.

For solving the problems of the technologies described above, the shallow grooved-isolation technique of precisely controlling line width of the present invention comprised the steps: for the 1st step, at the silicon chip surface resist coating, exposed etching window behind the exposure imaging;

In the 2nd step, measure the live width between the etching window;

In the 3rd step, adopt anisotropic etch process at etching window etch silicon nitride, silica and part silicon;

In the 4th step, dry plasma is removed photoresist;

The 5th step, the wet chemistry stripping photoresist;

In the 6th step, measure the live width between the shallow groove isolation structure;

Innovation part of the present invention is, increases by a step between the 3rd step and the 4th step: adopt isotropic etching technology at etching window etch silicon nitride, silica and part silicon, etch period

Wherein a1 is the live width between the etching window of described method the 2nd pacing amount, Δ a be before the etching live width loss amount measured of shallow grooved-isolation technique, a3 is the desired value of the live width between the shallow groove isolation structure, c is the lateral etching speed of isotropic etching.

The present invention can accurately control the characteristic size of shallow grooved-isolation technique, reduces the required precision to photoetching CD, eliminates photoetching and does over again, thereby reduce production costs.

Description of drawings

The present invention is further detailed explanation below in conjunction with drawings and Examples:

Fig. 1 is the flow chart of existing shallow grooved-isolation technique;

Fig. 2 is the silicon chip generalized section in the 3rd step of existing shallow grooved-isolation technique;

Fig. 3 is the flow chart of shallow grooved-isolation technique of the present invention;

Fig. 4 is the etch rate schematic diagram of isotropic etching;

Reference numeral is among the figure: the 10-silicon chip; The 11-silica; The 12-silicon nitride; The 13-photoresist; The 14-etching window; The 15-shallow groove isolation structure; The photoetching CD of a1-shallow grooved-isolation technique; The final CD of a2-shallow grooved-isolation technique.

Embodiment

See also Fig. 3, the shallow grooved-isolation technique of precisely controlling line width of the present invention also comprises the steps: after silicon chip surface growing silicon oxide and deposit silicon nitride

The 1st step, at the silicon chip surface resist coating, remove the photoresist of etching window behind the exposure imaging, keep all the other regional photoresists.

In the 2nd step, measure the live width between the etching window, just the photoetching CD of shallow grooved-isolation technique.

In the 3rd step, adopt anisotropic etch process to etch away silicon nitride, silica and part silicon in etching window.

In the 4th step, adopt isotropic etching technology at etching window etch silicon nitride, silica and part silicon.

In the 5th step, dry plasma is removed photoresist.

The 6th step, the wet chemistry stripping photoresist.

In the 7th step, measure the live width between the shallow groove isolation structure, just the final CD of shallow groove isolation structure.

During said method the 4th goes on foot, etch period

Wherein: a1 is the live width between the etching window of described method the 2nd pacing amount, just photoetching CD.Δ a is an etching live width loss amount, and under the constant situation of etching apparatus, material, condition, Δ a is also constant, therefore can know the value of Δ a from shallow grooved-isolation technique before.A1+ Δ a is equivalent to the a2 in the existing shallow grooved-isolation technique.A3 is the desired value of the final CD of shallow grooved-isolation technique, is known naturally.C is the lateral etching speed of isotropic etching.

See also Fig. 4, the lateral etching width of isotropic etching is along with the linear variation of etch period, and promptly the lateral etching speed of isotropic etching is fixed value.Under the constant situation of etching apparatus, material, condition, can be at any three etch period point sampling and measuring lateral etching width, as long as these three sampling points are point-blank, the slope of this straight line is lateral etching speed so.

Said method is in the 4th step, and reaction condition can be set to: the pressure of reaction chamber is 5～20mT, and the top power is 800～1500w, and deflection power is 0～10w, and feeding the fluorocarbon gases flow is 50～250sccm, and the feeding argon gas is 50～150sccm.

The 3rd step and the 4th of said method goes on foot, can be at the same cavity of same board, and also can be at the different cavitys of different platform.

The present invention can be more accurate to live width control.When the 1st step photoetching CD is big, need not to carry out photoetching and do over again, in the isotropic etching that only needs to increase in the 4th step further etching get final product.Therefore reduced requirement to photoetching process.

Claims

1. the shallow grooved-isolation technique of a precisely controlling line width, this method comprises the steps:

In the 1st step,, expose etching window behind the exposure imaging at the silicon chip surface resist coating;

In the 2nd step, measure the live width between the etching window;

In the 4th step, dry plasma is removed photoresist;

The 5th step, the wet chemistry stripping photoresist;

It is characterized in that: between the 3rd step and the 4th step, increase by a step: adopt isotropic etching technology at etching window etch silicon nitride, silica and part silicon, etch period

2. the shallow grooved-isolation technique of precisely controlling line width according to claim 1, it is characterized in that: the isotropic etch step of described increase, the pressure of reaction chamber is 5～20mT, the top power is 800～1500w, deflection power is 0～10w, feeding the fluorocarbon gases flow is 50～250sccm, and the feeding argon gas is 50～150sccm.