CN101770358A - System and method for processing jump instruction of microprocessor in branch prediction way - Google Patents
System and method for processing jump instruction of microprocessor in branch prediction way Download PDFInfo
- Publication number
- CN101770358A CN101770358A CN201010111407A CN201010111407A CN101770358A CN 101770358 A CN101770358 A CN 101770358A CN 201010111407 A CN201010111407 A CN 201010111407A CN 201010111407 A CN201010111407 A CN 201010111407A CN 101770358 A CN101770358 A CN 101770358A
- Authority
- CN
- China
- Prior art keywords
- instruction
- jump instruction
- redirect
- jump
- prediction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a system and a method for processing a jump instruction of a microprocessor in a branch prediction way. The system comprises a coding module and a transmission module, wherein the coding module comprises a branch predictor used for predicting by adopting a static prediction method when the jump instruction to be processed is in the jump execution type or adopting a dynamic prediction method when the jump instruction to be processed is not in the jump execution type after the coding module judges that an instruction to be processed is the jump instruction and judges the type of the jump instruction through precoding, and directly writing the jump instruction to be processed and a delay slot instruction thereof in an operational queue in a sequence of the instructions in a program; and the transmission module comprises a prediction result processor used for canceling the instruction executed by error and continue fetching in a correct jump direction when the branch predictor predicts the jump instruction by error after the jump instruction is executed and written back to the transmission module. The system cancels operation by adopting different cancellation methods on the basis that whether the instruction is the jump execution instruction or not when the instruction is cancelled.
Description
Technical field
The present invention relates to the micro-processor architecture field, specially refer to a kind of jump instruction of microprocessor in branch prediction way disposal system and method.
Background technology
In existing microprocessor system, jump instruction brings many challenges for the design of microprocessor.For example for the microprocessor that flowing structure is arranged, when microprocessor when carrying out one section program that jump instruction arranged, if run into jump instruction, may determine so the earliest jump instruction whether the pipelining-stage of redirect and jump target addresses be the decoding stage, for example directly redirect (jump) instruction.
But, to wait until that generally the execute phase could determine the redirect direction and the jump target addresses of jump instruction after finishing to most of jump instruction.And during this time follow-up instruction may be taken out from internal memory, What is more has begun to carry out, therefore when jump instruction is finally determined redirect, these acquired instructions or the instruction of having carried out all need to be cancelled, and microprocessor need obtain instruction again and carries out from the correct destination address of jump instruction.This will reduce microprocessor performance widely.
Therefore in existing microprocessor Design, mostly adopt diverse ways to handle jump instruction, thereby improve processor performance.
Wherein, the method that prior art discloses a kind of general processing jump instruction is a branch prediction method, this method is when running into jump instruction, microprocessor adopt specific mode predict the direction of jump instruction (such as, whether conditional branching is predicted its redirect), perhaps predict the destination address (, predicting the destination address of its redirect) of jump instruction for example for indirect jump instruction and program link order.Microprocessor is inferred executive routine according to prediction result, and these instructions are taken out to send in the streamline then from internal memory and carried out before the final solution of the result of jump instruction.If branch prediction is correct, performance of processors will be improved so.This be because the result of jump instruction is final solve before, the instruction after these branch's jump instructions has begun to carry out (no matter be jump target addresses, or the subsequent instructions of jump instruction).If yet the branch prediction mistake, these infer that the instruction of carrying out will be cancelled.
But,, cancel the design complexities that these instructions will increase processor as the microprocessor of MIPS structure for the superscalar processor structure.
Simultaneously, this branch prediction method of prior art is for the microprocessor of MIPS structure, because the MIPS instruction set stipulates that all jump instructions all must have delay slot instruction, therefore also needs processing delay slot order etc., thereby brings more complicated problems.
So-called delay slot instruction is meant immediately following that instruction after jump instruction.
In the microprocessor of MIPS structure, for most of jump instruction no matter finally whether redirect of jump instruction, the delay slot instruction of its correspondence all must be carried out, but for (branchlikely) instruction is carried out in redirect, delay slot instruction finally whether carry out be come according to the redirect direction that (branch likely) instruction is carried out in redirect fixed.Have only when (branch likely) instruction redirect is carried out in this redirect, the instruction that postpones groove just can be performed; Otherwise the instruction that postpones groove does not need to carry out.Therefore for the MIPS instruction set, for different jump instructions, delay slot instruction needs differentiating and processing.
Because cannot be as the delay slot instruction except jump instruction, the instruction of other any types all can be done delay slot instruction, therefore locate delay slot instruction and determine whether cancelling delay slot instruction according to the jump instruction of delay slot instruction correspondence, make existing branch prediction method complicated more, existing branch prediction method is not suitable for the microprocessor of superscalar processor structure, particularly the microprocessor of MIPS structure.
Summary of the invention
The object of the present invention is to provide a kind of jump instruction of microprocessor in branch prediction way disposal system and method, it makes that the branch prediction method of microprocessor is simpler, thereby improves the performance of microprocessor.
A kind of jump instruction of microprocessor in branch prediction way disposal system for realizing that the object of the invention provides comprises decoding module and transmitter module.
Described decoding module comprises branch predictor, being used for judging pending instruction at described decoding module by pre-decode is jump instruction, and after the type of jump instruction, whether according to this pending jump instruction is that type is carried out in redirect, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to instructing order in the program operation queue item that writes direct;
Described transmitter module comprises the processor that predicts the outcome, is used for after jump instruction executes and write back to described transmitter module, and at described branch predictor during to the prediction error of jump instruction, the wrong instruction of carrying out of cancellation and continue to get finger from correct redirect direction; When the cancellation instruction,, take different canceling methods to cancel operation according to whether being the redirect execution command.
More preferably, whether this pending jump instruction of described basis is that type is carried out in redirect, and adopts static prediction or performance prediction method to predict, is meant:
According to the type of pending jump instruction, if the redirect execution command then adopts the prediction of static prediction method to this pending jump instruction, and predicts its redirect; Otherwise, if the jump instruction that other non-redirects are carried out then adopts the performance prediction method to predict.
More preferably, whether described basis is the redirect execution command, takes different canceling methods to cancel operation, is meant:
If the jump instruction of branch prediction mistake is the redirect execution command, then execution is all cancelled in the instruction of all after this jump instruction; If the jump instruction of branch prediction mistake is not the redirect execution command, then execution is all cancelled in the instruction of all behind the delay slot instruction of this jump instruction.
For realizing that the object of the invention more provides a kind of jump instruction of microprocessor in branch prediction way disposal route, comprise the following steps:
Steps A, judge pending instruction by pre-decode is jump instruction, and after the type of jump instruction, whether according to this pending jump instruction is that type is carried out in redirect, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to instructing order in the program operation queue item that writes direct;
Step B, after jump instruction executes and writes back to transmitter module, to the prediction error of jump instruction the time, the wrong instruction of carrying out of cancellation and continue to get finger from correct redirect direction; When the cancellation instruction,, take different canceling methods to cancel operation according to whether being the redirect execution command.
More preferably, in the described steps A, whether be that type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, comprise the following steps:
Steps A 1 is if the redirect execution command then adopts the prediction of static prediction method to this pending jump instruction, and predicts its redirect;
Steps A 2 is if the jump instruction that other non-redirects are carried out then adopts the performance prediction method to predict.
More preferably, among the described step B,, take different canceling methods to cancel operation, comprise the following steps: according to whether being the redirect execution command
Step B1, if the jump instruction of branch prediction mistake is the redirect execution command, then execution is all cancelled in the instruction of all after this jump instruction;
Step B2, if the jump instruction of branch prediction mistake is not the redirect execution command, then execution is all cancelled in the instruction of all behind the delay slot instruction of this jump instruction.
Beneficial effect of the present invention: jump instruction of microprocessor in branch prediction way disposal system of the present invention and method, it takes new Forecasting Methodology, make and carry out new processing at cancellation delay slot instruction after the jump instruction prediction error, make that the branch prediction method of microprocessor is simpler, when reducing the microprocessor hardware complexity, can improve the performance of microprocessor.
Description of drawings
Fig. 1 is a jump instruction of microprocessor in branch prediction way disposal system structural representation of the present invention;
Fig. 2 is jump instruction of microprocessor in branch prediction way process flow figure of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, a kind of jump instruction of microprocessor in branch prediction way disposal system of the present invention and method are further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein is only in order to explain the present invention rather than limitation of the present invention.
In embodiments of the present invention, with based on the microprocessor of MIPS structure of five-stage pipeline structure be example, jump instruction of microprocessor in branch prediction way disposal system of the present invention and method are described, but, it will be understood by those skilled in the art that jump instruction of microprocessor in branch prediction way disposal system of the present invention and method also go in the microprocessor of other superscalar processor structure.
As shown in Figure 1, in order to further specify the present invention, the embodiment of the invention at first illustrate based on the microprocessor of MIPS structure of five-stage pipeline structure, the same with the microprocessor of other most of superscalar processor structures, the embodiment of the invention based on the microprocessor of MIPS structure of pipeline organization, comprise following five part parts, be respectively:
Get finger print piece 1, be used for the finger of getting of streamline, and from internal memory or Instructions Cache (cache), obtain instruction (instruction) in program according to the precedence that instruction occurs;
Decoding module 2, the decoding that is used to instruct;
It, and is delivered in the operation queue instruction decode (instruction after the decoding is called operation) according to the precedence that occurs in program of instruction, and the state of its operation is to launch;
Transmitter module 3, the emission that is used to instruct;
It selects not emission and the off-the-shelf operation issue of operand to the function corresponding unit from operation queue, and the status modifier of the operation that will launch is for launching;
Ordering calculation functional unit 4, the computing that is used to instruct;
Its each functional unit (comprising memory access parts and a plurality of arithmetic units etc.) is carried out the operation that launches from operation queue, and operation result is write back to corresponding of operation queue, and the mode bit of revising this operation has write back;
Register file module 5 is used to receive the submission of instruction;
It submits instruction to so if the operation of operation queue team head has been launched and operation result returns, and operation result is write back register.
Jump instruction of microprocessor in branch prediction way disposal system of the present invention, in the decoding module 2 of described microprocessor, comprise branch predictor 21, being used for judging pending instruction at decoding module 2 by pre-decode is jump instruction, and after the type of jump instruction, whether according to this pending jump instruction is that (branch likely) type is carried out in redirect, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to instructing order in the program operation queue item that writes direct.
In the embodiment of the invention, the decoding module 2 of microprocessor enters into the decoding stage in pending instruction, judge by pre-decode, thereby determine whether this pending instruction is jump instruction, and after determining that it is jump instruction, judge the type of this pending jump instruction.
Whether decoding module 2 is jump instruction and the type of determining jump instruction in the decoding stage by the pre-decode decision instruction, it is a kind of prior art, those skilled in the art are according to the description of present embodiment, can realize pre-decode process of the present invention, therefore, describe in detail no longer one by one in embodiments of the present invention.
The branch predictor 21 of the embodiment of the invention according to the type of pending jump instruction, if (branch likely) instruction is carried out in redirect, then adopts the prediction of static prediction method to this pending jump instruction, and predicts its redirect; Otherwise,, then adopt the performance prediction method to predict if the jump instruction of (branch likely) is carried out in other non-redirects; Then will this pending jump instruction and delay slot instruction according to the order of instruction in the program operation queue item that writes direct.
Performance prediction and static prediction are the key concept in the processor structure, basic on, performance prediction is to carry out direction history according to this jump instruction to predict this redirect direction; Static prediction only then is meant simple forecast, and this instructs whether redirect, and the execution direction of its prediction in the process that whole procedure is carried out all is the same.
The transmitter module 3 of the embodiment of the invention is used for all instructions, and comprising that pending jump instruction and delay slot instruction thereof are transmitted directly in the corresponding instruction calculation function unit 4 carries out computing.
The transmitter module 3 of the embodiment of the invention, any delay slot instruction is not carried out special processing, be that any delay slot instruction all need not special processing, and jump instruction that all are pending and delay slot instruction thereof carry out computing with the same being transmitted directly to of other instructions in the corresponding instruction calculation function unit 4, reduce the complexity of microprocessor hardware.
The transmitter module 3 of the embodiment of the invention, also comprise the processor 31 that predicts the outcome, be used for after jump instruction executes and write back to transmitter module 3, when the prediction error of 21 pairs of jump instructions of branch predictor, cancel the wrong instruction of carrying out and continue to get finger from correct redirect direction; When the cancellation instruction,, take different canceling methods to cancel operation according to whether being that (branch likely) instruction is carried out in redirect.
If mistake appears in the prediction of 21 pairs of jump instructions of branch predictor, then wrong the execution then of cancellation instructed, and continues instruction fetch from correct execution direction then.The processor 31 that predicts the outcome takes different canceling methods to cancel operation according to different jump instruction types.
Carry out (branch likely) instruction if the jump instruction of branch prediction mistake is redirect, then execution is all cancelled in the instruction of all after this jump instruction; Do not carry out (branch likely) instruction if the jump instruction of branch prediction mistake is not redirect, then execution is all cancelled in the instruction of all behind the delay slot instruction of this jump instruction.
For the redirect execution command, when having only the jump instruction redirect, its delay slot instruction just can be performed, if not redirect of jump instruction can not be performed so.Because just with static prediction and predict its redirect, when prediction was carried out, the delay groove of all redirects execution commands all was performed like this before in jump instruction.Therefore if prediction is correct, this jump instruction redirect is described then, then delay slot instruction does not need to be cancelled execution; And if prediction error, illustrate that then this jump instruction in fact can redirect, therefore the delay groove that is performed when prediction is carried out is carried out and need be cancelled.
If the prediction of 21 pairs of jump instructions of branch predictor does not have mistake, jump instruction is transmitted into carries out computing in the ordering calculation corresponding functional unit, the result is write back to transmitter module 3, the result of execution with predict the outcome consistent, be branch predictor 21 prediction redirects, and execution result show redirect; Perhaps predicted branches fallout predictor 21 is predicted not redirect, and execution result is when showing not redirect, does not need transmitter module 3 to carry out other any processing after the mode bit of then revising this operation has write back, directly submits to.
The register file module 5 of the embodiment of the invention is used for directly instruction results being submitted to, and being need not to handle after instruction is carried out.
The register file module 5 of the embodiment of the invention in presentation stage, because the processor 31 that predicts the outcome has been handled execution result, therefore only needs directly to submit instruction execution result to according to normal submission logic, need not to carry out other special processings.
So just make that the branch prediction method of microprocessor is simpler, when reducing the microprocessor hardware complexity, can improve the performance of microprocessor.
Correspondingly, the present invention also provides a kind of jump instruction of microprocessor in branch prediction way disposal route, and as shown in Figure 2, it comprises the steps:
Step S100 from the pending instruction of taking-up of the streamline of microprocessor, and obtains instruction according to the precedence that this instruction occurs from internal memory or Instructions Cache (cache) in program.
Step S200, judge pending instruction by pre-decode is jump instruction, and after the type of jump instruction, whether according to this pending jump instruction is that (branch likely) type is carried out in redirect, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to instructing order in the program operation queue item that writes direct.
In step S200, whether be that (branchlikely) type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, comprise the following steps:
Step S210 if (branch likely) instruction is carried out in redirect, then adopts the prediction of static prediction method to this pending jump instruction, and predicts its redirect;
Step S220 if the jump instruction of (branch likely) is carried out in other non-redirects, then adopts the performance prediction method to predict.
Step S300, with all instructions, comprising that pending jump instruction and delay slot instruction thereof are transmitted directly in the corresponding instruction calculation function unit 4 carries out computing.
Step S400, after jump instruction executes and writes back to transmitter module 3, to the prediction error of jump instruction the time, the wrong instruction of carrying out of cancellation and continue to get finger from correct redirect direction; When the cancellation instruction,, take different canceling methods to cancel operation according to whether being that (branch likely) instruction is carried out in redirect.
In step S400, according to whether being that (branch likely) instruction is carried out in redirect, take different canceling methods to cancel operation, comprise the following steps:
Step S410 carries out (branch likely) instruction if the jump instruction of branch prediction mistake is redirect, and then execution is all cancelled in the instruction of all after this jump instruction;
Step S420 does not carry out (branch likely) instruction if the jump instruction of branch prediction mistake is not redirect, and then execution is all cancelled in the instruction of all behind the delay slot instruction of this jump instruction.
Described step S400 also comprises the following steps:
If branch predictor does not have mistake to the prediction of jump instruction, jump instruction is transmitted into carries out computing in the ordering calculation corresponding functional unit 4, the result is write back, the result of execution with predict the outcome consistently, promptly predict redirect, and execution result shows redirect; Perhaps predict not redirect, and execution result is when showing not redirect, do not need decoding module 2 to carry out other any processing after the mode bit of then revising this operation has write back, directly submit to.
Step S500 after instruction is carried out, directly is submitted to instruction results the register file module.
With two examples explanation jump instruction of microprocessor in branch prediction way disposal system of the present invention and method are described in further detail below.
Example 1. is established in this example, and operation queue has 8, promptly can have simultaneously 8 instructions to carry out in streamline simultaneously.If operation queue has had three instructions, and queue head pointer points to the second instruction.At first decoding module is deciphered the instruction of getting the finger print piece and getting; In order to accelerate branch prediction, in decoding, pre-decode is done in these instructions, the result according to pre-decode does branch prediction then.After pre-decode, find that article one instruction is that (branch likely) instruction is carried out in redirect, then predict its redirect, and the redirect that will decipher bus is carried out and is identified (blikely sign) and be changed to 1; The second instruction is the delay slot instruction of this instruction.And then these two instructions are fed to operation queue.Wherein the 4th of article one instruction write operation formation, and the blikely of operation queue sign is changed to 1; Emission state sign (issued sign) is changed to 0; Result phase sign (WB sign) is changed to 0, and the 5th of second instruction write operation formation, its blikely identifies and is changed to 0; The issued sign is changed to 0; The WB sign is changed to 0.Next is clapped, and gets the finger print piece and will continue to get finger from the jump target addresses of this jump instruction.
At launching phase, transmitter module finds not emission and the off-the-shelf instruction of operand that it is transmitted into corresponding ordering calculation functional unit from operation queue.If second and the 3rd of operation queue launch, and the 4th and the 5th 's operand is ready to, is transmitted into the function corresponding unit simultaneously with the 4th and the 5th so; If only the 4th operand is ready to, so only be transmitted into corresponding functional unit with the 4th; If only the 5th operand is ready to, so only be transmitted into corresponding functional unit with the 5th.In out of order transmitter logic, the shooting sequence of these two instructions is without any contact.
Writing back the stage, if the 4th result writes back, and the execution result of instruction is not redirect, be 1 with the 4th WB position so, and judge whether its blikely sign is 1, if 1, and all instructions of (comprising the 5th) after the 5th are all cancelled execution.Cancel the operation of these instructions, if these operations are just carried out at functional unit, cancellation is carried out; Then that these instructions are shared operation queue item discharges.Get the finger print piece at last and will continue instruction fetch from correct path.If writing back the stage, the execution result of instruction was redirect when the 4th result write back, and was left intact so, and only the WB position with four instructions is 1.
Presentation stage is submitted instruction to according to the normal logic of submitting to, need not special processing.
Example 2. is established in this example, and operation queue has 8, promptly can have simultaneously 8 instructions to carry out in streamline simultaneously.If operation queue has had three instructions, and queue head pointer points to the second instruction.At first decoding module is deciphered the instruction of getting the finger print piece and getting; In order to accelerate branch prediction, in decoding, pre-decode is done in these instructions, the result according to pre-decode does branch prediction then.After pre-decode, find that article one instruction is common jump instruction, predict its whether redirect according to branch predictor.And the blikely sign that will decipher bus is changed to 0; The second instruction is the delay slot instruction of this instruction.And then these two instructions are fed to operation queue.Wherein the 4th of article one instruction write operation formation, and the blikely of operation queue sign is changed to 0; The issued sign is changed to 0; WB sign is changed to 0, and the 5th of second instruction write operation formation, its blikely sign is changed to 0; The issued sign is changed to 0; The WB sign is changed to 0.Next is clapped, and gets the finger print piece and will continue to get finger from the predicted path of this jump instruction.
At launching phase, transmitter module finds not emission and the off-the-shelf instruction of operand that it is transmitted into corresponding ordering calculation functional unit from operation queue.If second and the 3rd of operation queue launch, and the 4th and the 5th 's operand is ready to, is transmitted into the function corresponding unit simultaneously with the 4th and the 5th so; If only the 4th operand is ready to, so only be transmitted into corresponding functional unit with the 4th; If only the 5th operand is ready to, so only be transmitted into corresponding functional unit with the 5th.In out of order transmitter logic, the shooting sequence of these two instructions is without any contact.
Writing back the stage, if the 4th result writes back, and the execution result and the prediction result of instruction are inconsistent, but predict that promptly the redirect execution result shows not redirect; Perhaps predicting not redirect but execution result shows redirect, is 1 with the 4th WB position so; And judge whether its blikely sign is 1,, so execution is all cancelled in all instructions of (not comprising the 5th) after the 5th if be not 1.The operation of cancelling these instructions comprises that cancellation is carried out if these operations are just carried out at functional unit; Then that these instructions are shared operation queue item discharges.Get the finger print piece at last and will continue instruction fetch from correct path.If writing back the stage, when the 4th result writes back the execution result of instruction with predict the outcome consistent, but promptly predict redirect execution result demonstration redirect; Perhaps predict not redirect but execution result shows not redirect, be left intact so that only the WB position with four instructions is 1.
Presentation stage is submitted instruction to according to the normal logic of submitting to, need not special processing.
Jump instruction of microprocessor in branch prediction way disposal system of the present invention and method, adopt branch predictor to predict, and carry out the back result by the processor that predicts the outcome according to jump instruction and handle, make and carry out new processing at cancellation delay slot instruction after the jump instruction prediction error, make that the branch prediction method of microprocessor is simpler, when reducing the microprocessor hardware complexity, can improve the performance of microprocessor.
Should be noted that at last that obviously those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification.
Claims (11)
1. a jump instruction of microprocessor in branch prediction way disposal system comprises decoding module and transmitter module, it is characterized in that:
Described decoding module comprises branch predictor, being used for judging pending instruction at described decoding module by pre-decode is jump instruction, and after the type of jump instruction, whether according to this pending jump instruction is that type is carried out in redirect, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to instructing order in the program operation queue item that writes direct;
Described transmitter module comprises the processor that predicts the outcome, is used for after jump instruction executes and write back to described transmitter module, and at described branch predictor during to the prediction error of jump instruction, the wrong instruction of carrying out of cancellation and continue to get finger from correct redirect direction; When the cancellation instruction,, take different canceling methods to cancel operation according to whether being the redirect execution command.
2. branch prediction disposal system according to claim 1 is characterized in that, whether this pending jump instruction of described basis is that type is carried out in redirect, and adopts static prediction or performance prediction method to predict, is meant:
According to the type of pending jump instruction, if the redirect execution command then adopts the prediction of static prediction method to this pending jump instruction, and predicts its redirect; Otherwise, if the jump instruction that other non-redirects are carried out then adopts the performance prediction method to predict.
3. branch prediction disposal system according to claim 1 is characterized in that, whether described basis is the redirect execution command, takes different canceling methods to cancel operation, is meant:
If the jump instruction of branch prediction mistake is the redirect execution command, then execution is all cancelled in the instruction of all after this jump instruction; If the jump instruction of branch prediction mistake is not the redirect execution command, then execution is all cancelled in the instruction of all behind the delay slot instruction of this jump instruction.
4. according to each described branch prediction disposal system of claim 1 to 3, it is characterized in that, also comprise ordering calculation functional unit and register file module;
Jump instruction that transmitter module is pending with all and delay slot instruction thereof are transmitted directly in the corresponding instruction calculation function unit and carry out computing.
Described register file module is used for directly instruction results being submitted to after instruction is carried out.
5. a jump instruction of microprocessor in branch prediction way disposal route is characterized in that, comprises the following steps:
Steps A, judge pending instruction by pre-decode is jump instruction, and after the type of jump instruction, whether according to this pending jump instruction is that type is carried out in redirect, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to instructing order in the program operation queue item that writes direct;
Step B, after jump instruction executes and writes back to transmitter module, to the prediction error of jump instruction the time, the wrong instruction of carrying out of cancellation and continue to get finger from correct redirect direction; When the cancellation instruction,, take different canceling methods to cancel operation according to whether being the redirect execution command.
6. whether branch prediction disposal route according to claim 5 is characterized in that, in the described steps A, be that type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, comprises the following steps:
Steps A 1 is if the redirect execution command then adopts the prediction of static prediction method to this pending jump instruction, and predicts its redirect;
Steps A 2 is if the jump instruction that other non-redirects are carried out then adopts the performance prediction method to predict.
7. whether branch prediction disposal route according to claim 5 is characterized in that, among the described step B, according to being the redirect execution command, take different canceling methods to cancel operation, comprises the following steps:
Step B 1, if the jump instruction of branch prediction mistake is the redirect execution command, then execution is all cancelled in the instruction of all after this jump instruction;
Step B2, if the jump instruction of branch prediction mistake is not the redirect execution command, then execution is all cancelled in the instruction of all behind the delay slot instruction of this jump instruction.
8. branch prediction disposal route according to claim 7 is characterized in that, among the described step B, also comprises the following steps:
If branch predictor does not have mistake to the prediction of jump instruction, jump instruction is transmitted into carries out computing in the ordering calculation corresponding functional unit, the result is write back, the result of execution with predict the outcome consistently, promptly predict redirect, and execution result shows redirect; Perhaps predict not redirect, and execution result is when showing not redirect, do not need decoding module to carry out other any processing after the mode bit of then revising this operation has write back, directly submit to.
9. according to each described branch prediction disposal route of claim 5 to 8, it is characterized in that, also comprise the following steps: before the described steps A
From the pending instruction of taking-up of the streamline of microprocessor, and from internal memory or Instructions Cache, obtain instruction in program according to the precedence that this instruction occurs.
10. branch prediction disposal route according to claim 9 is characterized in that, also comprises the following steps: between described steps A and the step B
Jump instruction that all are pending and delay slot instruction thereof are transmitted directly in the corresponding instruction calculation function unit and carry out computing.
11. branch prediction disposal route according to claim 10 is characterized in that, also comprises the following steps: after the described step B
After instruction is carried out, directly instruction results is submitted to the register file module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010111407 CN101770358B (en) | 2010-02-10 | 2010-02-10 | System and method for processing jump instruction of microprocessor in branch prediction way |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010111407 CN101770358B (en) | 2010-02-10 | 2010-02-10 | System and method for processing jump instruction of microprocessor in branch prediction way |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101770358A true CN101770358A (en) | 2010-07-07 |
| CN101770358B CN101770358B (en) | 2013-01-30 |
Family
ID=42503240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010111407 Active CN101770358B (en) | 2010-02-10 | 2010-02-10 | System and method for processing jump instruction of microprocessor in branch prediction way |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101770358B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102360283A (en) * | 2011-09-28 | 2012-02-22 | 中国科学院声学研究所 | Processing method for calling subprogram of microprocessor, and device for same |
| CN103218206A (en) * | 2012-01-18 | 2013-07-24 | 上海算芯微电子有限公司 | Instruction branch pre-jump method and system |
| WO2015027809A1 (en) * | 2013-08-30 | 2015-03-05 | 华为技术有限公司 | Instruction processing method and device, and processor |
| CN104793921A (en) * | 2015-04-29 | 2015-07-22 | 深圳芯邦科技股份有限公司 | Instruction branch prediction method and system |
| CN103984531B (en) * | 2014-05-30 | 2016-09-28 | 龙芯中科技术有限公司 | Overlength branch redirects processing method and processing device |
| CN106294276A (en) * | 2016-08-08 | 2017-01-04 | 合肥工业大学 | A kind of coarseness multinuclear that is applicable to calculates transmitter module and the working method thereof of system |
| CN106293642A (en) * | 2016-08-08 | 2017-01-04 | 合肥工业大学 | A kind of branch process module and branch process mechanism thereof calculating system for coarseness multinuclear |
| CN109101276A (en) * | 2018-08-14 | 2018-12-28 | 阿里巴巴集团控股有限公司 | The method executed instruction in CPU |
| CN109710268A (en) * | 2017-10-25 | 2019-05-03 | 康烁 | Binary translation method and device towards VLIW framework |
| CN112613039A (en) * | 2020-12-10 | 2021-04-06 | 海光信息技术股份有限公司 | Performance optimization method and device for ghost vulnerability |
| CN113076136A (en) * | 2021-04-23 | 2021-07-06 | 中国人民解放军国防科技大学 | Safety protection-oriented branch instruction execution method and electronic device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6247122B1 (en) * | 1998-12-02 | 2001-06-12 | Ip-First, L.L.C. | Method and apparatus for performing branch prediction combining static and dynamic branch predictors |
| CN1359488A (en) * | 1999-05-03 | 2002-07-17 | 英特尔公司 | Optimized execution of statically strongly predicted branch instructions |
| US20040030838A1 (en) * | 2002-08-12 | 2004-02-12 | Van De Waerdt Jan-Willem | Instruction cache way prediction for jump targets |
| CN1560735A (en) * | 2004-03-09 | 2005-01-05 | 中国人民解放军国防科学技术大学 | Recovery method of return address stack in double stack return address predicator |
-
2010
- 2010-02-10 CN CN 201010111407 patent/CN101770358B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6247122B1 (en) * | 1998-12-02 | 2001-06-12 | Ip-First, L.L.C. | Method and apparatus for performing branch prediction combining static and dynamic branch predictors |
| CN1359488A (en) * | 1999-05-03 | 2002-07-17 | 英特尔公司 | Optimized execution of statically strongly predicted branch instructions |
| US20040030838A1 (en) * | 2002-08-12 | 2004-02-12 | Van De Waerdt Jan-Willem | Instruction cache way prediction for jump targets |
| CN1560735A (en) * | 2004-03-09 | 2005-01-05 | 中国人民解放军国防科学技术大学 | Recovery method of return address stack in double stack return address predicator |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102360283B (en) * | 2011-09-28 | 2014-01-08 | 中国科学院声学研究所 | Processing method for calling subprogram of microprocessor, and device for same |
| CN102360283A (en) * | 2011-09-28 | 2012-02-22 | 中国科学院声学研究所 | Processing method for calling subprogram of microprocessor, and device for same |
| CN103218206A (en) * | 2012-01-18 | 2013-07-24 | 上海算芯微电子有限公司 | Instruction branch pre-jump method and system |
| CN104423927B (en) * | 2013-08-30 | 2018-07-13 | 华为技术有限公司 | Command processing method and device, processor |
| WO2015027809A1 (en) * | 2013-08-30 | 2015-03-05 | 华为技术有限公司 | Instruction processing method and device, and processor |
| CN104423927A (en) * | 2013-08-30 | 2015-03-18 | 华为技术有限公司 | Method and device for processing instructions and processor |
| CN103984531B (en) * | 2014-05-30 | 2016-09-28 | 龙芯中科技术有限公司 | Overlength branch redirects processing method and processing device |
| CN104793921B (en) * | 2015-04-29 | 2018-07-31 | 深圳芯邦科技股份有限公司 | A kind of instruction branch prediction method and system |
| CN104793921A (en) * | 2015-04-29 | 2015-07-22 | 深圳芯邦科技股份有限公司 | Instruction branch prediction method and system |
| CN106293642A (en) * | 2016-08-08 | 2017-01-04 | 合肥工业大学 | A kind of branch process module and branch process mechanism thereof calculating system for coarseness multinuclear |
| CN106294276A (en) * | 2016-08-08 | 2017-01-04 | 合肥工业大学 | A kind of coarseness multinuclear that is applicable to calculates transmitter module and the working method thereof of system |
| CN106293642B (en) * | 2016-08-08 | 2018-10-02 | 合肥工业大学 | A kind of branch process module and its branch process mechanism for coarseness multinuclear computing system |
| CN106294276B (en) * | 2016-08-08 | 2018-11-06 | 合肥工业大学 | A kind of transmitting module and its working method suitable for coarseness multinuclear computing system |
| CN109710268A (en) * | 2017-10-25 | 2019-05-03 | 康烁 | Binary translation method and device towards VLIW framework |
| CN109710268B (en) * | 2017-10-25 | 2022-02-08 | 康烁 | VLIW architecture-oriented dynamic binary translation method and device |
| CN109101276A (en) * | 2018-08-14 | 2018-12-28 | 阿里巴巴集团控股有限公司 | The method executed instruction in CPU |
| US11579885B2 (en) | 2018-08-14 | 2023-02-14 | Advanced New Technologies Co., Ltd. | Method for replenishing a thread queue with a target instruction of a jump instruction |
| CN112613039A (en) * | 2020-12-10 | 2021-04-06 | 海光信息技术股份有限公司 | Performance optimization method and device for ghost vulnerability |
| CN112613039B (en) * | 2020-12-10 | 2022-09-09 | 成都海光微电子技术有限公司 | Performance optimization method and device for ghost vulnerability |
| CN113076136A (en) * | 2021-04-23 | 2021-07-06 | 中国人民解放军国防科技大学 | Safety protection-oriented branch instruction execution method and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101770358B (en) | 2013-01-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101770358B (en) | System and method for processing jump instruction of microprocessor in branch prediction way | |
| US5958041A (en) | Latency prediction in a pipelined microarchitecture | |
| KR100208889B1 (en) | Parallel processing device amd parallel processing method | |
| US5442757A (en) | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | |
| US7734897B2 (en) | Allocation of memory access operations to memory access capable pipelines in a superscalar data processing apparatus and method having a plurality of execution threads | |
| US8069340B2 (en) | Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions | |
| TWI552070B (en) | Execute at commit state update instructions, apparatus, methods, and systems | |
| JP3397081B2 (en) | Processor, data processing system and method for speculatively executing a conditional branch instruction using a selected one of a plurality of branch prediction schemes | |
| US5611063A (en) | Method for executing speculative load instructions in high-performance processors | |
| US20140189316A1 (en) | Execution pipeline data forwarding | |
| US9870226B2 (en) | Control of switching between executed mechanisms | |
| JP2018005488A (en) | Arithmetic processing unit and control method for arithmetic processing unit | |
| US6622240B1 (en) | Method and apparatus for pre-branch instruction | |
| JP2742374B2 (en) | Method and system for improving instruction dispatch efficiency in a superscalar processor system | |
| US8977837B2 (en) | Apparatus and method for early issue and recovery for a conditional load instruction having multiple outcomes | |
| US6862676B1 (en) | Superscalar processor having content addressable memory structures for determining dependencies | |
| US20140129805A1 (en) | Execution pipeline power reduction | |
| JP2815236B2 (en) | Instruction dispatching method for superscalar microprocessor and checking method for register conflict | |
| US9213547B2 (en) | Processor and method for processing instructions using at least one processing pipeline | |
| US20100100709A1 (en) | Instruction control apparatus and instruction control method | |
| US5903918A (en) | Program counter age bits | |
| CN112559048B (en) | Instruction processing device, processor and processing method thereof | |
| US8051275B2 (en) | Result path sharing between a plurality of execution units within a processor | |
| JP4996945B2 (en) | Data processing apparatus and data processing method | |
| US7472264B2 (en) | Predicting a jump target based on a program counter and state information for a process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100080 No. 10 South Road, Haidian District Academy of Sciences, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |
|
| CP03 | Change of name, title or address |